Introduction

Tunneling field effect transistors (TFETs) offer interesting opportunities to address two major challenges faced by aggressively scaled conventional CMOS technology: (i) the increasing difficulty in scaling the supply voltage (VDD) and (ii) minimizing the leakage currents that degrade the ION/IOFF switching ratio. Both of them lead to more power consumption in devices whereas we need exactly the opposite (energy efficiency) for wide-range deployment of ultra-mobile computation capability. As the transistor gate length is reduced, improved performance, requires the supply voltage, VDD and simultaneously the threshold voltage, VT, to be lowered to maintain a high overdrive factor (VDD – VT)1. Doing this, however, exponentially increases the ‘OFF’ state leakage current (IOFF) due to a physical limitation commonly referred to as the 60 mV/dec sub-threshold slope (SS) bottleneck. This is inherent in all current generation electronics that utilizes CMOS transistors with over-the-barrier charge transport physics.

Additionally, transistor off-state power dissipation is considered to be empirically proportional to1:

In order to reduce power consumption, reducing VDD is absolutely critical, which in turn demands devices with steep SS enabling faster turn on at low supply voltages. Contrary to classical MOSFETs, where charge carriers are thermally injected by lowering an energy barrier, the primary transport mechanism in a TFET is inter-band tunneling, where charge carriers transfer from one energy band into another at a heavily doped p+/n+ junction. In a TFET, inter-band tunneling can be switched “ON” and “OFF” abruptly by controlling the band bending in the channel region using gate-to-source bias, Vgs. This can be realized in a reverse-biased p-i-n structure, where asymmetric doping is used to suppress ambipolar transport1. While all-silicon TFETs have been studied rigorously using technology drive current boosters such as the use of a high-κ gate dielectric, abrupt doping profiles at the tunnel junction, ultra-thin body, higher source doping, a double gate, a gate oxide aligned with the intrinsic region and a shorter intrinsic region (and gate) length, ION of just 100 µA/µm have been achieved2. One of the more efficient ways to radically improve ION is by using a low band gap material as the source injector. Here, the smaller effective mass of charge carriers increases the tunneling probability, according to the triangular Wentzel–Kramer–Brillouin (WKB) approximation3,4. Potential source material candidates for N/PMOS TFETs are Germanium (Ge) and Indium Arsenide (InAs), respectively. Simulation studies using the above materials in a hetero-structure have shown ION values of 244 µA/µm and 83 µA/µm for Ge and InAs NTFET and PTFET, respectively, which corresponded to ION enhancements by factors > 400× and > 100×, respectively, over their all-Si planar counterparts1. Combining this with new and unique non-planar architectures opens up new opportunities for TFETs that are on-par with traditional Boltzmann transistors. Table 1 summarizes some recent state-of-the-art III-V source TFET demonstrations.

Table 1 Summary of state-of-the-art III-V TFET demonstrations
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We have recently shown the unique advantages of vertical nanotube architecture with core-shell gates for improved drive current capability compared to nanowires on silicon. Inspired by carbon nanotubes, the nanotube architecture mimics the gate all-around nanowire (GAA NW) devices by having an outer (shell) gate, as well as, an inner (core) gate inside the nanowire making it a hollow cylindrical structure. When compared to arrays of nanowires, the nanotube architecture outperforms in terms of drive current capability, CV/I metric (i.e. intrinsic gate delay), power consumption and area efficiency5,6,7,8. In this paper we present a hetero-structure Si/InAs p-channel TFET device concept that combines the advantages of a low band-gap source injector and inherent high drive current advantage in NTFET (Figure 1).

Figure 1
figure 1

Schematic of the Nanotube (NT) architecture.

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Tunneling in TFET devices is governed by the inter-band tunneling probability across the tunneling barrier, which is typically calculated using WKB approximation9:

Where m* is the effective mass, Eg is the band gap, λ is the screening tunneling length and ΔΦ is the potential difference between the source valence band and channel conduction bands. From this simple triangular approximation, we can see that that the band gap (Eg), the effective carrier mass (m*) and the screening tunneling length (λ) should be minimized to increase the tunneling probability. While Eg and m* are material dependent parameters, λ depends on other parameters such as the device geometry, doping profiles and gate capacitance. A small λ value would result in a strong modulation of the channel bands by the gate1. It has been shown that the highest tunneling rate and hence lowest λ values were found for the gate-all-around (GAA) architecture for a 10 nm diameter nanowire, while ultra-thin body (UTB) double gate FETs has shown comparatively higher λ values10. Planar UTBs have the highest λ values10. Because λ is also sensitive to gate capacitance, tunneling probability can also be enhanced by using high-κ gate dielectrics, as well as, small channel body thickness. Also, the abruptness of the doping profile at the tunnel junction is also important to control ΔΦ. In order to minimize the tunneling barrier, the high source doping level must fall off to the intrinsic channel in as short a width as possible. Typically this requires a change in the doping concentration of about 4–5 orders of magnitude within a distance of only a few nanometers1.

With the above in mind, we hypothesize that the nanotube TFET’s excellent electrostatic control would enable steep turn on characteristics, while maintaining low IOFF values comparable to NW TFET. This transistor architecture in conjunction with a low band gap source material in a hetero-structure configuration would enable a higher inter-band tunneling rate, when compared to all-silicon TFET structure. For this reason, InAs was chosen as a source material, for a p-type TFET application, since theoretically it has a band gap of 0.385 eV and electron effective mass of 0.026 mo11. Also, a recent experimental demonstration of InAs NW on Si(111) has shown the possibility of growing NW without misfit dislocation for diameters less than 20 nm, which is attributed to the reduction of strain field owing to the nanometer-scale footprint of NW12. The authors found that the hetero-structure with small diameter NW possesses fewer misfit dislocations, which quantitatively suppress trap assisted tunneling via dislocation levels and has pure band-to-band tunneling as the dominant tunneling process. The highest InAs normalized current by the same group is 0.5 mA/µm for n-type using p+ Si source and Zn doped n+ InAs channel12.

Results

(Figure 2) shows the energy band diagram of the simulated p-channel nanotube TFET. (Figure 3(a)) compares the normalized Ids-Vgs characteristics of a 10 nm thin NTFET (with 100 nm inner core-gate diameter, CGdia) and 10 nm diameter NWFET at Vdd = 1V. Transfer characteristics at lower supply voltages are shown in Supporting Figure S113. We have used the NW circumference (πd), where d is the NW diameter, in the case of the NT we have used average circumference , where CGdia and NTw are the nanotube core-gate diameter and thickness respectively. As it can be seen the nanotube architecture has 5× higher normalized current output than that of the GAA NW architecture. Both architectures provide ION/IOFF of more than 105. We have compared threshold voltage, VT, values for both devices and they were −0.58V and −0.63V for the NT and NW TFETs, respectively, showing a difference of 0.05V, using the constant current method defining VT at a normalized current of Ids = 10−7A/μm14. However, we have also used the proposed threshold definition by Boucart et al. arguing that TFET threshold voltages can be physically defined based on the saturation of the barrier width narrowing with respect to Vgs15. According to the new definition of threshold votlage, VTG, is the voltage at which the first derivative of the transconductance, gm, shows a maxima with respect to Vgs15. We have found that VTG = −0.73 and −0.72V for the NT and NW TFETs, respectively, which shows that the two devices have similar threshold voltage values. Both threshold voltage extraction methods are shown in Supporting Figure S2. So, this confirms the fairness of the comparison as both devices show similar normalized IOFF and VTG values.

Figure 2
figure 2

Band diagram of the P-type nanotube architecture TFET showing both ON state OFF states.

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Figure 3
figure 3

(a) Normalized Ids-Vgs characteristics of a 10 nm diameter NW and 10 nm thin NT p-channel TFETs; and (b) Sub-threshold Slope (SS) for the NT and NW TFET showing sub 60 mV/dec for more than 5 orders of magnitude of current.

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Figure 3(b) compares the SS values of the 10 nm NT and NW FETs. Both architectures show SS values less than 60 mV/dec over 5 decades1. However, the NW architecture TFET shows lower point SS values as low as 25 mV/dec, while the lowest SS values for the NTFET is ~ 40 mV/dec. We have shown before in the past this is due to the ultimate electrostatic control in the GAA architecture6. However, smaller drain bias has been experimentally reported to yield lower point and average SS16, as is also shown in Supporting Figure S3 at Vds = −0.8V, where the NT TFET shows a minimum point SS of 22 mV/dec and the NW TFET shows a minimum if 23 mV/dec. The reason for this is that lower Vds provides in principle lower ION min, the ION value at the knee of the SS swing, thus also the average SS slope would be reduced. We have also compared the non-normalized “ON” current of the 10, 20, 30 nm NW TFETs with the 10 nm NT TFET in (Figure 4(a)). The 10 nm NT TFET shows a non-normalized ION ~ 0.32 mA, while the NW TFETs show ION ~ 5.9×10−6A, 2.51×10−5A, 5.31×10−5A for the 10, 20 and 30 nm NWs, respectively. This means that the 10 nm NTFET shows 54×, 13× and 6× increase in drive current over that of the 10, 20 and 30 nm diameter NW TFETs. As for SS, (Figure 4(b)) shows that only 10 and 20 nm NW TFET and the 10 nm NT TFET can achieve sub 60 mV/dec SS. So, having a small diameter NW is essential to maintain a low SS.

Figure 4
figure 4

(a) Transfer (Ids-Vgs) characteristics of NWs of 10, 20, 30, 40 and 50 nm diameter and 10 nm NT; and (b) SS comparison between 10 nm thick NT and 10, 20 and 30 nm diameter NW TFETs.

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Discussion

In order to supply high drive current while maintaining small SS, arraying small diameter NWs is inevitable. However, this would come at the expense of chip area and off-state leakage as will be seen the following sections. Additionally, the low “OFF” current characteristic of the TFET would be lost as arraying would cause, at the least, multiplying the “OFF” state leakage current by the number of NWs in the array needed to supply the same “ON” current as one NT. Therefore, in the case of 54 NW array of 10 nm diameter NWs, the leakage would be at least 13× higher compared to a single 10 nm NT. Finally, although it could be argued that arraying could boost the “ON” current value, sensitivity of parameters like threshold voltage, for example, variations in NW width could lead to degradation of the SS swing for a large array of devices17. Recent demonstrations of sub 60 mV/dec of have been for all silicon single NW p and n-type TFET of diameter < 20 nm which supplies a maximum ON current in the nA regime and a normalized “ON” current of 1.2 µA/µm18,19. However, when an array of TFETs is tested sub 60 mV/dec SS have been demonstrated for currents as low as 0.01 µA/µm20. Also, degraded SS slope was noticed for higher drain current giving a maximum ION = 64 μA/μm at VDD = 1.0 V and at a higher gate bias VGS = 2 V. On the other hand, a SS of 52 mV/dec have been shown at an even higher ION = 100 μA/μm at VDD = 1.0 V and Vgs = 1 V for all-silicon single gated SOI based TFETs with vertical self-aligned top gate structure supplying and for 70 nm thick SOI with 2 nm Effective Oxide Thickness (EOT)21. Even higher drain currents have been shown for double gate strained-Ge hetero-structure TFET with a drive current of 300 μA/μm at a SS of 50 mV/dec22. That is why we think the NT architecture could be an excellent candidate for as a vertical structure that resembles double gate structure and could provide a higher integration density compared to the NW structure.

To consider the scalability of the nanotube architecture, we studied the non-normalized drain current as a function of the inner core-gate diameter (Figure 5(a)). An important observation here is that the core-gate contact scaling tunes the on-state drive performance without compromising the sub-threshold swing, as can be seen from (Figure 5(b)). This becomes a competitive technology option compared to GAA NWFETs. To fully comprehend this concept, consider the top-down plan-view chip layout perspective of a single nanotube and an array of GAA nanowires. (Figure 6(a)). In vertical GAA nanowire technology, maintaining a small nanowire pitch (NWpitch) ensures high integration density and drivability. In order to compete with this, the core-gate diameter (CGdia) of the nanotube should be highly scalable just like the nanowire pitch. One pragmatic approach to investigate this is by studying the device dimension scalability effects on chip area. Using the 2013 International Technology Roadmap for Semiconductors (ITRS) Overall Roadmap Technology Characteristics (ORTC), scalable parameters for current generation FinFET technology are adapted here, which are summarized in Table 2. In this comparison, the nanowire pitch is assumed to be equal to the fin half-pitch and the nanotube core-gate diameter is assumed to be equal to contact/via size as specified in the 2013 ORTC target for future technology nodes. The contact/via size scaling is considered equal to the M1 metal half-pitch. The other parameters in the comparison are the nanowire diameter (NWdia) and the nanotube thickness (NTw), both of which are assumed equal to the fin width target given in Table 2. From (Figure 4(a)), a 100 nm core-gate diameter, 10 nm thin InAs/Si nanotube has greater than 10× higher non-normalized drive capability compared to a single 10 nm diameter GAA InAs/Si nanowire. To achieve similar performance levels as the nanotube, more than 10× nanowires need to be stacked in an array. Using the above parameters and assuming that the normalized drive current scales linearly with channel thickness (NTw and NWdia) in both the nanotube and nanowire architecture, chip-area estimates of the single nanotube and a 10× nanowire array are carried out at different technology nodes using simple analytical calculations. As it can be seen from (Figure 6(b)), the contact/via scaling at the moment is comparable to the nanowire-pitch. But at around the 7 nm technology node (2017), the pitch scaling will start to become more aggressive. However, even after this and considering the fact that large nanowire arrays are required to achieve similar drivability as a single nanotube, the InAs/Si nanotube architecture will outperform InAs/Si GAA nanowire arrays at the extreme scaling limit in terms of chip area consumed.

Table 2 2013 ITRS ORTC FinFET SCALING PARAMETERS
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Figure 5
figure 5

Non-normalized NT drive current (a) and SS (b) as a function of inner core gate diameter.

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Figure 6
figure 6

(a) Illustrated top-down plan-view comparison of between; and (b) chip area comparison using ITRS predicted parameters between a single nanotube device and an array of 10 × GAA nanowires.

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We also compared the BTBT generation rate of both the 10 nm nanotube and 10 and 20 nm GAA NW TFETs in (Figure 7(a)). Color maps of BTBT generation rate and SRH Recombination rate of the 10 nm NT, 10 nm NW and 20 nm NW TFETs are provided in Supporting Figures S4, S5 and S6, showing the cross sections in the middle of the channel along which we made the measurements. The 10 nm diameter nanowire shows a slightly higher peak BTBT generation of 1.6×1032 (cm−3s−1), when compared to the 10 nm thick nanotube, showing ~1.5×1032 (cm−3s−1), due to the shorter tunneling length, λ, for the nanowire architecture. Similar peak BTBT generation rate is expected as it has been theoretically shown that the differences in the scaling tunneling length, λ, between the GAA and double gate architectures, which resembles the NT Core-Shell gates architecture,reduces for body thickness ≤ 10 nm and almost diminishes for body thickness of 5 nm10. On the other hand, the larger diameter nanowire (20 nm) shows lower peak tunneling rate of 5.53×1031 (cm−3s−1) due to larger body thickness leading to higher tunneling length, λ, values. However, one major difference between the two architectures is the distance over which BTBT generation is significant away from the Si/InAs interface. For the case of the NT, we observe that BTBT generation rate is higher over a larger distance, almost 7 nm into the Silicon channel, when compared to both the 10 nm and 20 nm NW, as shown in (Figure 7(a)). This is an indication of higher lateral tunneling across the Si-InAs interface for the NT architecture when compared to the NW architecture, which could explain the higher normalized current. This reason for this is that when analyzing the band diagrams for the 10 nm NT and NW TFETs, shown in Figure S7, it was found that the gradient of the holes quasi Fermi level is higher for the NT TFET as we move from the Si/InAs interface into the Si channel. This is important since the BTBT tunneling is proportional to the valence band gradient, according to the mode used. So, a higher gradient corresponds to lower scanning tunneling length, λ. In addition, lateral tunneling is fundamentally limited by the inversion layer thickness of in the ‘ON’ state and thus is sensitive to the Channel/Source interface cross sectional area.

Figure 7
figure 7

(a) BTBT Generation Rate; and (b) SRH Recombination Rate for the 10 nm NT and 10, 20 nm NWs as function of the distance from the Si/InAs interface.

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On the other hand, the 10 nm NW TFET is shows higher BTBT generation rate when moving away from the interface into the InAs source, indicating higher vertical tunneling within the source, when compared to both the 10 nm NT and 20 nm NW TFETs. Although higher vertical tunneling is desired in hetero-structure TFETs for increasing the drive current23, it could also lead to higher Shockley-Reed-Hall (SRH) recombination in the small direct band gap InAs source. When analyzing the SRH recombination rate in (Figure 7(b)), it was found that the peak SRH recombination rate for the 10 nm NW is almost an order of magnitude higher than the 10 nm NT TFET, as well as, the 20 nm NW TFET. To get a quantitative sense of the effect of BTBT generation and SRH recombination rates on the drive current, we analyzed the integrated area under the curve for (Figure 7(a–b)). For the 10 nm NT BTBT generation curve, the area under the curve was found to be 8.4% higher than that of the 10 nm NW curve and 45% higher than that of the 20 nm NW curve. This can partially account for the larger non-normalized current seen for 10 NT TFET, 54×, compared to that of the 10 nm nanowire TFET. The nanotube has larger available cross sectional area for tunneling when compared to the 10 nm nanowire. Since a 100 nm core-gate diameter nanotube with 10 nm thickness has 44× the cross sectional area of a 10 nm nanowire. Hence, doing a back-of-the-envelope multiplication the extra 8.4% in volumetric band-band generation by the additional cross sectional area gives 47.7× the anticipated increase in the current. The area under the SRH recombination curve for the 10 nm NW 8.7× of that of the 10 nm NT and 12× of that of the 20 nm NW.This demonstrates the potential of the nanotube transistor architecture to radically enhance the drive current capability of tunnel FETs to values comparable to state-of-the-art CMOS due to both higher BTBT generation rate and lower SRH recombination rate when compared to NW architecture at the same body thickness.

We precluded discussion over the fabrication of nanotube TFET as it is out of the scope of this paper and can be found in our pertinent work. With the advent of III-V channel material growth on silicon12,24, the nanotube device formation using bottom-up approach is very much possible.

Conclusion

We have presented the advantages of nanotube architecture with inner/outer core-shell gates for hetero-structure (Si/InAs) TFET application, when compared to gate-all-around nanowire based TFETs. 3D device simulations have shown that a p-channel nanotube TFET is able to outperform nanowire arrays, while preserving chip area and at comparable SS values. We believe the nanotube architecture combined with hetero-structure III-V/IV material systems holds a great promise for high performance, ultra-low power consumer computing applications.

Methods

To study the benefits of a nanotube architecture over a nanowire on a hetero-structure Si/InAs TFET platform, 3D simulations of a NT (Figure 1) and GAA NW TFET using Synopsys™ using the dynamic nonlocal path BTBT model11,24,25. For this case, indirect BTBT model was assumed as Si is an indirect bandgap material. The tunneling path for this model is calculated as a straight line straight line with its direction opposite to the gradient of the valence band and ends conduction band. Both devices are compared for a gate length (Lg) of 20 nm. Silicon drain is p-doped with acceptor active concentration NA = 1×1020 cm−3, while an intrinsic channel is used. The InAs source was used with n-doping with donor active concentration ND = 1 × 1018 cm−3, both typical to the previously demonstrated device24. Both the nanotube thickness and nanowire diameter are kept at 10 nm. The gate metal in both devices has a work function of 4.53 eV and a nitride gate dielectric is assumed with an (effective oxide thickness) EOT of 0.5 nm. A dynamic nonlocal band-to-band (BTB) tunneling model is utilized in conjunction with Shockley–Reed–Hall recombination and drift–diffusion physics. The band-to-band tunneling (BTBT) parameters, ‘A’ and ‘B’ for silicon are 4 × 1014 cm−3 s−1 and 1.9 × 107 V cm−1 respectively24,25. While for InAs the BTBT parameters were taken as 9 × 1019 cm−3 s−1 and 1.3×106 V cm−1 respectively11.

This comparative simulation study does not include any gate overlap with the source, assumes an ideal interface with no defects due to strain and takes into account trap-assisted tunneling due to dopants induced defect levels. However, it does not take into account bandoffsets due to strain, quantum confinement effects and multiple valley BTBT effects. The dynamic nonlocal BTBT model uses the Kane two-band model which is a simple two-band model capable of including one conduction band and one valence band and it is formulated as two coupled Schrodinger-like equations for the conduction-band and valence-band envelope functions. The coupling term is treated by the k•p perturbation method, which gives the solutions of the single electron Schrodinger equation in the neighborhood of the bottom of the conduction band and the top of the valence bands, where most of the electrons and holes, respectively, are concentrated. The valence band and conduction band dispersion relationship are assumed to be bulk-like. This simulation framework has been previously utilized in the literature for simulating tunneling in hetero-structures for both Si/InAs Esaki diodes and TFETs11,25. The nanotube TFET has a silicon channel thickness of 10 nm and an inner core gate diameter (CGdia) of 100 nm. All contacts are assumed to be Ohmic with zero contact resistance.