In a significant step forward in complexity and capability for bottom-up assembly of nanoelectronic circuits, this study demonstrates scalable and programmable logic tiles based on semiconductor nanowire transistor arrays. The same logic tile, consisting 496 configurable transistor nodes in an area of about 960 μm2, could be programmed and operated as, among other functions, a full-adder, full-subtractor and multiplexer. The promise is that these logic tiles can be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.
- Hao Yan
- Hwan Sung Choe
- Charles M. Lieber