Delta-Sigma Modulation Techniques in Analog-to-Digital Conversion

Delta-sigma modulation is a cornerstone approach for high-resolution analogue-to-digital conversion, combining oversampling with active noise shaping to achieve superior signal fidelity. In these systems, the analogue input is fed into one or more integrators, a coarse quantiser and a feedback digital-to-analogue converter in a closed loop. The quantisation noise is pushed towards higher frequencies by designing the noise-transfer function, allowing in-band performance to be dramatically improved once the signal is decimated and filtered. Architectures range from first-order single-loop modulators suitable for low-power sensing to high-order continuous-time or discrete-time designs delivering multi-MHz bandwidths and sub-noise-floor resolution. Key practical challenges include finite amplifier gain, clock jitter, thermal noise, distortion and mismatches, which are addressed through integrator-sharing topologies, compensation techniques, digital calibration, sampling-noise cancellation and variation-aware circuit methods. Through co-design of analogue front-ends and digital back-ends, modern delta-sigma converters achieve figures of merit approaching fundamental thermodynamic limits, finding deployment in precision instrumentation, biomedical monitoring, wireless communications and the Internet-of-Things.

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Recent work on ultralow-power inverter-based modulators has demonstrated nanowatt-level single-bit delta-sigma converters optimised for wearable health monitors. By adopting a switched-capacitor inverter amplifier and a three-tap FIR noise-shaping network, designers achieved peak SINAD above 77 dB while consuming under 100 nW, confirming robust performance under process variation without complex digital calibration.

Advances in digital reconstruction have introduced novel linear filters for incremental delta-sigma converters. The L2min2 family of filters and its symmetric variant improve quantisation and thermal noise suppression over classical CIC or cascade-of-integrators filters, reducing noise penalty factors to near unity and enabling lower oversampling ratios at a given resolution. Experimental prototypes in CMOS and FPGA validate these filters’ hardware friendliness and superior noise shaping in both first- and second-order systems.

Fully dynamic discrete-time converters employing floating inverter amplifiers and correlated level shifting have emerged as a means to raise integrator gain and cancel sampling noise without calibration loops. By integrating passive cascaded integrators and exploiting noise-cancelling techniques, these designs achieve SNDRs above 94 dB with oversampling ratios of 256 while consuming under 80 µW. Such architectures remove the need for static bias networks and demonstrate high stability across PVT corners.

Delta-Sigma Modulation Techniques in Analog-to-Digital Conversion publication trend

The graph below shows the total number of articles in delta-sigma modulation techniques in analog-to-digital conversion across all publications each year (not limited to Nature Index journals).

Technical terms

Delta-Sigma Modulation: A technique that oversamples the input and shapes quantisation noise to achieve high resolution within a target bandwidth.

Oversampling Ratio (OSR): The factor by which the sampling frequency exceeds twice the signal bandwidth, critical for noise reduction.

Noise Shaping: The process of filtering quantisation noise so that its power is transferred out of the signal band.

Decimation Filter: A digital filter that reduces the converter’s sample rate to the desired output rate while rejecting out-of-band noise.

Signal-to-Noise-and-Distortion Ratio (SNDR): A performance metric combining signal quality, noise and distortion into a single figure of merit.

References

1. L${}_{\text{2}}$min${}^{\text{2/2s}}$: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs. IEEE Transactions on Signal Processing (2023).
2. Ultralow-Power Inverter-Based Delta-Sigma Modulator for Wearable Applications. IEEE Access (2024).
3. A 79.2-μW 19.5-kHz-BW 94.8-dB-SNDR Fully Dynamic DT ΔΣ ADC Using CLS-Assisted FIA With Sampling Noise Cancellation. IEEE Transactions on Circuits & Systems II Express Briefs (2023).