Introduction

Power devices fabricated using wide-bandgap semiconductors such as SiC and GaN demonstrate better performance than those fabricated using the conventional semiconductor Si and normally off SiC or GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with an inversion channel have advanced power device technology1,2,3,4,5,6,7,8. Such power device technology enables an effective utilization of electric power for Shinkansens (bullet trains), airplanes, industrial equipment, medical equipment and so on. Diamond semiconductor has a strong potential for use in the field of high-power electronics because its breakdown electric field and thermal conductivity are higher than those of Si, SiC and GaN. Consequently, diamond-based transistors such as metal-semiconductor field-effect transistors (MESFETs), junction field-effect transistors (JFETs), hydrogen-terminated diamond MOSFETs (H-diamond FETs) and pnp bipolar junction transistors (pnp BJTs) have been developed9,10,11,12,13,14,15,16,17,18,19,20. However, diamond MOSFETs and insulated gate bipolar transistors (IGBTs) with inversion channels have not yet been developed. MOS gates with inversion channels enable a high control of electrical power due to their gate voltage control and the desired threshold voltage can be obtained by controlling the impurity concentration in the bodies. Achieving the desired threshold voltage for devices with an accumulation channel or devices that use the bulk as a channel, such as high-electron-mobility transistors (HEMTs), MESFETs, JFETs and H-diamond FETs, is difficult. Therefore, the normally off characteristics of MOSFETs with an inversion channel are more advantageous than the characteristics of devices with an accumulation channel or devices that use the bulk as a channel when such devices have conduction carrier supplied by the same semiconductor type at their control gate. In addition, in the case of wide-bandgap semiconductor devices, reducing channel resistance is important because the on-resistance of the devices is largely limited by the channel resistance due to the suppressed drift layer resistance. MOSFETs can considerably reduce the channel resistance per unit area when fabricated with a trench gate structure to widen the channel width (Wch), although the Wch of two dimensional channel devices such as HEMTs cannot be widened without increasing the surface area. Moreover, the carrier density of an inversion channel is higher than that of the bulk because wide-bandgap semiconductors have large ionization energies of acceptor and donor impurities.

Because of the aforementioned advantages of MOSFETs, those fabricated with an inversion channel are expected to draw out the maximum performance of semiconducting diamond and represent a substantial advancement in the field of diamond power devices. Therefore, the realization of diamond MOSFETs with an inversion channel is a long-standing research topic. Although diamond MOS capacitors with boron-doped p-type diamond bodies have been reported21,22,23,24,25, the inversion channel diamond MOSFETs have not yet been reported. Here, we fabricated diamond MOSFETs with a phosphorus-doped n-type diamond body by wet annealing for controlling the MOS interface. In this study, we adopted an n-type diamond body. Here, n-type diamond was selected as a body because its upward bending ability will be advantageous in the inversion mode of FET operation and the band offset of Al2O3/O-terminated diamond (111) is higher for holes (1.34 eV) than electrons (0.56 eV)24,26. We operated diamond p-channel MOSFETs with an inversion channel; these diamond MOSFETs exhibit normally off characteristics, clear saturation characteristics and high on/off ratios. We expect the results of this study to represent a major breakthrough in diamond power device technology.

Results

In this study, we fabricated diamond MOSFETs using phosphorus-doped n-type diamond as the body, as shown in Fig. 1. Before the deposition of the Al2O3 layer, we terminated the surface of the n-type diamond body with OH by wet annealing to fabricate a high-quality Al2O3/O-terminated diamond interface22.

Figure 1
figure 1

(a) Schematic cross-sectional structure and (b) top-view optical image of Al2O3/diamond MOSFET with n-type body. Schematic structure in (a) is cross-sectional view along red broken line in (b). S, D and G are source, drain and gate contacts, respectively.

Full size image

Figure 2 shows the drain current (Id) and drain voltage (Vds) characteristics at gate voltages (Vg) ranging from 0 to −12 V with a voltage step of −1 V, gate length (Lg) of 5 μm and gate width (Wg) of 150 μm for a diamond MOSFET at room temperature. The MOSFET shows normally off and clear saturation characteristics. Id can be well modulated by controlling Vg. Maximum Id and drain conductance were −247 μA (drain current density: −1.6 mA/mm) and 110 μS (0.73 mS/mm), respectively. Off Id was less than 10−14 A at Vg = −2 V. Therefore, Id on/off ratios greater than 10 orders of magnitude were obtained at room temperature. By controlling Vg, 33 of 42 MOSFETs modulated Id. We also succeeded in controlling Vg in diamond p-channel MOSFETs using another diamond substrate.

Figure 2
figure 2

Id–Vds characteristics of diamond MOSFET with Lg = 5 μm and Wg = 150 μm at room temperature.

Applied Vg and Vds range from 0 to −12 V with a voltage step of −1 V and from 0 to −5 V with a voltage step of −0.1 V, respectively.

Full size image

We determined transfer characteristics in the linear region of the Id–Vg curve for this MOSFET to obtain the field-effect mobility (μFE), subthreshold swing (SS) and threshold voltage (VT). Figure 3 shows Id in the linear scale and transfer conductance gm vs Vg characteristics at a low drain voltage (Vds = −0.1 V) and Vg from 0 to −12 V with a voltage step of −0.1 V for a diamond MOSFET with Lg = 5 μm and Wg = 150 μm at room temperature. The maximum gm was 4.5 μS (30 μS/mm) at Vg = −10.7 V. VT was 6.3 V, as determined from the fitting of the Id–Vg curve in the Vg range from −7 to −9 V. μFE was estimated using the following equation:

Figure 3
figure 3

Id and gm in linear scale vs Vg of diamond MOSFET with Lg = 5 μm and Wg = 150 μm at room temperature.

Applied Vg ranges from 0 to −12 V with a voltage step of −1 V and Vds is a constant value of −0.1 V.

Full size image

where Lch is the channel length and Cox is the gate oxide capacitance (ε of Al2O3: 7.3)22. Maximum μFE was 8.0 cm2/Vs. Figure 4 shows Id and the gate current (Ig) in the logarithmic scale vs Vg characteristics at Vds = −0.1 V and Vg from 0 to −12 V with a voltage step of −0.1 V for a diamond MOSFET with Lg = 5 μm and Wg = 150 μm at room temperature. Gate leakage current values were 27 pA/mm at Vg = −9 V and 110 nA/mm at Vg = −12 V. SS is estimated using the following equation:

Figure 4
figure 4

Id and Ig in logarithmic scale vs Vg of diamond MOSFET with Lg = 5 μm and Wg = 150 μm at room temperature.

Applied Vg ranges from 0 to −12 V with a voltage step of −1 V and applied Vd is a constant value of −0.1 V.

Full size image

where k is the Boltzmann constant, q is the electronic charge, CD («Cox) is the depletion layer capacitance, Dit is the interface-state density and Cit (=qDit) is the associated capacitance27. The values of SS and Dit were deduced to be 380 mV/dec (from the fitting of the Id–Vg curve in the Vg range from −3.0 to −3.5 V) and approximately 6 × 1012 cm−2 eV−1, respectively.

Discussion

In general, the inversion channel is checked using the C-V measurements of the MOS capacitor configuration. For wide-bandgap semiconductors even in SiC28, it is difficult to directly measure the inversion capacitance because the opposite carriers are barely excited beyond the bandgap energy. Therefore, we have demonstrated the creation of the inversion channel layer via FET operations with normally off characteristics. When the gate bias was negative, the valence band minimum of the n-type diamond near the gate insulator bend upwards across to the bulk Fermi energy. Holes in the p+-type source area can move into the n-type body as minority carriers and towards opposite p+-type drain areas, indicating the p-type inversion channel. This observation of Id with normally off characteristics is the direct evidence of a p-type inversion channel layer.

The MOSFETs exhibit a high drain current density compared with previously reported diamond JFETs (0.48 mA/mm) and MESFETs (0.06 mA/mm). This is because of the high bulk resistances of JFETs and MESFETs resulting from the large ionization energies of acceptor (EA: 370 meV) and donor (ED: 570 meV) impurities for diamond10,11. To obtain a high drain current density, i.e., a low on-resistance, the improvement of μFE is necessary. μFE of the present diamond MOSFETs with an inversion channel was 8.0 cm2/Vs. Electron μe and hole mobility μh of diamond bulk are greater than 3,000 cm2/Vs at room temperature (μe = 7,300 and μh = 5,300 cm2/Vs by time-resolved cyclotron resonance and μe = 4,500 and μh = 3,800 cm2/Vs by time-of-flight)29,30. Generally, when a high-quality MOS interface is used, μFE of approximately one half of μe and μh can be obtained in the case of Si MOSFETs. Therefore, μFE greater than 1,000 cm2/Vs is expected in diamond MOSFETs. Present μFE is lower than this ideal value because Dit was very high (~6 × 1012 cm−2 eV−1) for the present Al2O3/n-type diamond body. Figure 5(a,b) show a transmission electron microscopy (TEM) image of the MOS structure under the gate voltage and an atomic force microscopy (AFM) image of the phosphorus-doped n-type diamond body surface. As shown in Fig. 5(a), although the Al2O3 layer and n-type diamond body interface appears smooth, the interface exhibited a dark line because the n-type diamond body had some bunching steps across the channel region similar to those shown in Fig. 5(b). Bunching steps cause high Dit because these steps are not (111) surfaces and are not perfectly OH terminated. Therefore, this partial non-OH termination surface occurs low μFE. Atomically flat surface that we previously succeeded is important for reducing Dit and improving μFE31. In addition, the quality improvement of the phosphorus-doped n-type diamond body is important for obtaining high μFE. The fabrication of high-quality phosphorus-doped n-type diamond bodies is a critical issue in the diamond semiconductor field.

Figure 5
figure 5

(a) TEM image of Al2O3/diamond interface. (b) AFM image of surface of n-type diamond body.

Full size image

In this study, we could not measure the breakdown voltage of the diamond MOSFETs because Vds concentrated at Al2O3. Introducing a lightly doped layer as an active layer between Al2O3 and the drain region should result in a high breakdown voltage. This issue is a topic for further investigation.

The present diamond MOSFETs provide a possible path in the realization of ultimate high-power devices.

Methods

Sample preparation

Figure 1(a,b) show a schematic cross-sectional structure and top-view optical microscopy image of the planar diamond MOSFET. First, an n-type body was deposited onto a high-pressure, high-temperature (HPHT) synthetic Ib (111) semi-insulating single-crystal diamond substrate by microwave plasma-assisted chemical vapor deposition (CVD). During the growth of the n-type body, the methane concentration, plasma power and chamber pressure were 0.4%, 3.6 kW and 150 Torr, respectively. The thickness and phosphorus concentration of the deposited n-type body were ~10 μm and ~1 × 1017 cm−3, respectively. Second, a selective p+-type layer was grown on the n-type body through a metal mask (Ti/Au: 10 nm/200 nm) by microwave plasma-assisted CVD. During the growth of the p+-layer, the methane concentration, plasma power and chamber pressure were 0.2%, 1200 W and 50 Torr, respectively. The thickness and boron concentration of the selective deposited p+-type layer were ~50 nm and ~1 × 1020 cm−3, respectively. Third, the sample was annealed in a quartz tube in an electric furnace at 500 °C for 60 min to obtain stable OH surface terminations22. The wet annealing was performed under an atmosphere of N2 gas bubbled through ultrapure water. The flow of the N2 gas was 400 sccm. An Al2O3 layer was then deposited onto the sample by atomic layer deposition (ALD) at 300 °C. The thickness of the Al2O3 layer was 34 nm. After the deposition of the Al2O3 layer, the termination of the diamond surface changed from OH to O, same as that in the ALD mechanism. The gate, drain and source electrodes (Ti/Pt/Au: 30 nm/30 nm/100 nm) were fabricated by photolithography and lift-off, as shown in Fig. 1(b). Lg and Wg were 5 μm and 150 μm, respectively. As determined from transfer length model patterns on the same substrate, the contact resistance of the Ti/p+-type diamond interface was 2.9 × 10−6 Ωcm2 and the leakage current level was less than the detection limit (<10−14 A at ±5 V) for the lateral n-type body and Al2O3 layer.

Characterization

The current–voltage (I–V) characteristics of the MOSFETs were measured using a parameter analyzer (KEITHLEY 4200-SCS). The I–V measurements were conducted at room temperature in air. AFM measurements were performed using a scanning probe microscope (SHIMADZU SPM-9700). The measurements were conducted in the contact mode over a scanning area of 10 × 10 μm2 using a Si cantilever (Hitachi High-Tech Science Corp. SI-DF20). Cross-sectional TEM images were obtained using TEM system of JEOL JEM-ARM200F operated at an acceleration voltage of 14.5 keV.

Additional Information

How to cite this article: Matsumoto, T. et al. Inversion channel diamond metal-oxide-semiconductor field-effect transistor with normally off characteristics. Sci. Rep. 6, 31585; doi: 10.1038/srep31585 (2016).