Introduction

The usage of renewable energy sources (RESs) is becoming more common and crucial as a result of the fast-rising demand for electrical energy and the expanding use and higher production costs of fossil fuel-based energy resources. One of the renewable energy sources, photovoltaic (PV) energy, has experienced rapid development during the past few decades. PV sources' output power and voltage are variable, nonlinear, and dependent on the surrounding temperature, solar radiation levels, and load values1. To connect the PV sources to the electricity grid and obtain the maximum energy possible from these sources under different operating conditions, high step-up voltage DC/DC converters with greater efficiency are used to emphasize the right tracking of the maximum power and lift the low PV voltage level to proper DC levels needed for inverters2. DC/DC boost converters are used for a variety of practical applications, which require high levels of DC voltage with small input current ripples3. One of the most important of these applications is RESs. The traditional DC/DC boost converter includes four components: a power switch, diode, input inductor, and output capacitor. It has a simple structure with a low price, and it is characterized by a non-pulsating input current in the continuous conduction mode (CCM) operation4. Nevertheless, the main disadvantages of this converter are extreme conduction losses, severe switching stresses, excessive input current ripples, and rising electromagnetic interference (EMI). Additionally, it is improper for applications that need raising voltage gains.

Many research efforts have been done to get further voltage gain without working at an extreme duty ratio and to remedy the abovementioned issues5. An interleaved DC/DC boost converter was introduced in6. It used two standard boost converters connected in parallel. The reliability of the interleaved converter based on the Markov standard was presented in7. To minimize the ripples of the input current, the switching losses and EMI levels, different PWM control schemes were introduced in8, and another control structure based on a look-up table was stated in9. However, they have problems with isolating gate signals and increasing the cost. Moreover, the voltage gain was identical to the conventional converters10. Interleaved boost converter based on a voltage doubler was used11. Another control method by combining alternating phase shift control and customary interleaving PWM control for the interleaved converter was proposed in12. A six-phase interleaved DC/DC converter with switched capacitor voltage multiplier cells was listed in13. These structures confirmed low current ripples, large voltage gain, and balancing of voltage capacitors. However, the main issues were the duty cycle restriction and rising cost. An assortment of DC/DC boost converters based on a switched capacitor was suggested in14 and a switched capacitor/inductor was hired in15. High voltage gain was satisfied, but they have large conduction losses, serious switching stresses, and circuit complexity. In16, a cascaded boost converter was used with high-voltage gain, and low switching losses, and current ripples. However, shortcomings were noted such as rising cost, decreased efficiency, and complexity of the control system.

Different topologies in the literature were introduced for realizing high-voltage gain such as coupled inductor/capacitor converter17, voltage-cl amped coupled inductor converter18, a standard boost in series with flyback converter19, and classic converter with a coupled inductor and a voltage lift cell20. Nevertheless, several issues like lowest efficiency, adding EMI levels, pulsing input current, high price, and complexity of the drive circuit are noted. To decrease the output diode voltage stress of the flyback cell and improve the efficacy, a coupled inductor boost combined flyback converter was suggested in21. However, a snubber circuit is needed to absorb the surges across the main power switch. A DC/DC converter that used voltage multiplier cells of capacitor-inductor-diode with a voltage lift circuit to boost the voltage gain was introduced in22. High voltage gain and low switches voltage stresses were accomplished. Unfortunately, because the main switch is connected in series with the input DC source, the input current is discontinuous. Therefore, the circuit is not appropriate for renewable energy applications such as PV applications. The converter efficiency decreased as the number of cells increased because each cell is made up of four components, making it suitable only for low-power applications. Quasi Z-source converters23, quasi-Y-source converters24, and hybrid Z-source boost converters25 were also founded. Two cascaded Z-source boost converters were proposed in26, which took the advantage of cascaded technique and impedance source converters. These topologies attained high voltage gain at a small duty ratio and continual input current. But they have a limited duty cycle, excessive stresses on the active switch, and complex drive circuit. A hybrid topology was presented in27,28 integrated the coupled inductor and switched capacitor to achieve higher voltage gain. Nonetheless, the copper loss and the main switch voltage stress were raised by rising the turns ratio of the coupled inductor. A DC/DC converter based on quad switched inductor was studied in29 to accomplish high voltage gain. However, this converter has a lot of components, which reduces the efficiency, and raises the cost and the size of the circuit. Another DC/DC converter based on the voltage multiplier structure was introduced in30. High voltage gain and high efficiency can be achieved, but the converter has some drawbacks for example high voltage stress on the main switch, and is suitable only for low voltage low power applications.

This article offers a new high voltage gain non-isolated DC/DC boost converter to improve the abovementioned problems. This converter uses a reduced number of passive components. It has the following features: control simplicity, high output voltage gain, and small voltage stress across the power switch and diodes. Furthermore, cascading additional cells can be offered to have a very high voltage gain. The circuit description and modes of operation are described in detail. The steady-state process of the proposed converter is studied. The voltage gain derivation in CCM is evaluated. The voltage stresses across the power switch, diodes, and capacitors are derived. Power losses and efficiency are derived based on the equivalent model for the suggested topology circuit with parasitic elements. The experimental results and comparative analysis are given to confirm the success of the proposed converter.

The proposed topology in this paper differs from the circuit in22, which uses the main switch connected in series with the input DC source. Consequently, the input current is discontinuous which causes constraints for PV applications. Also, each cell of this circuit in22 consists of four components, then, the converter efficiency decreased as the number of cells increases. So, it is suitable only for low-power applications. The current work also differs from the circuits in23,24,25,26 which employ Quasi Z-source, quasi-Y-source, hybrid Z-source, and two cascaded Z-source boost converters, respectively. Although these topologies attain high voltage gain with a low duty ratio and continuous input current. However, they have a limited duty cycle, high stresses on the active switch, and complex drive circuits.

The proposed converter and its steady-state investigation

Circuit description and modes of operation

The offered multi-cells DC/DC boost converter is shown in Fig. 1. To understand the operation of the proposed DC-DC boost converter, the circuit with two cells (n = 2) shown in Fig. 2 is analyzed. Each cell contains two passive elements (one inductor and one capacitor), and one diode.

Figure 1
figure 1

The multi-cells proposed DC-DC boost converter.

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Figure 2
figure 2

The two cells proposed DC-DC boost converter.

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The proposed circuit composes of one active power switch, four diodes, and five passive components. Under assumptions of the ideal power switch and diodes, and pure inductive and capacitive elements, steady state analysis of the two operation modes is discussed. The key waveforms of the two cells of the suggested converter are displayed in Fig. 3.

Figure 3
figure 3

Operating modes of proposed converter.

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Mode 1 (0 ≤ t ≤ DT)

Figure 4 shows the equivalent circuit during mode 1. As obvious SW, D1, D2, and D3 are ON, and Do is OFF. The currents (iL1, iL2) of the inductors (L1 and L2) increase linearly. The inductor’s voltage opposes the input dc voltage Vin. The capacitors C1 and C2 charge with a voltage nearly the same as Vin. The saved energy in the capacitor Co supplies the load. The equations of mode 1 can be obtained from Fig. 4b by applying KVL and KCL as follow:

$$V_{L1 - on} = V_{L2 - on} = V_{C1 - on} = V_{C2 - on} = V_{in}$$
(1)
Figure 4
figure 4

Equivalent circuit of Mode 1: (a) active and inactive elements, and (b) equivalent electrical circuit.

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The supply current during the switching-on period (is-on) is given by;

$$\left. \begin{gathered} i_{s - on} = i_{L1 - on} + i_{C1 - on} + i_{L2 - on} + i_{C2 - on} \hfill \\ i_{Co} = i_{o} \hfill \\ \end{gathered} \right\}$$
(2)

Mode 2 (DT ≤ t ≤ T)

Figure 5 displays the equivalent circuit during mode 2. It is noted that SW, D1, D2, and D3 are OFF, and Do is ON. The inductors’ voltages VL1 and VL2 are inverted, and the saved energy in the passive components L1, L2, C1, and C2 is transmitted to the load and Co. The equations of mode 2 can be obtained from Fig. 5b by applying KVL and KCL as follow:

$$V_{in} + V_{L1 - off} + V_{C1 - off} + V_{L2 - off} + V_{C2 - off} = V_{o}$$
(3)
Figure 5
figure 5

Equivalent circuit of Mode 2: (a) active and inactive elements, and (b) equivalent electrical circuit.

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The supply current during the switching-off period (is-off) is given by;

$$\left. \begin{gathered} i_{s - off} = i_{L1 - off} = i_{C1 - off} = i_{L2 - off} = i_{C2 - off} \hfill \\ i_{s - off} = i_{Co} + i_{o} \hfill \\ \end{gathered} \right\}$$
(4)

Voltage gain derivation and voltage stresses across the switch, diodes, and capacitors

The ripple of the inductor current iL1 during the switching-on interval is:

$$\Delta i_{{L_{1 - on} }} = \frac{{V_{in} }}{{L_{1} }}DT$$
(5)

where D is the duty ratio.

The ripple of the inductor current iL2 during the switching-on interval is:

$$\Delta i_{{L_{2 - on} }} = \frac{{V_{in} }}{{L_{2} }} DT$$
(6)

The ripple of the inductor current iL1 during the switching-off interval is:

$$\Delta i_{{L_{1 - off} }} = \frac{{( V_{o} - 4 V_{in} )}}{{L_{1} }} (1 - D) T$$
(7)

The ripple of the inductor current iL2 during this mode is:

$$\Delta i_{{L_{2 - off} }} = \frac{{( V_{o} - 4 V_{in} )}}{{L_{2} }} (1 - D) T$$
(8)

By using the volt-sec balance through the inductors L1 and L2, and from Eqs. (5) and (7);

$$\Delta i_{{L_{1} }} = \frac{{V_{in} }}{{L_{1} }} D T = \frac{{( V_{o} - 4 V_{in} )}}{{L_{1} }} (1 - D) T$$
(9)

Also, Eqs. (6) and (8) yield;

$$\Delta i_{{L_{2} }} = \frac{{V_{in} }}{{L_{2} }} D T = \frac{{( V_{o} - 4 V_{in} )}}{{L_{2} }} (1 - D) T$$
(10)

By solving Eqs. (9) or (10), the voltage gain can be found as follow:

$$\frac{{V_{o} }}{{V_{in} }} = \frac{{(4 - 3 D)}}{(1 - D)}$$
(11)

For steady-state operation, the charge on capacitors C1 and C2 should not change;

$$D T i_{C1 - on} = (1 - D) T i_{C1 - off}$$
(12)

and

$$D T i_{C2 - on} = (1 - D) T i_{C2 - off}$$
(13)

If each of the inductances L1 and L2 is large enough, IL1 is nearly equal to its average current IL1 and also, IL2 is nearly equal to its average current IL2.

For L1 = L2;

$$I_{L1} = I_{L2} = I_{L}$$
(14)

Then, from Eq. (4), we obtain

$$i_{s - off} = I_{L}$$
(15)

Also, by substituting from Eqs. (12), (13), and (14) into Eq. (2), one can obtain:

$$i_{s - on} = I_{L} + \frac{1 - D}{D}I_{L} + I_{L} + \frac{1 - D}{D}I_{L} = \frac{2}{D}I_{L}$$
(16)

The average supply current can be given as:

$$I_{s} = D i_{s - on} + (1 - D) i_{s - off}$$
(17)
$$I_{s} = 2 I_{L} + (1 - D) I_{L} = (3 - D) I_{L}$$
(18)

The voltage stresses across the switch, diodes, and capacitors respectively can be expressed as:

$$V_{SW} = \frac{{(3 - 2 D)}}{(1 - D)} V_{in}$$
(19)
$$\left. \begin{gathered} V_{D1} = V_{D2} = V_{D3} = \frac{{(3 - 2 D)}}{{2 (1 - D)}} V_{in} \hfill \\ V_{Do} = \frac{{(3 - 2 D)}}{(1 - D)} V_{in} \hfill \\ \end{gathered} \right\}$$
(20)
$$\left. \begin{gathered} V_{C1} = V_{C2} = V_{in} \hfill \\ V_{Co} = \frac{{(4 - 3 D)}}{(1 - D)} V_{in} \hfill \\ \end{gathered} \right\}$$
(21)

From this analysis, we can summarize the following:

For n = 1;

$$G_{1} = \frac{(2 - D)}{{(1 - D)}}$$
(22)

where G1 is the voltage gain at number of cells (n) = 1.

For n = 2;

$$G_{2} = \frac{{(4 - 3 D)}}{(1 - D)}$$
(23)

This equation can be written as;

$$G_{2} = \frac{{(2 - D)}}{(1 - D)} + 2$$
(24)

where G2 is the voltage gain at number of cells (n) = 2.

For n = 3;

$$G_{3} = \frac{{(6 - 5 D)}}{(1 - D)}$$
(25)

This equation can be written as:

$$G_{3} = \frac{{(2 - D)}}{(1 - D)} + 4$$
(26)

where G3 is the voltage gain at number of cells (n) = 3.

To generalize the formula based on number of cells (n), the voltage gain can be obtained according to the following formula for n ≥ 1.

$$G_{n} = \frac{{(2 - D)}}{(1 - D)} + 2(n - 1)$$
(27)

and the average supply current for any number of cells can be given as following:

$$I_{s} = ( n + 1 - D) I_{L}$$
(28)

The voltage gain of the proposed converter at different number of cells (n = 1, 2, and 3) is displayed in Fig. 6. It is obvious that the voltage gain has a higher value in comparison to the conventional DC-DC boost converter. Moreover, the proposed converter can be extended to get higher voltage gains by increasing the cascading additional cells.

Figure 6
figure 6

Voltage gain of the proposed boost converter at different number of cells (n = 1, 2 and 3) and the conventional one.

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Also, the voltage stresses across the switch, diodes, and capacitors for any number of cells can be expressed as:

$$V_{SW} = (G_{n} - 1) V_{in}$$
(29)
$$\left. \begin{gathered} V_{D1} = V_{D2} = V_{D3} = \frac{{(G_{n} - 1)}}{2} V_{in} \hfill \\ V_{Do} = (G_{n} - 1) V_{in} \hfill \\ \end{gathered} \right\}$$
(30)
$$\left. \begin{gathered} V_{C1} = V_{C2} = V_{in} \hfill \\ V_{Co} = G_{n} V_{in} \hfill \\ \end{gathered} \right\}$$
(31)

Design consideration

The design of inductors and capacitors is considered an important issue to guarantee the operation of the suggested circuit in CCM. Therefore, this part is presented to describe the design of these passive elements.

Inductor design

During Mode 1, the voltage across the inductor is provided by:

$$V_{L} = L\frac{di}{{dt}} = L\frac{{\Delta I_{L} }}{{\Delta t_{on} }}$$
(32)

The voltage across the inductor is the same as the input voltage. The inductance is defined by:

$$L = \frac{{V_{in} }}{{\Delta I_{L} }} D T = \frac{{V_{in} }}{{{(\% }r_{i} ) I_{L} }} D T$$
(33)

where %ri is the percent inductor current ripple allowed. The average value of the inductor current IL can be obtained from Eq. (18), then, substituting into Eq. (33), one obtains:

$$L = \frac{{D (3 - D)}}{{{(\% }r_{i} ) G_{2}^{2} }} R_{L} T$$
(34)

where RL is the load value. Then, the inductance value for any number of cells can be given from the following equation,

$$L = \frac{{D (n + 1 - D)}}{{{(\% }r_{i} ) G_{n}^{2} }} R_{L} T$$
(35)

Capacitor design

The current flowing through the capacitor C1 in 0 ≤ t ≤ DT period can be obtained from Eqs. (12) and (15) as ((1-D)/D)IL. Then, the capacitance value C1 can be derived as:

$$C_{1} \frac{{\Delta V_{C} }}{{D T}} = C_{1} \frac{{{(\% }r_{v} ) V_{in} }}{{D T}} = \frac{(1 - D)}{D} I_{L}$$
(36)

where %rv is the percent capacitor voltage ripple allowed in C1.

By substituting from Eq. (18) into Eq. (36), the capacitance value C1 can be obtained. In the same way, the capacitance value C2 can be derived. Hence,

$$C_{1} = C_{2} = \frac{{G_{2}^{2} T}}{{{(\% }r_{v} ) R_{L} }} * \frac{(1 - D)}{{(3 - D)}}$$
(37)

For any number of cells, the capacitance value of C1 and C2 can be given from the following relation:

$$C_{1} = C_{2} = \frac{{G_{n}^{2} T}}{{{(\% }r_{v} ) R_{L} }} * \frac{(1 - D)}{{(n + 1 - D)}}$$
(38)

The capacitor Co is charged in the period DT ≤ t ≤ T, hence,

$$C_{o} = \frac{{(1 - D) T}}{{\Delta V_{Co} }}* I_{{C_{o} }} = \frac{{(1 - D) T}}{{{(\% }r_{v} ) V_{Co} }}*(I_{L} - I_{o} )$$
(39)

By substituting from Eq. (18) into Eq. (39), the capacitance value Co can be obtained.

$$C_{o} = \frac{{(1 - D) T}}{{{(\% }r_{v} ) R_{L} }}*(\frac{{G_{2} }}{(3 - D)} - 1)$$
(40)

For any number of cells, the capacitance value of Co can be given from the following relation,

$$C_{o} = \frac{{(1 - D) T}}{{{(\% }r_{v} ) R_{L} }}*(\frac{{G_{n} }}{(n + 1 - D)} - 1)$$
(41)

Power losses and efficiency

The power losses of the two-cell for the proposed topology are estimated by calculating the switching losses and conduction losses. The power loss of each component is determined, then, the converter power losses can be investigated by summing all these parts. Also, the converter efficiency can be determined based on the power losses. The converter model with the parasitic elements is displayed in Fig. 7.

Figure 7
figure 7

Equivalent model for the proposed circuit with parasitic elements.

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For the computation of conduction losses in the converter, all diodes are considered with cut in voltages VD1, VD2, VD3, and VDo. Also, the internal resistances are rD1, rD2, rD3, and rDo. Each inductor L1 and L2 has a lumped DC resistance rL1 and rL2, respectively, and each capacitor C1, C2 and Co has an equivalent series resistance rC1, rC2, and rCo, respectively. Both conduction and switching losses are considered for the main switch with on-state resistance occupied as rsw.

The power switch losses

The practical power switch has conduction and switching losses. The switching loss is the sum of the conduction and switching losses and it can be written as:

$$P_{{loss (SW)}} = P_{{loss - conduction (SW)}} + P_{{loss - switching (SW)}}$$
(42)

where the conduction loss of SW can be stated as:

$$P_{{loss - conduction (SW)}} = i_{SWrms}^{2} *r_{SW}$$
(43)

The switch current can be obtained from Mode 1 and Eq. (16), then the rms value of the switch current can be established as:

$$i_{SWrms} = \frac{{2 V_{o} G}}{{R \sqrt D (3 - D)}}$$
(44)

Substituting from (44) into (43), then the power conduction loss can be determined by:

$$P_{{loss - conduction (SW)}} = \frac{{4 V_{o}^{2} G^{2} }}{{R^{2} D (3 - D)^{2} }}r_{SW}$$
(45)

The switching loss (Ploss-switching) of the power switch SW can be determined by:

$$\begin{aligned} P_{{loss - switching (SW)}} & = P_{{loss - switching (SW) - on}} + P_{{loss - switching (SW) - off}} \\ P_{{loss - switching (SW)}} & = \frac{{t_{on} *V_{SW} *i_{SW - on} *f_{S} }}{2} + \frac{{t_{off} *V_{SW} *i_{SW - off} *f_{S} }}{2} \\ P_{{loss - switching (SW)}} & = \frac{{(t_{rt} + t_{ft} )*V_{SW} *i_{SW - avg} *f_{S} }}{2} \\ \end{aligned}$$
(46)

where trt and tft is the rise time and fall time of the switch, respectively.

The average current of the switch current can be found as:

$$i_{SW - avg} = \frac{{2 G V_{o} }}{{R (3 - D)}}$$
(47)

Substituting from (19) and (47) into (46), then the power switching loss can be determined by:

$$P_{{loss - switching (SW)}} = \frac{{(t_{rt} + t_{ft} )*V_{o}^{2} *(3 - 2D)*f_{S} }}{{R (3 - D) (1 - D)}}$$
(48)

Then the switching loss of SW can be investigated by:

$$\left. \begin{aligned} P_{{loss - total (SW)}} & = \frac{{4 G^{2} V_{o}^{2} }}{{R^{2} D (3 - D)^{2} }}r_{SW} \\ & \quad + \frac{{(t_{rt} + t_{ft} )*V_{o}^{2} *(3 - 2D)*f_{S} }}{{R (3 - D) (1 - D)}} \\ \end{aligned} \right\}$$
(49)

The diodes losses

The diodes are supposed to have the same cut in voltages and equivalent series resistance, VD1 = VD2 = VD3 = VDo = VD ; rD1 = rD2 = rD3 = rDo = rD.

The total diodes losses can be stated as:

$$\left. \begin{aligned} P_{{loss - total (Diodes)}} &= P_{loss - D1} + P_{loss - D2} \hfill \\ &\quad + P_{loss - D3} + P_{loss - Do} \hfill \end{aligned} \right\}$$
(50)

where, the power loss of each diode can be determined by;

$$\begin{aligned} P_{loss - D1} & = V_{D} *i_{D1avg} + i_{D1rms}^{2} *r_{D} \\ P_{loss - D1} & = (2 - D) V_{D} *i_{L} + \frac{{(2 - D)^{2} }}{D}*i_{L}^{2} *r_{D} \\ P_{loss - D1} & = \frac{{(2 - D) G V_{o} V_{D} }}{{R (3 - D)}} + \frac{{(2 - D)^{2} G^{2} V_{o}^{2} }}{{R^{2} (3 - D)^{2} D}}*r_{D} \\ \end{aligned}$$
(51)
$$\begin{aligned} P_{loss - D2} & = V_{D} *i_{D2avg} + i_{D2rms}^{2} *r_{D} \\ P_{loss - D2} & = (1 - D) V_{D} *i_{L} + \frac{{(1 - D)^{2} }}{D}*i_{L}^{2} *r_{D} \\ P_{loss - D2} & = \frac{{(1 - D) G V_{o} V_{D} }}{{R (3 - D)}} + \frac{{(1 - D)^{2} G^{2} V_{o}^{2} }}{{R^{2} (3 - D)^{2} D}}*r_{D} \\ \end{aligned}$$
(52)
$$\begin{aligned} P_{loss - D3} & = V_{D} *i_{D3avg} + i_{D3rms}^{2} *r_{D} \\ P_{loss - D3} & = V_{D} *i_{L} + \frac{1}{D}*i_{L}^{2} *r_{D} \\ P_{loss - D3} & = \frac{{G V_{o} V_{D} }}{{R (3 - D)}} + \frac{{G^{2} V_{o}^{2} }}{{R^{2} (3 - D)^{2} D}}*r_{D} \\ \end{aligned}$$
(53)
$$\begin{aligned} P_{loss - Do} & = V_{D} *i_{Doavg} + i_{Dorms}^{2} *r_{D} \\ P_{loss - Do} & = (1 - D) V_{D} *i_{L} + (1 - D)*i_{L}^{2} *r_{D} \\ P_{loss - Do} & = \frac{{(1 - D) G V_{o} V_{D} }}{{R (3 - D)}} + \frac{{(1 - D) G^{2} V_{o}^{2} }}{{R^{2} (3 - D)^{2} }}*r_{D} \\ \end{aligned}$$
(54)

Then, the total power loss in the diodes can be determined by substituting from (51), (52), (53), and (54) into (50) as:

$$\left. \begin{aligned} P_{{loss - total (Diodes)}} &= \frac{{(5 - 3D) G V_{o} V_{D} }}{{R (3 - D)}} \hfill \\ &\quad + \frac{{(2 - D) G^{2} V_{o}^{2} }}{{R^{2} (3 - D) D}}*r_{D} \hfill \\ \end{aligned} \right\}$$
(55)

The capacitors losses

There are three capacitors are shown in the proposed topology. The total power loss due to the capacitors is given by:

$$\left. \begin{aligned} P_{{loss - total (Capacitors)}} &= i_{{_{C1rms} }}^{2} *r_{C1} + i_{{_{C2rms} }}^{2} *r_{C2} \hfill \\ &\quad+ i_{{_{Corms} }}^{2} *r_{Co} \hfill \end{aligned} \right\}$$
(56)

The three capacitors are assumed to has the same equivalent series resistance, rC1 = rC2 = rCo = rC.

The rms value of current through the capacitors and the power loss of each capacitor can be estimated using the expressions:

$$\left. \begin{gathered} i_{C1rms} = i_{C2rms} = \sqrt {\frac{(1 - D)}{D}} I_{L} \hfill \\ i_{Corms} = \sqrt {\frac{D}{(1 - D)}} I_{o} \hfill \\ \end{gathered} \right\}$$
(57)

Then,

$$\left. \begin{gathered} P_{loss - C1} = P_{loss - C2} = \frac{(1 - D)}{D} I_{L}^{2} *r_{C} = \frac{(1 - D)}{D} \frac{{G^{2} V_{o}^{2} }}{{R^{2} (3 - D)^{2} }}*r_{C} \hfill \\ P_{loss - Co} = \frac{D}{(1 - D)} I_{o}^{2} *r_{C} = \frac{{D V_{o}^{2} }}{{R^{2} (1 - D)}} *r_{C} \hfill \\ \end{gathered} \right\}$$
(58)

Substituting from (58) into (56), the total power loss due to the capacitors can be given by:

$$\left. \begin{aligned} P_{{loss - total (Capacitors)}} &= \frac{{2 (1 - D)}}{D} \frac{{G^{2} V_{o}^{2} }}{{R^{2} (3 - D)^{2} }}*r_{C} \hfill \\ &\quad + \frac{{D V_{o}^{2} }}{{R^{2} (1 - D)}} *r_{C} \hfill \end{aligned} \right\}$$
(59)

The inductors losses

The inductors loss can be expressed as:

$$P_{{loss - total (Inductors)}} = i_{{_{L1rms} }}^{2} *r_{L1} + i_{{_{L2rms} }}^{2} *r_{L2}$$

Assuming the inductors have the same internal resistance rL1 = rL2 = rL and have the same rms value of the inductor currents iL1rms = iL2rms = iLrms. Then, the inductors losses can be determined as:

$$P_{{loss - total (Inductors)}} = 2 i_{{_{Lrms} }}^{2} r_{L}$$
(60)

Using (18), the rms value of the inductor current can be established, then the total power loss in the inductors can be expressed as;

$$P_{{loss - total (Inductors)}} = \frac{{2 G^{2} V_{o}^{2} }}{{R^{2} (3 - D)^{2} }}*r_{L}$$
(61)

Substituting from Eqs. (49), (55), (59), and (61) into the below equation, the total converter loss can be obtained.

$$\left. \begin{aligned} P_{loss - total} &= P_{{loss - total (Switches)}} + P_{{loss - total (Diodes)}} \hfill \\ &\quad + P_{{loss - total (Capacitors)}} + P_{{loss - total (Inductors)}} \hfill \end{aligned} \right\}$$
(62)

The expression for total losses is as follows:

$$\left. \begin{aligned} P_{loss - total} &= [a ( 4 \frac{{r_{SW} }}{R} + b \frac{{r_{D} }}{R}) + c \frac{{r_{C} }}{R} + d \frac{{r_{L} }}{R} \hfill \\ &\quad + e \frac{{V_{D} }}{{V_{o} }} + f((t_{rt} + t_{ft} ) f_{s} ) ] P_{o} \hfill \\ \end{aligned} \right\}$$
(63)

where

$$\left. \begin{gathered} a = \frac{{G^{2} }}{{D (3 - D)^{2} }}, b = (2 - D)(3 - D) \hfill \\ c = \frac{{2 G^{2} (1 - D)}}{{D (3 - D)^{2} }} + \frac{D}{(1 - D)}, d = \frac{{2 G^{2} }}{{(3 - D)^{2} }} \hfill \\ e = \frac{{(5 - 3D) G}}{(3 - D)}, f = \frac{(3 - 2D)}{{(3 - D) (1 - D)}} \hfill \\ \end{gathered} \right\}$$
(64)

Finally, the efficiency (ɳ) of the suggested topology can be determined as:

$$\eta = \frac{{P_{o} }}{{P_{o} + P_{loss - total} }}$$
(65)

where, Po is the output power. Substituting from (63) into (65), the proposed converter efficiency (ɳ) can be defined as:

$$\eta = \frac{1}{{1 + a \left( {4 \frac{{r_{SW} }}{R} + b \frac{{r_{D} }}{R}} \right) + c \frac{{r_{C} }}{R} + d \frac{{r_{L} }}{R} + e \frac{{V_{D} }}{{V_{o} }} + f (t_{rt} + t_{ft} ) f_{S} }}$$
(66)

Experimental results

To authorize the efficacy of the proposed DC-DC boost converter, a prototype has been built in the laboratory. The parameters of the suggested converter are given in Table 1. A photograph of the experimental setup system is shown in Fig. 8, and a schematic drawing for the test system is shown in Fig. 9. The results are captured using an oscilloscope during open-loop and closed-loop control.

Table 1 Parameters of the suggested DC–DC boost converter.
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Figure 8
figure 8

The experimental setup system.

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Figure 9
figure 9

The schematic drawing for the test system.

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Open loop results

Figures 10, 11, 12 and 13 show the experimental results when the suggested DC-DC boost topology operates at D = 0.4. Fig. 10a shows the gate-emitter switch voltage waveform with duty cycle 40%. Fig. 10b shows the input and output voltage waveforms of the proposed converter. It is observed that the output DC voltage at this duty cycle equal to about 107 V obtained from input voltage equal to 24 V, that represents 4.46 times of the input voltage. Also, the output voltage ripple is equal to 4 V that represents 3.7% from the output voltage.

Figure 10
figure 10

Experimental waveforms of (a) gate-emitter voltage, (b) input and output voltage, (c) input current, (d) capacitor C1 voltage, and (e) capacitor C2 voltage.

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Figure 11
figure 11

Experimental waveforms of (a) inductor L1 voltage and current, (b) inductor L2 voltage and current, and (c) SW voltage.

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Figure 12
figure 12

Experimental waveforms of (a) diode D1 voltage, (b) diode D2 voltage, (c) diode D3 voltage, and (d) diode Do voltage.

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Figure 13
figure 13

Voltage gain versus duty cycle: derived and experimentally.

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It can be noticed from Fig. 10c that the input current is continuous with average value equal to about 2.36 A. The voltages of the capacitors C1 and C2 are shown in Fig. 10d and e, respectively. The voltages across the capacitors C1 and C2 are equal with value 21 V across each capacitor, which validates Eq. (21). The experimental waveforms of voltages and currents for L1 and L2 are captured in Fig. 11a and b, respectively. It can be noticed that iL1 and iL2 are continuous signals. This ensures that the converter operates in CCM. The average current value passes through L1 or L2 is found to be 1 A that confirms Eq. (18). The voltage across L1 or L2 is almost equal to the input voltage (24 V) during the mode 1, and their values are—14 V during mode 2 that confirm the analysis. Figure 11c displays the voltage across the main switch (SW) with a value of 76 V.

The experimental waveforms of voltages across D1, D2, D3, and Do are shown in Fig. 12 with values of 36.1 V, 35.9 V, 36 V and 76 V, respectively. It can be seen that the voltage across the diodes D1, D2, and D3 is almost equal with a value equal to the half value of the voltage across the diode Do that confirms Eq. (20). Furthermore, Eq. (19) is validated from Figs. 11c and 12d. These figures show that the voltage through the switch equals to the diode Do voltage.

To present the voltage gain against the duty cycle, the waveforms of Fig. 13 are plotted for derived and experimental results. It can be observed that the experimental and the theoretical curves have a good convergence. However, the slight variations between the theoretical and experimental results are due to the influence of parasitic elements.

The converter efficiency against the output power at different values of the input voltage and at D = 0.4 is given in Fig. 14. The maximum measured efficiency at Vin = 24 V and D = 0.4 is 92.6% and increases to 93.7% if the input voltage increases to 48 V. Also, it can be seen that the efficiency is enhanced with raising the input voltage. Furthermore, the measured efficiency at Vin = 24 V and output power Po = 52 W is 91.2%. In this case, the total power losses equal 5 W that represents 9.6% from the output power. Also, Fig. 14 shows the theoretical efficiency curve at Vin = 24 V that calculated from Eq. (66). The great convergence between the theoretical and measured efficiency curves proves the validity of the analysis. Table 2 shows the measured efficiency of the suggested converter and other similar works at the same output power, Po = 52 W. It is clear from Table 2 that the suggested converter has the highest efficiency compared to the other related topologies.

Figure 14
figure 14

Converter efficiency versus output power at different values of the input voltage and D = 0.4.

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Table 2 Measured efficiency of the proposed circuit and other related topologies.
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Figure 15a illustrates the power losses division and the ratio of power losses for each component from the total power losses. The switch loss, the inductors losses, the capacitors losses, and the diodes losses represents 4%, 19%, 29%, and 48% of the total power losses, respectively. Figure 15b illustrates the efficiency pie chart at this experimental case. Hence, the converter efficiency can be enhanced by choosing low voltage/current rating of its components and the production of final converter fabrication.

Figure 15
figure 15

(a) Power loss distribution, and (b) the efficiency pie chart at a duty cycle of 40%, Vin = 24 V and Po= 52 W for converter components.

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Closed loop results

The experimental prototype is also examined during a closed loop control. A schematic diagram of the circuit that is utilized to control the output voltage of the proposed converter is shown in Fig. 16. A PI controller is applied to regulate the output voltage. The parameters of the PI controller are KP = 100 and KI = 200.

Figure 16
figure 16

A schematic diagram of closed loop control circuit.

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Figure 17 shows the output voltage response with changing the reference voltage (Vref) at input dc voltage equal to 24 V and a full load value. A step change in the reference voltage from 125 to 105 V (decrease) and from 105 to 125 V again (increase). It is noted that the output voltage tracks the reference voltage smoothly. Figure 18 shows the output voltage response with changing the input voltage at Vref = 140 V. A step change (decrease/increase/decrease) in the input voltage from 30 to 24 V is applied. This step change represents 25% change of the input voltage. It is observed that the output voltage maintains its value under reference voltage change. Figure 19 shows the output voltage response with changing the load resistance value at Vref = 115 V. A step change (increase/decrease) in the load resistance value from about 30% of the full load to full load value is applied. The output voltage remains constant under load changes. This proves the effectiveness of the closed loop control of the proposed converter.

Figure 17
figure 17

Output voltage with changing the reference voltage (Vref) at Vin = 24 V.

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Figure 18
figure 18

Output voltage response with changing the input voltage (Vin) at Vref = 140 V.

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Figure 19
figure 19

Output voltage response with changing the load value at Vref = 115 V.

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Discussion

In this part, a comparison between the two-cell proposed converter and other recent boost topologies is presented. Table 3 shows the comparison results according to the number of components, ideal voltage gain, and maximum voltage stresses through the main switch, output diode, and the output capacitors. The waveforms, which summarize the comparison, are plotted as shown in Figs. 20, 21 and 22.

Table 3 Comparison between the proposed converter and recent converter topologies.
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Figure 20
figure 20

Voltage gain versus duty cycle.

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Figure 21
figure 21

Normalized switch voltage stress with voltage gain variation.

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Figure 22
figure 22

Normalized output diode voltage stress with voltage gain variation.

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Figure 20 illustrates the variation of voltage gain when the duty cycle is varied, the proposed converter has the highest voltage gain for D ≤ 0.5. For D > 0.5, the converter in29 has the highest voltage gain value. However, the proposed topology has a total number of components of 10 components, but the converter in29 has 16 components which increases the cost and complexity of the system and decreases the efficiency. Also, the proposed converter has higher voltage gain for duty cycle varies from 0.5 to 0.67 than converters in31,32,33, and the conventional one. The normalized maximum switch voltage stress for each converter is recorded in Table 3 and shown in Fig. 21. Converter in31 has the highest normalized switch voltage stress, while converter in29 has the lowest normalized voltage stress, and approximately constant for all voltage gain values. The introduced converter has modest normalized voltage stress across the main switch. The normalized maximum output diode voltage stress for each converter is documented in Table 3 and shown in Fig. 22. The suggested converter has the lower normalized output diode voltage stress except the converter in32 that has the lowest value. However, the converter in32 has total number of components of 14 components which greater than the proposed converter that decreases the efficiency and increases the cost and the volume of the converter. From this comparative analysis, it is proved that the suggested converter has significant features in comparison to the modern topologies.

Conclusion

A new design of compact circuit that converts a low-level dc voltage to a high-level dc voltage has been proposed in this paper. It has a single switch and fewer passive components compared with recent boost converters. The new converter gets a high voltage gain at modest duty cycle, low switching losses, good efficiency, and it can be extended to get higher voltage gains by increasing the cascading additional cells. The suggested converter has been examined during open and closed loop process, and ensures a good control performance under reference voltage, input voltage, and load changes. Experimental results under different operating situations prove the usefulness of the new converter. In addition, the comparison between the new two-cell boost converter and other recent topologies has been presented. The proposed converter has the greatest voltage gain for duty cycle values D ≤ 0.5 with a total number of 10 components, which decreases the cost and complexity of the converter and increases the efficiency.