Introduction

Compared to their inorganic counterparts, one-dimensional (1D) organic nanostructures offer several unique advantages, such as inherent compatibility with plastic substrates, amenability to roll-to-roll large area producing, flexibility and low-temperature processing requirements1,2,3. Also, the single-crystal 1D organic nanostructures offer the possibility to construct organic electronic devices with unprecedented performance2. It is known that the existence of large amount of defects and grain boundaries in the amorphous or poly-crystalline organic films is the important reason for the inferior performance of conventional organic devices4. However, till now most organic single-crystal devices are fabricated on rigid, flat and smooth substrates such as SiO2/Si and glass and the choice of substrates is generally limited by the processing temperature, compatibility with chemicals and handling requirements etc5,6,7. Fabrication of organic electronic devices on non-conventional substrates, such as paper, poly(dimethylsiloxane) (PDMS), tapes, non-planar or arbitrary substrates will enable the utilization of many desired properties of the substrates, including flexibility, transparency, biocompatibility and low cost and thus bring about a lots of new applications in flexible organic circuits8,9, paper electronics10, solar cells11, conformal sensors12 and biointegrated electronics13.

Unfortunately, traditional microelectronic processing techniques, including photolithography, metallization and lift-off, are still not applicable for the organic single-crystal devices, although these techniques have been demonstrated to be highly successful for the construction of large-scale integrated electronic devices based on inorganic semiconductors. This is because (i) organic materials are largely incompatible with photolithography process. The inferior chemical/physical stability of organic materials makes them hard to stand the photolithography and plasma involved electrode deposition processes14, (ii) many flexible/transparent substrates suffer from problems like shrinkage or degradation due to their incompatibility with the harsh solvents usually used in the photolithography and lift-off processes and (iii) these techniques are normally restricted to the flat substrates and not applicable to the non-conventional substrates, such as the substrates with curved surfaces15.

To overcome the difficulty in photolithography, various methods including shadow mask9,10, inkjet print16 and in-situ/post-growth integration techniques17,18,19, have been developed to fabricate the organic nanostructure based devices. However, the inherent disadvantages of shadow mask and inkjet print methods, such as the poor precision for mask alignment/ink positioning and the limitation in minimum feature size, impede their applications in integrated organic devices. The existing in-situ integration methods usually involve the direct growth of organic nanostructures on pre-fabricated electrode circuits13, but the solution based or high temperature initiating growth process will inevitably cause the damage to the device substrates. In the post-growth integration method, the as-prepared organic NWs are dispersed on the pre-fabricated electrode circuits, while the bottom-contact device configuration usually offers poor device performance. Recently, various transfer-printing methods have been developed to achieve the transfer of inorganic nanowires (NWs)-based devices onto diverse substrates20,21,22,23. However, these methods are not applicable to the organic nanostructures because photolithography on the NWs is required in these processes. Also, due to the use of strong acid (for etching the sacrificial layer like SiO2 etc.)23, these methods show limited applications on the transfer of device with more sophisticated structures, such as Schottky diodes and field-effect transistors (FETs).

Herein, we report an alternative and yet simple, versatile and high-yield two-step transfer printing (TTP) method that enables fabrication of organic devices onto diverse conventional or non-conventional substrates that are not easily accessible before. The transfer yield for the microelectrode arrays is very high and the devices eventually formed can function properly with excellent reproducibility. Various organic electronic devices, including resistors, Schottky diodes and FETs were demonstrated by using the TTP method. Notably, these devices exhibited performance comparable to the device counterparts fabricated by conventional methods, demonstrating the high reliability, robustness and efficiency of the TTP method. It is expected that the TTP method will have important applications in future flexible organic electronics.

Results and discussion

The TTP method basically includes two different transfer printing processes: organic NWs are first transfer-printed from the growth substrate to the desired receiver substrate as highly aligned arrays by contact-printing (CP) method and then electrodes are transfer-printed onto the resulting receiver substrate by etching-assisted transfer printing (ETP) method. We note that CP method is a flexible and convenient way of transferring NWs to nonadhesive or adhesive target substrates with controllable density (Figure S1 in Supporting Information)24,25. Figure 1(a) illustrates the ETP process for organic NW based device fabrication, which includes two different approaches. At the beginning of both approaches, a thin copper (Cu) layer (300 nm) was deposited on Si substrate via electron-beam evaporation and served as sacrificial layer in subsequent transfer processes. The electrode arrays were then fabricated on the sacrificial layer through routine photolithography and lift-off processes (Figure 1(a), (I)). In first approach, a layer of poly(methylmethacrylate) (PMMA) (solids content 6%, molecular weight 495 kDa) was spin-coated on the electrode arrays and hardened at 120°C for 120 s on the hotplate, functioning as a temporary holder (Figure 1(a), (II)). Next, the whole structure was soaked in saturated ammonium persulfate ((NH4)2S2O8) solution at room temperature for 1–3 hours to etch away the sacrificial Cu layer. After that, the PMMA/electrodes film was released and floated freely on the surface of the solution (Figure 1(a), (III)). Photographs in Figure 1b–1d clearly show the ETP process for PMMA/electrodes film releasing from the Cu/Si substrate. The PMMA/electrodes film was then transferred to a deionized (DI) water bath to remove remaining etchant. The target substrate with CP transferred NW arrays was put underneath the floating PMMA-supported electrodes and then lifted up (Figure 1(a), (IV) and (V)). Finally, the PMMA film was dissolved quickly with acetone for ~5 s, leaving behind the top-contacted NW devices on the target substrate (Figure 1(a), (VI)). Also, the PMMA film can be selectively removed at the electrode pad positions to avoid the possible damage of organic solvent to the organic NWs (Figure 1(a), (VII)). In second approach, flexible adhesive tape was used as the receive substrate. After the transfer of organic NWs with CP method, the adhesive tape, along with NWs on it, was pressed against the electrodes patterned Cu/Si substrate (Figure 1(a), (VIII)), then followed by etching away the sacrificial Cu layer to separate the NW devices onto the tape from the donor Si substrate, as shown in Figure 1(a), (IX).

Figure 1
figure 1

(a) Schematic illustration of the TTP method for organic NW based device fabrication. (b), (c) and (d) show the corresponding photographs for the ETP process.

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Figure 2(a)–2(f) show the photographs of the microelectrode arrays fabricated by the ETP method on diverse substrates. Notably, this method shows little limitation on the types of target substrates; microelectrode arrays for different kinds of devices, including resistors, diodes and transistors, could be readily fabricated and transferred onto diverse substrates, such as conventional substrates of SiO2 (300 nm)/Si, glass and non-conventional substrates of paper, PDMS, thermal release tape (TRT) and Kapton tape. It is noteworthy that a high yield of near 100% for the microelectrode arrays can be achieved, as shown in Figure 2(g)–2(i), revealing the high reliability of the proposed ETP method. Local defects and damages are occasionally observed in the ETP fabricated electrode array (Figure 2(f), marked with a red circle), but they normally come from the complicated photolithography, metallization and lift-off processes for microelectrode fabrication, while have no relation with the subsequent ETP process. It is believed that these defects can be effectively excluded as long as the electrodes fabrication and ETP transfer are well implemented. The ETP process seemingly shares partial common technological features with the previously reported graphene transfer method26, in which graphene film is released and transferred from the growth substrate of Cu foil, however microelectrode transfer or even the whole device transfer by using this method has never been exploited thus far. In a previous work which is most similar to us process, Au electrodes were pre-patterned on SiO2/Si substrate then released by etching the SiO2 sacrificial layer in a HF solution23. However, the use of HF etchant seriously limits the types of metallic electrodes or device structures that can be accessible. Therefore, our work represents an important progress for extending the transfer printing method towards future advanced device applications.

Figure 2
figure 2

Photographs of the transferred microelectrode arrays on various substrates via EPT method, including conventional substrates such as (a) SiO2/Si, (b) glass and non-conventional substrates such as (c) paper, (d) PDMS, (e) thermally release tape, (f) Kapton tape. (g), (h) and (i) show the representative SEM images of the transferred microelectrode arrays, including resistors, diodes and top-gate FETs, on diverse substrates.

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Evidently, the present TTP method offers several important advantages compared to the previous methods9,10,16. First, organic NW devices can be constructed on almost any conventional and non-conventional substrates, since the TTP process involves no harsh fabrication process, thermal stress and vacuum condition. The high transfer yield also guarantees its application in future integrated devices. Second, the TTP method exhibits extremely high flexibility; most of the common electrodes such as Au, Ag, Ti and Al etc. can be transferred because (NH4)2S2O8 doesn't react with them and therefore almost all types of organic devices, such as resistors, diodes and transistors, can be constructed. Third, the TTP method can bridge up the gap between traditional photolithography techniques and organic devices. It surpasses conventional shadow mask or inkjet print methods. It is expected that new organic single-crystal devices with more sophisticated structures as well as higher integration level can be realized by using the TTP method. For instance, top-gate FETs, which are not accessible before for organic single-crystal devices, could be readily fabricated through the TTP method (discussed below). Forth, the use of flexible and rollable substrates in the TTP method, such as adhesive tapes, allows the device fabrication implementing in a cost- and time-effective manner, e.g., roll-to-roll (R2R) method can be utilized, thus facilitating the large-scale applications of the organic nanodevices.

By using the TTP method, various devices were successfully constructed from the copper phthalocyanine (CuPc) NWs and their device characteristics were further assessed. Figure 3(a) and 3(b) depict the representative current versus voltage (I-V) curves of the resistors and Schottky diodes fabricated on SiO2/Si, glass, PDMS and TRT substrates, respectively, in dark at room temperature. Significantly, it is noted that the devices fabricated by TTP method can function properly on various substrates; I-V curves of the resistors exhibit good linearity, while pronounced rectifying behaviors are observed for the Schottky diodes. To avoid any performance fluctuation caused by the variation of NW number in device channels, the CP process for NW transferring in first step was carefully carried out to ensure nearly the same NW densities on various substrates. In particular, for the adhesive substrates like PDMS and tapes, the NWs were first transferred to a rigid substrate of SiO2/Si or glass and then the transfer was accomplished by adhering the NW arrays to the adhesive substrates. In this work, the NW densities are controlled to be ~6/100 μm on the receiver substrates. To evaluate the impact of substrate types on device performances, 50 resistor devices on each substrates were measured and the statistical distributions of the dark conductance (G = I/V) are depicted in Figure S2. Notably, similar results are obtained on various substrates; the mean conductance is 0.44, 0.46, 0.42, 0.48 pS on SiO2/Si, glass, PDMS and TRT substrates, respectively, indicating the high reproducibility and reliability of the TTP approach. By taking into account the mean diameter of the NWs of ~550 nm and the device channel length of 10 μm, the conductivities of the CuPc NWs could be estimated to be 0.2 μScm−1 in dark. Moreover, investigations on the Schottky diodes on various substrates also disclose an excellent reproducibility; the mean rectification ratios are deduced to be 39.5, 40.8, 41.2 and 40.2 on SiO2/Si, glass, PDMS and TRT substrates, respectively, at a voltage range of ±5 V. Since the Schottky diodes based on organic nanostructures are rarely reported, we can't compare the diode performance with previous results directly. However, in comparison with the conventional organic film based Schottky diodes, which typically have a low rectification ratio less than 1027,28, our devices exhibit a large superiority due to the single-crystalline nature of the organic NWs as well as the unique approach for device construction. It is noted that, in above measurements, the residual PMMA on the electrode arrays were fully removed by quickly soaking the devices in acetone for 5 s to facilitate the electrical measurements. However, this may bring the concern that the organic NWs will be damaged during the solvent treatment. To address this issue, an especially designed electrode pads with much longer electrical connections were adopted, as shown in Figure S3(a) and 3(b). PMMA on the electrode pads could be selectively dissolved so as to facilitate the direct comparison of the electrical characteristics of the device before and after removing PMMA (Figure S3(c)). Notably, from Figure S3(d), no visible degradation of device performance is observed, indicating that the CuPc NWs are insensitive to acetone. Certainly, this electrode design can be extended to other organic NWs which are not so stable in organic solvent.

Figure 3
figure 3

Representative I-V curves of CuPc NWs based resistors (a) and Schottky diodes (b) on SiO2/Si, glass, PDMS and TRT substrates, respectively. (c) The transfer characteristics of CuPc NW based top-gate FETs measured at VDS = −10 V on PDMS. (d) Output characteristics of the top-gate FET. VG varied from −15 to +10 V in a step of +5 V. (e) Optical microscope images of the CuPc NW based devices, including resistor, Schottky diode and top-gate FET, fabricated on SiO2/Si, tape and PDMS, respectively.

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Besides the resistors and diodes, devices with much more sophisticated structure, i.e., top-gate FETs were also fabricated on various substrates, as shown in Figure 3(c) and 3(d) and Figure S4. The top-gate FET consists of a CuPc NWs channel, Au source and drain electrodes, a Si3N4 (150 nm) dielectric layer and an Au top gate. From the electrical output characteristics, i.e., source-drain current (IDS) versus source-drain voltage (VDS) at varied gate voltage (VG) of a typical device on PDMS (Figure 3(d)), it is noted that the device conductance increases monotonously with the decrease of VG, which is the typical feature of a p-channel metal-oxide-semiconductor FET (MOSFET). This result is consistent with the p-type characteristic of the CuPc NWs. Further analysis on the electrical transfer characteristics of the device, in Figure 3(c), discloses a hole mobility (μ) of 0.04 cm2V−1s−1 according to the equation μ = gmL/WC0VDS29, where gm = 5.1 nS at VDS = −10 V represents the transconductance of the FET and is deduced from the slope of the IDS-VG curve in the linear part according to the relationship of gm = dIDS/dVG, W/L = 3.3 : 10 is the width-to-length ratio of the NWs channel, C0 is the capacitance per unit area and is given by C0 = εε0/h, where ε is the dielectric constant of Si3N4 (7.5), ε0 is vacuum permittivity and h (150 nm) is the thickness of the Si3N4 gate dielectric layer. The current on/off ratio of the device can be deduced to be ~105. Interestingly, the device can operate at a relatively small gate voltage range of ±15 V due to the unique top-gate structure. To gain statistical significance, more than 90 devices on PDMS substrate were measured and over 80% of the devices exhibited a mobility above 0.01 cm2V−1s−1. Meanwhile, the mobilities of the devices fabricated on SiO2/Si and glass were also measured and estimated to be 0.01–0.05 cm2V−1s−1 (Figure S4). Although the mobilities of our devices are still lower than the best results obtained for single CuPc NW or nanoribbon (NR) based FETs (0.1–0.4 cm2V−1s−1)30,31, the values are comparable to the previous reports on CuPc NW or nanotube (NT) based FETs (0.0057–0.064 cm2V−1s−1)32 and film based FETs (0.0067 cm2V−1s−1)33. Moreover, the large current on/off ratio and the low operating voltage presented in this work manifest a high performance of the top-gate CuPc NW FETs. We believe that the device performance can be substantially improved by further optimizing the device structure, reducing the contact resistance, purifying the source material and so on. Close inspection on the optical microscope images of the devices in Figure 3(e) verifies that the TTP process does not produce any visible damage to the CuPc NWs as well as the electrodes; the devices, even the top-gate FET with multi-layer structure, are as perfect as that on the original Cu/Si substrate. On the other hand, after carefully examining the electrical characteristics of the TTP fabricated devices, we found that ~30% devices show non-ideal device performance, such as non-linear I-V curves (for resistors) and hysteresis (for Schottky diodes and top-gate FETs), indicating that the contact problem somewhat exists in the TTP fabricated devices. However, it is believed that device reproducibility could be significantly improved in the next step work by means of post-annealing and so on. The above results unambiguously demonstrate the great potential of TTP approach for producing high-performance and highly integrated organic NW devices on diverse substrates.

Organic NW based FETs are essential components for future organic electronics. While great progress has been made in the development of organic NW FETs34,35, almost all the devices are constructed with a bottom-gate configuration. It has been well confirmed that, in inorganic FETs, top-gated devices with high-dielectric-constant (high-k) dielectrics can significantly reduce the required switching/operation voltage and allow the fabrication of independently addressable device arrays and functional circuits and therefore are of significant interests36,37. However, due to the inadequate microelectronic techniques, top-gate organic nanostructure based FETs are rarely reported yet. Also, few methods can fabricate organic top-gate FETs on arbitrary conventional or non-conventional substrates at a wafer scale with high yield. Therefore, it appears that the TTP method can overcome the limitations of the existing microelectronic techniques and offers the possibility to construct high-performance top-gate FETs based on the organic NWs. In order to directly compare the performance of the bottom-gate FETs with the top-gate FETs, CuPc NWs were first transferred to a conventional SiO2 (300 nm)/p+-Si substrate, constituting the bottom-gate NW FETs. Afterward, the top-gate NW FETs were realized by transferring the electrodes onto the top of NWs via ETP method (Figure 4(a)). With this well-designed device architecture, the bottom-gate and top-gate NW FETs can be studied simultaneously, avoiding the fluctuation of NW properties. Inset in Figure 4(a) shows a typical SEM image of the top-gate CuPc NW FET fabricated on the SiO2/p+-Si substrate with two NWs in the conduction channel. Interestingly, it is found that the gate dielectric and gate electrode can wrap on the CuPc NWs, forming a near surrounding top-gate FET structure. As we will discuss later, this device structure will be very beneficial to the device performance improvement. Figure 4(b) depicts the representative transfer characteristics (IDS-VG) of the top-gate and bottom-gate NW FET. Notably, the top-gate FET exhibits much enhanced performance compared to the bottom-gate FET, with the current reaching two orders of magnitude higher than that in bottom-gate FET at the same conditions. In addition, for the top-gated NW FET, the gm at VDS = −10 V is about 1.2 nS, corresponding to a hole mobility of μ = 0.01 cm2V−1S−1, which is nearly 34 times larger than that of the bottom-gated FET (gm = 0.07 nS, μ = 0.0003 cm2V−1S−1). The remarkably superior device performance of the top-gate NW FETs could be attributed to their distinct structures. The high-k Si3N4 dielectric as well as the unique surrounding gate structure, make for a large gate capacitance and thus a higher gate modulation capability for the top-gate FETs.

Figure 4
figure 4

(a) Schematic illustration of the top-gate and back-gate NW FETs on a same chip. In top-gate FET, Au electrode and high-k Si3N4 layer serve as the top gate and gate dielectric, respectively. In bottom-gate FET, the degenerately doped p+-Si substrate and the SiO2 layer serve as the bottom gate and gate dielectric, respectively. Inset shows the top-view SEM image of a top-gate NW FET fabricated on SiO2/Si substrate. (b) IDS-VG curve of the top-gate NW FET at VDS = −10 V, along with the IDS-VG curve of bottom-gate NW FET measured at the same conditions for comparison.

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The proposed TTP method exhibits extremely high flexibility and is able to fabricate organic NW devices on a large variety of substrates, even on curved or other non-planar surfaces, as demonstrated in Figure 5. The microelectrode arrays can be successfully transferred to various non-planar substrates, including gloved finger tips, cylindrical and spherical PDMS and leaf. From Figure 5(a)–5(d), it is clear that the metal electrodes are smoothly following the deformation of the curved surfaces. It is noteworthy that these types of device configurations are extremely difficult to be achieved using established electronic technologies, owing to the intrinsically planar nature of the patterning, deposition, etching, materials growth methods that exist for fabricating such systems15.

Figure 5
figure 5

Photographs of the transferred microelectrode arrays on curved substrates, such as (a) gloved finger tips, (b) hemispheroidal PDMS, (c) leaf and (d) cylindrical PDMS. (e) Photograph and representative I-V curve of the CuPc NW resistor devices fabricated on cylindrical PDMS substrate. Inset shows the enlarged optical image of the device on curved PDMS. (f) Optical image of the organic NW resistors on the cylindrical PDMS substrate.

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The high flexibility of organic NWs also makes it suitable to be used in the flexible electronics. Figure 5(e) shows the photograph of the CuPc NW devices fabricated on the cylindrical PDMS substrate by TTP method. The corresponding optical microscope images (Figure 5(f) and inset in Figure 5(e)) reveal that the NWs can bridge between the two Au electrodes, similar to that on the flat PDMS substrate. Electrical measurements on the devices demonstrate the good ohmic contacts of Au electrodes with the NWs on the cylindrical PDMS (Figure 5(e)) and the conduction current is close to that obtained on the flat PDMS. From the above results, it is believed that the TTP method provides an effective route for integrating well-developed planar device technologies onto the surfaces of complex curvilinear objects, suitable for diverse applications that cannot be achieved by conventional means.

To further exploit the great potential of the TTP method for future low-cost and flexible device applications, a glossy brochure paper was adopted as the device substrate and CuPc NW photodetectors were constructed on it. The as-synthesized CuPc NWs were first transferred onto the glossy brochure paper and then the microelectrode arrays consisting of Au-Au (50 nm) electrode pairs were transferred on the top of the NWs via ETP method, forming the top-contacted resistor devices, as shown in Figure 6(a). Upon bending, as shown in Figure 6(b), the dark current of the device changes little (Figure 6(c)), indicating that the device is robustness against the tensile stress. The device exhibits pronounced photoresponse when it is illuminated with on-off modulated white light (intensity ~0.5 mWcm−2), as shown in Figure 6(d). The impact of bending curvature on the device performance is investigated; the device Ilight/Idark ratio decreases mildly from 14 at curvature = 0 cm−1 to 3.3 at curvature = 0.8 cm−1, while the response speed shows little dependence on the bending curvature and is less than 1s within the measurement range.

Figure 6
figure 6

(a) Optical microscope image of devices fabricated on the glossy brochure paper via TTP method. (b) Photographs of the device with different bending curvature. The corresponding dark I-V curves are shown in (c). Curve I, II, III and IV correspond to the bending curvatures of 0, 0.3, 0.4 and 0.8 cm−1, respectively. (d) Photoresponse of the bended device under on-off modulated white light illumination (0.5 mWcm−2). The voltage bias was fixed at +10 V.

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Conclusion

In summary, we developed a novel two-step transfer printing method to achieve the fabrication of a host of organic NW based devices, such as resistors, diodes and top-gate FETs, onto diverse conventional or non-conventional substrates. The TTP method combines two different transfer-printing processes: the organic NWs transfer via CP method and the electrodes transfer via ETP method. The ETP method has the advantages of simplicity, low cost and nearly 100% transfer yield regardless of monolayer and multilayer electrodes and can transfer most of the common metallic electrodes. The devices fabricated by TTP method exhibited closed and even superior performance as compared to the devices fabricated via conventional methods. The TTP method can extend photolithography process to organic electronics and thus surpass the conventional inkjet printing and shadow mask methods in terms of high integration level and low cost. On the other hand, the TTP method will endow the organic single-crystal devices with desirable properties, such as flexibility, stretchability, transparency and biocompatibility through the use of non-conventional substrates and thereby impact a range of applications, such as biosensing, flexible displays, robotics and energy conversion systems. Given the versatility and reproducibility of the TTP method, we believe that it will open up unique opportunities for integrations of organic devices onto various substrates or the surfaces of complex curvilinear objects and is suitable for diverse applications that cannot be achieved by conventional means.

Methods

Growth of CuPc NW arrays and transfer of NWs onto various substrates

Synthesis of the CuPc NW arrays were conducted in a horizontal quartz tube furnace via physical vapor deposition (PVD). Briefly, a predetermined amount of CuPc powder (J&K, >90%) as the source material was placed at the center of the furnace, while the Si substrate with 6 nm Au on was placed at downstream direction with distance of ~8 cm from the source. The reaction chamber was flushed and filled with 60 sccm Ar carrier gas after it was evacuated to a base pressure of 2 Pa. The pressure in the tube was adjusted to 220 Pa before heating. The temperature of the source material and absorbent were maintained at 415°C during the experiment, while the substrate temperature was ~180°C. After a growth duration of 2 h, large-area aligned CuPc NW array was obtained on the Si substrate (Figure S1). The CuPc NWs were then transferred to the device substrate by the CP method, which involves directional sliding of the CuPc NWs growth substrate against the device substrate, resulting in the well-aligned NWs on the device substrate (Figure S1).

Device construction

The microelectrode arrays were fabricated on the Cu (300 nm)/Si substrate via standard photolithography, metallization and lift-off processes. Cu served as the sacrificial layer in the ETP process. Photolithography was performed in Karl Suss (MJB4) mask aligner with positive photoresist (AR-P 5350). The metallic electrodes were deposited by E-beam evaporation (Kurt J Lesker Company, PVD 75). To fabricate the resistors, symmetric electrode pairs of Au-Au (50 nm) were used, while asymmetric electrode pairs of Au-Ti (50 nm) was adopted for the Schottky diodes. To construct the top-gate FETs, Au (50 nm) source and drain electrodes with channel width of 200 µm and channel length of 10 µm were first defined by photolithography on the Cu layer and then high-k Si3N4 (150 nm) gate dielectric was deposited by magnetron sputtering (Kurt J Lesker Company, PVD 75) on the source/drain electrodes, followed by the deposition of Au (50 nm) gate electrode on the dielectric layer.

All the electrical measurements were conducted using a semiconductor characterization system (Keithley 4200-SCS) on a probe station (M150, Cascade) in a clean and shielded box at room temperature. To determine the photoconductive characteristics of the CuPc NWs on the paper, the white light from the optical microscope on the probe station was used as the light source (~0.5 mWcm−2).