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Ferroelectric gating of two-dimensional semiconductors for the integration of steep-slope logic and neuromorphic devices

Nature Electronics volume 6, pages 658–668 (2023)Cite this article

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Abstract

The co-integration of logic switches and neuromorphic functions could be used to create new computing architectures with low power consumption and novel functionalities. Two-dimensional (2D) semiconductors and ferroelectric materials could be potentially used to make such devices, but integrating them on the same platform is challenging. Here we show that the 2D semiconductor tungsten diselenide and 2D/2D heterostructures of tungsten diselenide/tin diselenide can be integrated with doped high-k ferroelectric (silicon-doped hafnium oxide) and high-k dielectric gate stacks. With this single platform, four types of logic switch—2D metal–oxide–semiconductor field-effect transistors (FETs), 2D/2D tunnel FETs, negative-capacitance 2D FETs and negative-capacitance 2D/2D tunnel FETs—can be created. The negative-capacitance tungsten diselenide/tin diselenide tunnel FET exhibits an average subthreshold swing of 55 mV dec–1 over four decades of current, and the negative-capacitance tungsten diselenide FET exhibits an average subthreshold swing of 50 mV dec–1 over three decades. The shared ferroelectric gate stacks on 2D devices can also be exploited to create co-integrated artificial synapses for neuromorphic computing.

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Fig. 1: A hybrid ferroelectric and 2D material technology platform.
Fig. 2: Fabrication.
Fig. 3: Room-temperature electrical characteristics of a representative WSe2/SnSe2 TFET and WSe2 FET fabricated on the same flake and platform.
Fig. 4: Electrical characteristics of the NC WSe2/SnSe2 TFET.
Fig. 5: Electrical characteristics of the NC WSe2 FET.
Fig. 6: Synaptic functionality characterization of the hybrid technology platform.

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Data availability

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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Acknowledgements

We acknowledge the ERC Advanced Grant Milli-Tech (grant no. 695459) and ERC-2016-ADG, Project ‘MEMS 4.0’, grant agreement no. 742685, for providing financial support for this research. We also thank A. Seabaugh and P. Paletti for sharing the data presented in Fig. 4h and Supplementary Fig. 14.

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Authors and Affiliations

  1. Nanoelectronic Devices Laboratory, Institute of Electrical and Microengineering, École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland

    Sadegh Kamaei, Ali Saeidi, Yingfen Wei, Carlotta Gastaldi & Adrian M. Ionescu

  2. Microsystems Laboratory, Institute of Electrical and Microengineering, École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland

    Xia Liu & Juergen Brugger

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Contributions

S.K. and A.M.I. conceived the main idea of this experimental study and designed and developed the process flow. S.K., X.L. and J.B. conceived the fabrication process. S.K. performed the electrical measurements and data analysis. C.G. performed the atomic force microscopy and piezoelectric force microscopy measurements. S.K., C.G. and A.S. carried out the MFM characterization and optimization. S.K. and Y.W. performed the pulsed measurements. S.K. and A.S. prepared the figures and schematics. S.K., A.S., J.B. and A.M.I. wrote the manuscript.

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Correspondence to Sadegh Kamaei.

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Nature Electronics thanks Zheng-Dong Luo, Shubhadeep Bhattacharjee and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Supplementary Notes 1–5, Figs. 1–24 and Tables 1 and 2.

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Kamaei, S., Liu, X., Saeidi, A. et al. Ferroelectric gating of two-dimensional semiconductors for the integration of steep-slope logic and neuromorphic devices. Nat Electron 6, 658–668 (2023). https://doi.org/10.1038/s41928-023-01018-7

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