Abstract
Logic-in-memory architectures could be used to develop efficient computing devices with low power consumption. However, the approach is limited by device performance issues, including reliability and versatility. Here we report a two-dimensional van der Waals heterostructure device that can function as both reconfigurable transistor and reconfigurable non-volatile memory, as well as provide reconfigurable logic-in-memory capabilities. The architecture of the device—termed a partial floating-gate field-effect transistor—offers both charge-trapping and field-regulating units. When operating as a transistor, the device can be switched between the p- and n-type mode, and exhibits a subthreshold swing of 64 mV dec–1 and on/off current ratio approaching 108. When operating as a memory, the device can be switched between the p- and n-type memory, and exhibits an erase/program ratio approaching 108. We use the devices to fabricate complementary metal–oxide–semiconductor circuits, and linear and nonlinear logic gates with in situ storage, as well as device-efficient half-adder circuits.
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Data availability
The data that support the findings of this study are available from the corresponding authors on reasonable request. Source data are provided with this paper.
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Acknowledgements
We are grateful to the National Natural Science Foundation of China (nos. 51902098 (D. Li), 52221001, U19A2090 and 62090035 (A.P.), 51972105 (X.Z.), U1930114 (H.D.) and 51991341 (Yuan Liu)) and the Key Program of Science and Technology Department of Hunan Province (nos. 2019XK2001 and 2020XK2001 (A.P.)), the Science and Technology Innovation Program of Hunan Province (nos. 2021RC3061 (D. Li), 2020RC2028 (B.Z.) and 2021RC2042 (H.L.)), the Natural Science Foundation of Hunan Province (nos. 2021JJ20016 (D. Li), 2021JJ30132 (X.Z.)) and the project funded by China Postdoctoral Science Foundation (nos. BX2021094 and 2020M680112 (B.Z.) and 2021M690953 (H.L.)), National Key R&D Program of China (No. 2021YFA1200503 (Yuan Liu)).
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D. Li and A.P. conceived and supervised the experiment. D. Li, X.S., C.Z. and J.Y. designed the devices and circuits. X.S., C.Z., H.L., B.Z. and L.X. performed the device fabrication and property characterization. Yong Liu captured the Raman spectra of the heterojunctions. W.Y. and D. Liang obtained the AFM images and height profiles of the devices. Q.S., W.Z. and C.M. supported the cross-sectional information of the device. X.Z., H.D., L.L., Yuan Liu and D. Li provided assistance with the mechanism analysis and discussion. X.S. and D. Li wrote the manuscript with help from all the authors.
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Nature Electronics thanks Dayane Reis, Tania Roy and Hyeon-Jin Shin for their contribution to the peer review of this work.
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Extended data
Extended Data Fig. 1 Transport properties of WSe2-based ambipolar FET and memory.
Transport properties of WSe2-based ambipolar FET and memory. Schematic structure of WSe2-based (a) ambipolar FET and (c) ambipolar memory. (b) The corresponding optical image. (d) Transfer curves of WSe2 FET, where graphene is used as the back gate and drain voltage is applied between electrodes E2 and E3. Typical ambipolar conduction behaviour is observed with the minimum current point locating at around 0 V, and the small voltage hysteresis demonstrates little interface charge states. (e) Double sweep transfer characteristic of WSe2-based memory by scanning control gate voltage between -8 and +8 V. (f) Retention performance of channel current after applying voltage pulse of +8 or -8 V on control gate, showing a small erase/program ratio less than 10.
Extended Data Fig. 2 Relationship between pulse width of CG and device performance.
Relationship between pulse width of CG and device performance. (a) Transfer curves of PFGFET in FET mode after different pulse width. (b) Relationship between the pulse width and ION/IOFF. Dynamic switching behaviour between p- and n-type with pulse width of (c) 90 μs and (d) 5 ms.
Extended Data Fig. 3 Switching and retention performance of PFGFET.
Switching and retention performance of PFGFET. (a) Switching and (b) retention performance of reconfigurable memory.
Extended Data Fig. 4 Transport properties of MoTe2-based device (PFGFET #6) with 16.2 nm hBN tunnelling layer.
Transport properties of MoTe2-based device (PFGFET #6) with 16.2 nm hBN tunnelling layer, indicating that ambipolar MoTe2 has similar behaviours with such device architecture. (a) Optical and AFM images of the device. Transfer curves of the PFGFET device acquired at (b) memory mode (VTG = ± 5 V) and (c) field effect transistor mode (VCG-pulse = ±15 V). (d) The reconfigurability of PFGFET at field effect transistor mode. The PFGFET is initially programmed at p-type state with VCG-pulse of -15 V. When an opposite VCG-pulse (+15 V) is introduced, this state will be erased, resulting in n-type state. (e) Switching and (f) retention performance of reconfigurable PFGFET #4. The results indicate that the ambipolar MoTe2 exhibits similar reconfigurable memory and FET capacity, that is, enables the coexistence of memory and logic function in a single unit.
Extended Data Fig. 5 Transport properties of MoS2-based PFGFET (PFGFET #2).
Transport properties of MoS2-based PFGFET (PFGFET #2). Schematic structure of MoS2-based (a) FET and (c) PFGFET. (b) The corresponding optical image of FET and PFGFET. (d) Transfer curve of MoS2 FET, where graphene is used as the back gate and drain voltage is applied between electrodes E1 and E2. Typical n-type depletion conduction behaviour is observed. (f) The n-type transport behaviour with optimized on/off transition is acquired at MoS2-based PFGFET (between E2 and E3 electrons). (e) Subthreshold swing acquired from transfer curves of FET and PFGFET. The SS of PFGFET is extracted to be 66 mV/dec. (g) Double sweep transfer characteristic of MoS2-based memory by scanning control gate voltage between -8 and +8 V. The erase/program ratio for VTG = -2 V and VTG = 2 V are about 1 and 108, indicating the n-type conduction behaviour of MoS2. (h) Switching and (i) retention performance of MoS2-based PFGFET.
Extended Data Fig. 6 Power consumption of the NOR logic gate.
Power consumption of the NOR logic gate. (a) Output waveforms (b) current and (c) power consumption of NOR logic gate with read voltage of 1 V. (d) Output waveforms (e) current and (f) power consumption with read voltage of 100 mV. (g) Output waveforms (h) current and (i) power consumption with read voltage of 10 mV.
Supplementary information
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Sun, X., Zhu, C., Yi, J. et al. Reconfigurable logic-in-memory architectures based on a two-dimensional van der Waals heterostructure device. Nat Electron 5, 752–760 (2022). https://doi.org/10.1038/s41928-022-00858-z
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DOI: https://doi.org/10.1038/s41928-022-00858-z
