Reconfigurable frequency multiplication with a ferroelectric transistor

Abstract

Frequency multiplication is essential in wireless communication systems, where stable high-frequency oscillations are required. However, multipliers typically employ power- and area-hungry filtering and amplification circuits. Here, we show that a single ferroelectric field-effect transistor, made from ferroelectric hafnium oxide, can be used as a full-wave rectifier and frequency doubler. This is achieved by using the parabolic shape of the transistor’s transfer characteristics, which can be tailored by accurately tuning the partial polarization switching and the band-to-band tunnelling drain current. Due to the reversible polarization switching, our approach is fully reconfigurable, allowing either multiplication or simple transmission of the input frequency to be activated within a single ferroelectric transistor. With our devices, we also implement two practical cases of the frequency modulation scheme without any additional filtering circuits.

Main

Frequency multiplication or harmonic generation is widely used in communication systems, where a nonlinear element generates an output signal whose frequency is a multiple (harmonic) of its input frequency1. Over the past 70 years, many different nonlinear devices have been employed in such applications, including Schottky diodes and field-effect transistors (FETs)1,2. However, besides the desired frequency, they typically generate a series of additional harmonics. This leads to low conversion efficiencies and the need for complicated filtering and amplification circuit designs, which are often power- and area-intensive. Thus, the development of more efficient frequency multiplication approaches is desirable.

One such approach is to exploit symmetries in the output characteristics of the device to selectively enhance the generation of either even or odd harmonics with symmetric or antisymmetric characteristics, respectively, as well as to confine most of the output power to a single, desired harmonic3. For example, the antisymmetric current–voltage (IV) curve in resonant tunnelling diodes results in efficient odd harmonics generation3. Similarly, frequency doubling has been theoretically predicted, and later experimentally demonstrated, by employing a three-terminal ballistic junction with symmetric parabolic characteristics4,5. Recently, multipliers based on graphene FETs6,7 and carbon nanotube (CNT) FETs8 have demonstrated promising capabilities. Due to their unique properties (such as ambipolar conduction, nearly symmetric current–voltage transfer characteristics and a broad operating frequency range), these carbon-material-based FETs have also been used to create other radiofrequency (RF) devices, including frequency mixers9 and tunable amplifiers and modulators10.

A ferroelectric FET (FeFET) resembles a conventional transistor, but has a ferroelectric layer in the gate stack11. Depending on the polarization direction (up or down) in the ferroelectric, the threshold voltage of the transistor can be high or low, respectively. For this reason, the traditional application of FeFETs is as non-volatile memory elements. FeFETs based on perovskite ferroelectrics have demonstrated excellent endurance and retention performance, as well as functionality in large memory arrays12. However, these materials have a series of integration and scaling issues, which could limit further development of the technology. The recent discovery of ferroelectricity in hafnium oxide (HfO2)13 has inspired renewed interest in FeFETs, and the material has the potential to overcome many of the limitations of perovskite FeFET technology. This is due, in particular, to its robust ferroelectricity even upon aggressive vertical14 and lateral scaling15, its wide spectrum of deposition techniques, as well as factors that stabilize the ferroelectric phase16. Furthermore, the material is fully compatible with the fabrication processes employed in the semiconductor industry. As a result, large HfO2-based FeFET memory arrays have already been demonstrated17,18. In addition, the peculiar switching patterns of the FeFETs also make them attractive for a range of other novel applications. For example, their accumulative switching19 is of interest in the development of capacitor-less integrate-and-fire neurons20, their partial polarization switching in artificial synapses21,22, and their abrupt stochastic switching in random number generators and stochastic computing23. FeFETs are also of potential use in logic computations24 and steep-slope devices25.

In this Article, we report a frequency multiplier based on a single FeFET. Our approach relies on the unique symmetric and rectifying properties of the transfer (IV) curve of the devices. We achieve this by electrically tuning both the partial polarization switching of the ferroelectric for the right IV branch and the band-to-band tunnelling currents at the gate–drain overlap for the left branch. Based on this, we experimentally demonstrate frequency doubling of the input signal applied at the gate. Moreover, we show that the multiplication mode can be selectively activated or suppressed depending on whether the polarization in the gate stack is up or down, respectively: that is, the multiplication concept is fully reconfigurable. The device demonstrates no degradation after more than 1010 doubling cycles, circumventing the endurance weakness of HfO2-based FeFETs. We also exploit the reconfigurability to implement two practical schemes of the binary frequency-shift keying (FSK), which is a particular case of the widely adopted frequency modulation technique in telecommunication systems.

Shaping of transfer characteristics

Figure 1a shows a schematic gate stack of devices employed in this work, which consisted of polysilicon/TiN (gate electrode), 8 nm HfO2 (ferroelectric layer), 0.8 nm SiON (interface layer) and p-doped silicon substrate. The ferroelectricity in HfO2 was stabilized by adding 4% Si doping (see Methods). The operation of a FeFET relies on the reversal of ferroelectric polarization in the gate stack. By applying a positive gate pulse (VP) at the gate, the polarization points down, which, through Coulomb coupling, attracts minority electrons to the substrate and induces a low threshold voltage (VT) of the transistor (high conductivity). A negative pulse (VN) instead induces polarization pointing upward, which repels the electrons and yields a higher VT value (low conductivity). The two operations are usually termed program (PRG) and erase (ERS), respectively, and the obtained two VT states can be used to store digital information (see Methods and Supplementary Fig. 1 for detailed write and read operations). Nevertheless, the transition from low VT to high VT (and vice versa) is a highly gradual process as VP (and VN) amplitude progressively increases, as shown by the family of drain current–gate voltage (IDVG) curves in Fig. 1b. This originates from the multidomain structure of the ferroelectric (Fig. 1a) and the consequent partial switching of the polarization when the VP and VN amplitudes are not large enough to switch all the present domains. Hence, a continuum of intermediate VT states between the nominal low and high VT values will exist, which can be accessed either by varying VP (Fig. 1c) or VN (Fig. 1d). The pulse duration (tP) was fixed to 1 μs for all pulses in Fig. 1. Note also that the partial polarization switching can be alternatively achieved by modulating tP or the number of pulses, instead of increasing their amplitudes (Supplementary Fig. 2). This phenomenon of intermediate VT states has been exploited to implement analogue weights in artificial synapses22. Figure 1c,d also shows that the PRG and ERS transitions start and terminate at different absolute voltage values. This is attributed to the asymmetric gate stack; that is, the ferroelectric layer in our FeFETs is confined between heterogeneous top and bottom materials, which have different work functions and internal voltage drops.

Fig. 1: Partial polarization switching in FeFETs.
figure1

a, Schematic of the FeFET structure and layer composition. G, S and D indicate gate, source and drain terminals, respectively. Arrows represent ferroelectric domains pointing up and down, randomly distributed in the ferroelectric layer. b, Transfer (IDVG) characteristics as a function of the PRG (VP) and ERS (VN) voltages, collected at drain voltage VD = 100 mV, with source and bulk grounded. c,d, Increasing VP amplitude shifts the curves to lower threshold voltage (VT) values (c), whereas increasing VN amplitude shifts to higher values (d). Reference pulses (Vref) in c and d had amplitudes of −4.5 V and 4.5 V, respectively. All pulses employed in the figure had tP = 1 μs.

Another interesting property of a transistor that will be exploited in this work is the band-to-band tunnelling current illustrated in Fig. 2a. Generally, with a sufficient potential difference between the gate and the drain terminals that induces a very strong band bending in Si, a band-to-band tunnelling process in the gate-to-drain overlap region takes place26,27. As a consequence, a current can be sensed at the drain, which originates from the tunnelling of valence-band electrons into the conduction band (Fig. 2a). This current is typically termed gate-induced drain leakage (GIDL), because it represents an undesired source of leakage in logic transistors. However, some memory concepts take advantage of IGIDL to carry out write operations28. IGIDL depends heavily on the electric field in the overlap region, which can be varied, for example, by changing the drain (VD) and/or the gate voltage (VG). In fact, Fig. 2b shows that IGIDL can be gradually tuned over orders of magnitude by increasing VD and/or decreasing VG. It is important to note that IGIDL sensed at the drain has the same sign as the transistor current in the subthreshold and inversion regime. Moreover, at sufficiently high VD, the transfer curves in Fig. 2b tend to have a ‘V’ or a parabolic shape, containing a point of minimum conduction. Such an IDVG plot therefore shows rectifying behaviour, in the sense that both negative and positive VG values will result in positive ID. To a certain extent, this resembles the IV curve of full-wave rectifiers and the ambipolar curve of graphene-based6,7 and nanowire-based FETs29,30.

Fig. 2: Arbitrary tuning of the shape and symmetry of the FeFET transfer characteristics.
figure2

a, Energy band diagram illustrating the band-to-band tunnelling in the gate–drain overlap region. Valence-band electrons tunnel into the conduction band and consequently generate holes. Electrons and holes are collected by the drain and substrate, respectively, giving rise to IGIDL. b, Transfer curves as a function of VD, which increases from 0.1 V to 3 V in steps of 0.1 V. c, VT versus VP plot from Fig. 1c, showing three VT states (A, B and C) into which the FeFET is programmed. df, Linear plots of IDVG curves as a function of VD (from 0.1 V to 2.5 V) for high-VT (d, state A), intermediate-VT (e, state B) and low-VT (f, state C) states. g, Symmetry and width tuning of the parabolic curve as a function of VP with fixed drain bias. Although only three curves (corresponding to cases A, B and C) are shown here, an arbitrary and continuous tuning can be obtained by adopting a proper VP.

This can be better appreciated in the linear IDVG plots in Fig. 2d–f. Three example cases are shown, corresponding to the FeFET being programmed into high-VT (A, Fig. 2d), intermediate-VT (B, Fig. 2e) and low-VT (C, Fig. 2f) states, achieved by applying VP pulses as indicated in Fig. 2c. For each case, the family of transfer curves is collected as VD is increased from 100 mV to 2.5 V. Figure 2d shows that the rectifying parabolic shape becomes more prominent as VD increases. However, the shape is asymmetric and the minimum conduction point is shifted to the right. Nevertheless, by decreasing VT under partial (B) or total polarization switching (C), almost symmetric IDVG curves can be achieved (Fig. 2e,f). Figure 2g illustrates this VT shift on increasing VP at a fixed VD, that is, with a fixed left parabolic branch. Note also that by shifting VT, not only the symmetry, but also the width of the parabolic curves can be varied. Overall, these experiments indicate that the shape and symmetry of the FeFET transfer curve can be monotonically and arbitrarily tuned by pure electrical excitations, which is an extremely appealing feature.

Frequency multiplication

We will now use a FeFET programmed and biased in a way to display the symmetric shape shown in Fig. 2f (case C, the uppermost curve, VD = 2.5 V, VP = 3.5 V). By superimposing a sinusoidal signal of frequency fin to the gate d.c. bias, for which the device is at the minimum conduction point, the drain current will display a signal whose fundamental frequency is double that at the input, as schematically depicted in Fig. 3a. In fact, thanks to the rectifying behaviour, both the positive and negative input semicycles will result in positive drain current semicycles, so that each semicycle swing of the input signal will correspond to a full-cycle swing of the output signal. To carry out this experiment, we used the set-up depicted in Fig. 3b and monitored the output voltage Vout at the oscilloscope. Indeed, Fig. 3c shows that, by applying an input with fin = 1 kHz (green curve), the resulting output is a sinusoidal signal with frequency fout = 2 kHz, thus clearly demonstrating the frequency doubling. The spectral analysis of the output signal, Vout (Supplementary Section 5), confirms that the predominant frequency is indeed 2 kHz, where more than 85% of the signal power is concentrated. Other spectral components (mainly 1 kHz and 3 kHz) are present as well; these originate from the incomplete harmonic rejection with the non-ideal parabolic shape of the IDVG curve. Nevertheless, they appear largely attenuated (Supplementary Fig. 5.1a), showing the benefits of the symmetric characteristics over the generally non-symmetric one in conventional frequency multipliers1,2. Frequency doubling is also possible for higher fin values, as demonstrated in Supplementary Fig. 6 for 10 kHz, 100 kHz and 1 MHz. This is summarized in Fig. 3d, where all experimental points lie on a line with a slope of 2, which equals the desired frequency multiplication factor.

Fig. 3: Frequency doubling with a FeFET.
figure3

a, Principle of the full-wave rectification of a sinusoidal input Vin applied at the FeFET gate. Each semicycle swing of the input signal will correspond to a full-cycle swing of the output signal, consequently doubling the fundamental frequency. b, The electrical set-up: Vin, consisting of a d.c. bias close to the minimum conduction point (VG = 0 V) and a sinusoidal signal of frequency fin, VDD = 3.5 V, a load resistor of R = 1 MΩ and a d.c. block capacitor. Vout is recorded at the oscilloscope. c, The experimentally obtained dominant frequency of Vout is effectively doubled compared to Vin. d, The dominant output frequency fout as a function of fin ranging from 1 kHz to 1 MHz. The points correspond to experimental values taken from c and Supplementary Section 6 and lie on the dashed line; this has a slope of 2, which equals the desired frequency multiplication factor.

Note also that, by using the FeFET set into the high-VT state (case A, the uppermost curve in Fig. 2d, VD = 2.5 V) and by applying to it the same d.c. and a.c. signals as for the previous case, no multiplication will take place. Instead, the input fundamental frequency will be transmitted to the output. In fact, the input sinusoid experiences only the left branch of the deformed parabola, so full-wave rectification is precluded. This indicates that the multiplication mode can be activated and suppressed simply by programming and erasing the device, respectively, which makes the concept electrically reconfigurable. This property is demonstrated and exploited in the next section (see Fig. 6) and further analysed in Supplementary Section 5.

One concern that might arise is the practical use of these devices over an extended number of frequency multiplication cycles. In fact, in contrast to perovskite-based FeFETs, which typically display excellent switching endurance (more than 1012 PRG/ERS cycles27), HfO2-based FeFETs suffer from a relatively low endurance. This usually ranges between 104 and 105 bipolar cycles, after which it is not possible to achieve the VT tuning shown in Fig. 1b. Nevertheless, the frequency multiplication shown here does not rely on the switching but on the symmetric shape of the IDVG curve. The FeFET thus has to be programmed only once into a desired VT, after which the state is maintained in a non-volatile manner31 and can be used indefinitely for multiplication. To verify the impact of the frequency doubling on device reliability, we performed the cycling experiment depicted in the upper panel of Fig. 4a. The FeFET was stressed by applying alternating gate pulses of +2 V and −2 V (1 μs), with simultaneously superimposed drain voltage pulses of 2.5 V (1 μs). These are the maximum values the device is exposed to during multiplication (Fig. 2d–f), but are insufficient to induce any ferroelectric switching, as is evident in Fig. 1c,d. As a result, the device does not degrade and it displays very stable VT levels over the investigated 1010 cycles. As a consequence, the multiplication property remains unchanged after this stress test, as shown in Fig. 4b (left). Moreover, the right part of Fig. 4b shows that frequency doubling is maintained, stable und unperturbed, even when continuously performed on the same device over another three days. Therefore, this application circumvents the switching endurance issue (one of the major weaknesses of HfO2-based FeFETs).

Fig. 4: Reliability of FeFET-based frequency multiplication.
figure4

a, The VT states (low-VT, high-VT and intermediate-VT) and therefore the FeFET programming capability remain unchanged under extensive stressing by the maximum voltage values (upper panel) used during multiplication. It should be noted that this experiment does not represent the switching endurance of the device, because the adopted VG values are insufficient for switching. b, Left: frequency doubling after the stress test in a is almost identical to the one in Fig. 3c. Right: frequency doubling, performed continuously over three consecutive days, induced no significant degradation.

Frequency modulation

Frequency modulation (FM) is a widely used transmission technique in telecommunications and signal processing, where the information is encoded as a variation of the frequency of a carrier wave. For example, digital data can be encoded through discrete frequency changes, with each frequency representing a digit. The simplest scheme is binary FSK, as illustrated in Fig. 5a, where one frequency corresponds to a binary 1 and a second represents a binary 0.

Fig. 5: Experimental implementation of binary FSK.
figure5

a, FSK principle. Binary data 1 and 0 modulate the frequency of a carrier sinusoidal signal between two discrete values. b, Schematics of the FSK implementation with a FeFET: binary data 1s and 0s shift the d.c. bias of the parabolic transfer curve between the minimum conduction point and the GIDL branch, respectively. Accordingly, the frequency at the output is doubled or unchanged, respectively. c, Experimental implementation. The input signal is given by Vin = Vdata + Vcarrier, which effectively produces a frequency-modulated output signal 1-0-1-0. The 0s and 1s at the input correspond to two discrete frequency values of 1 kHz and 2 kHz at the output, respectively.

Here, we experimentally implement two FSK schemes with a FeFET-based doubler. We again adopt the experimental set-up depicted in Fig. 3b. Figure 5b presents a schematic of the first FSK scheme, which adopts a FeFET prepared in a way to display a symmetric parabolic IDVG curve (case C, Fig. 2f), that is, by setting the device into the low-VT state with VP = 4.5 V and tP = 1 μs. The input signal applied at the gate (Vin) is given by the sum of the data waveform (containing binary 1s and 0s) and of the sinusoidal carrier, that is, Vin = Vdata + Vcarrier, both of which are supplied by the arbitrary waveform generator. The data bit stream is used to shift the bias point on the IDVG curve10. This is achieved by adopting a square pulse as the data waveform, with amplitude of 0.5 V and a voltage offset of −0.5 V. In this way, the logical 0 will correspond to a gate bias of VG = −1 V at the left (GIDL) branch of the IDVG curve, where no frequency multiplication occurs and the input frequency is transmitted to the output. The logical 1 instead corresponds to VG = 0 V at the minimum conduction point, thus inducing frequency doubling at the output. Figure 5c shows the experimental results. The upper panel displays the total input signal Vin, where the sinusoidal component has frequency 1 kHz and peak-to-peak amplitude 3 V. The lower panel clearly shows that a frequency-modulated signal Vout is produced at the output, where the 0s and 1s correspond to two discrete frequency values of 1 kHz and 2 kHz, respectively. Note, however, that the amplitude of the 1s is nearly half that of the 0s due to the inherent process of the frequency doubling presented here (Fig. 3a). Although this is typically not the case for classical FM, the latter is also well-known to be largely robust to amplitude variations of the signal.

Figure 6 shows the principle and experimental implementation of a second FSK scheme, which is based on the reconfigurability of the transfer curve between the low-VT and high-VT states. Here, the stream of 0s and 1s is encoded by erasing and programming the FeFET, respectively, instead of changing the d.c. biasing point. According to Fig. 2g and the schematic in Fig. 6a, the ERS operation will result in a shift of the right branch of the IDVG curve, distorting its symmetry (Fig. 2g) and consequently shifting the minimum conduction point to the right. Thus, by biasing the FeFET at VG = 0 V, which corresponds to the minimum conduction point of the PRG curve only, the superimposed carrier signal at the input will be doubled at the output only if the FeFET was set into the PRG (low-VT) state, as already seen in Fig. 3c. The ERS (high-VT) state instead will transmit the input frequency to the output, as experimentally observed in the time-domain signal in Fig. 6b. Supplementary Fig. 5.2 indeed confirms the high spectral purity of the transmitted frequency f = 1 kHz, with more than 98% of the power concentration. Thus, Fig. 6 not only shows the experimental implementation of the discrete FM for FSK, but also demonstrates the reconfigurability concept between the frequency multiplication and transmission modes in a single FeFET device.

Fig. 6: Binary FSK by PRG/ERS operations.
figure6

a, Binary data 1 and 0 are encoded by shifting the right branch of the IDVG curve under PRG and ERS operations, respectively. The carrier is superimposed to the same d.c. gate bias and only in the case of PRG is doubled at the output. b, Experimental FSK implementation of the binary sequence 1-0-1-0. The PRG and ERS pulses were (+4.5 V, 1 μs) and (−4.5 V, 1 μs), respectively. The sinusoidal input had frequency 1 kHz and peak-to-peak amplitude 1.6 V. The 0s and 1s at the input correspond to the two discrete frequency values of 1 kHz and 2 kHz at the output, respectively.

Although a PRG/ERS pulse duration of 1 μs was used here, this value can be lowered considerably so as not to limit the FSK bandwidth. This can be done, for example, by exploiting the time–voltage switching trade-off of the ferroelectrics, where the switching time decreases exponentially by linearly increasing the PRG/ERS pulse amplitude, as reported in our previous work15. Ultimate switching times of a few hundreds of picoseconds may be expected, as experimentally demonstrated by Li and others32.

Finally, it should be noted that this concept can be easily extended to other digital modulation schemes which do not necessarily need to change the signal frequency. Phase-shift keying is one such scheme, where the phase of the carrier wave is modulated. For this application, a square data signal encoding 1 s and 0 s should bias the FeFET at the left and right branch of the IDVG, resulting in two sinusoidal output signals with a phase difference of 180°, as illustrated in Supplementary Fig. 9. Moreover, analogously to the graphene-based devices9, frequency mixing may be another appealing application of FeFETs, for example in modern wireless communication systems. In fact, the symmetric IDVG typically shows predominant even-order harmonics, whereas the odd-order ones are attenuated. By introducing two sinusoidal inputs at the FeFET gate, a sum and a difference of the input frequencies, as well as other even-order harmonics should be found at the output.

Conclusions

We have reported a purely electrical method to obtain a symmetric and rectifying ID–VG curve in a HfO2-based ferroelectric transistor. This is achieved by carefully adjusting the GIDL current and by partially switching the ferroelectric polarization in the gate stack. Both processes are monotonically tunable, giving rise to the possibility of reconfigurable ID–VG curves between symmetric or highly asymmetric shapes. A symmetric curve (FeFET in the low-VT state) was used to double the frequency of the signal applied at the gate (multiplication mode), whereas the asymmetric curve (FeFET in the high-VT state) transmitted the input frequency to the output (transmission mode), thus demonstrating a dual and reconfigurable functionality within a single device. Such a simple frequency multiplier was then used to experimentally implement two schemes of binary FSK for data transmission encoding. Moreover, it was pointed out that the peculiar nonlinearity of the ID–VG curve opens up the possibility of further RF applications, such as frequency mixers.

The key features of our HfO2-based FeFETs, which could prove valuable in the development of frequency multiplication applications, are its purely electrical ID–VG shaping, reconfigurability, advanced integration and scaling.

In regard to the electrical ID–VG shaping, the symmetry of the ID–VG curve can be monotonically tuned by electrical signals only (Figs. 1 and 2), which may be useful in overcoming potential circuit mismatches in a post-fabrication stage or to vary the operating point according to a desired specification/application. It could also be a powerful tool to selectively enhance or suppress desired harmonics.

In terms of reconfigurability, the FeFET functionality can be reversibly switched between the frequency doubling mode (fout = 2fin) and the frequency transmission mode (fout = fin), just by programming it to the low-VT or high-VT state, respectively (Fig. 6 and Supplementary Section 5).

For advanced integration, the HfO2-based FeFET can be fabricated easily using existing complementary metal–oxide–semiconductor (CMOS) processes and infrastructures due to the compatibility and wide employment of HfO2 in the semiconductor industry. This has recently led to the achievement of several FeFET milestones, including FeFETs in fully depleted silicon-on-insulator (FDSOI)18, FinFET33, junction-less34 and vertical 3D35 technologies. Moreover, the recent co-integration of FeFETs with conventional logic transistors sharing the same active area (Supplementary Section 7) is paving the way to the realization of densely packed and low-parasitic FeFET-based circuits.

FeFETs are fully functional upon aggressive lateral scaling, as has been experimentally reported down to channel lengths of L = 30 nm (ref. 15) and 20 nm (ref. 18) We have investigated frequency multiplication in devices down to L = 80 nm, which displayed proper doubling behaviour similar to that in Fig. 3c (Supplementary Section 8), illustrating their scaling potential in this new application.

The operating frequencies reported here were limited to the MHz range due to the limitations of our set-up. However, the FeFET-based multiplier is expected to operate in the GHz regime when fully integrated into a chip and on adopting further frequency boosters, such as a higher-mobility channel (strained Si, SiGe or Ge), FinFET, multi-gate or gate-all-around structures or SOI devices. In fact, transition frequency (fT) values up to 314 GHz (ref. 36) and 485 GHz (ref. 37) have been reported for 14 nm FinFET and SOI technology, respectively.

Methods

Device fabrication

The gate stack of devices used in this work consisted of layers of polysilicon/TiN (gate electrode), 8 nm Si:HfO2, 0.8 nm SiON and Si substrate, fabricated in a manner similar to that reported previously15,17. Around 4 mol% of Si doping was introduced into HfO2 during the deposition to induce the ferroelectric orthorhombic phase in the film after annealing. A two-step lithographic process defined the transistor lateral dimensions (1 μm channel width and 1 μm channel length). The source and drain n+ regions were obtained by P ion implantation, activated by a rapid thermal annealing at ~1,000 °C. This anneal also crystallized the ferroelectric layer.

Electrical characterization

Write and read operations were performed on the FeFETs with a Keithley 4200-SCS Semiconductor Analyzer with 4225-PMU pulse measurement units. All measurements were carried out in a voltage pulsed approach to avoid excessive device stress and parasitic charge trapping. The gate leakage was negligible (IG < 2 pA) for all VG values used here (Supplementary Section 3). The sinusoidal and square pulses used in Figs. 36 were supplied by an arbitrary waveform generator (Agilent 81160A). The output voltage, Vout, in Figs. 36 was collected at a Tektronix TDS7154B digital phosphor oscilloscope.

Data availability

The data that support the plots within this paper and other findings of this study are available from the corresponding author upon reasonable request.

References

  1. 1.

    Camargo, E. Design of FET Frequency Multipliers and Harmonic Oscillators (Artech House, 1998).

  2. 2.

    Räisänen, A. V. Frequency multipliers for millimeter and submillimeter wavelengths. Proc. IEEE 80, 1842–1852 (1992).

    Article  Google Scholar 

  3. 3.

    Tolmunen, T. J. & Frerking, M. A. Theoretical performance of novel multipliers at millimeter and submillimeter wavelengths. Int. J. Infrared Millimeter Waves 12, 1111–1133 (1991).

    Article  Google Scholar 

  4. 4.

    Xu, H. Q. Electrical properties of three-terminal ballistic junctions. Appl. Phys. Lett. 78, 2064–2066 (2001).

    Article  Google Scholar 

  5. 5.

    Shorubalko, I. et al. A novel frequency-multiplication device based on three-terminal ballistic junction. IEEE Electron Device Lett. 23, 377–379 (2002).

    Article  Google Scholar 

  6. 6.

    Wang, H., Nezich, D., Kong, J. & Palacios, T. Graphene frequency multipliers. IEEE Electron Device Lett. 30, 547–549 (2009).

    Article  Google Scholar 

  7. 7.

    Wang, Z. et al. A high-performance top-gate graphene field-effect transistor based frequency doubler. Appl. Phys. Lett. 96, 173104 (2010).

    Article  Google Scholar 

  8. 8.

    Wang, Z. et al. Large signal operation of small band-gap carbon nanotube-based ambipolar transistor: a high-performance frequency doubler. Nano Lett. 10, 3648–3655 (2010).

    Article  Google Scholar 

  9. 9.

    Wang, H., Hsu, A., Wu, J., Kong, J. & Palacios, T. Graphene-based ambipolar RF mixers. IEEE Electron Device Lett. 31, 906–908 (2010).

    Article  Google Scholar 

  10. 10.

    Yang, X., Liu, G., Baladin, A. A. & Mohanram, K. Triple-mode single-transistor graphene amplifier and its applications. ACS Nano 4, 5532–5538 (2010).

    Article  Google Scholar 

  11. 11.

    Miller, S. L. & McWhorter, P. J. Physics of the ferroelectric nonvolatile memory field effect transistor. J. Appl. Phys. 72, 5999 (1992).

    Article  Google Scholar 

  12. 12.

    Sakai, S. & Takahashi, M. Recent progress of ferroelectric-gate field-effect transistors and applications to nonvolatile logic and FeNAND flash memory. Materials 3, 4950–4964 (2010).

    Article  Google Scholar 

  13. 13.

    Böscke, T. S., Müller, J., Bräuhaus, D., Schröder, U. & Böttger, U. Ferroelectricity in hafnium oxide thin films. Appl. Phys. Lett. 99, 102903 (2011).

    Article  Google Scholar 

  14. 14.

    Tian, X. et al. Evolution of ferroelectric HfO2 in ultrathin region down to 3 nm. Appl. Phys. Lett. 112, 102902 (2018).

    Article  Google Scholar 

  15. 15.

    Mulaosmanovic, H. et al. Switching kinetics in nanoscale ferroelectric field-effect transistors based on hafnium oxide. ACS Appl. Mater. Interfaces 9, 3792–3798 (2017).

    Article  Google Scholar 

  16. 16.

    Park, M. H. et al. Ferroelectricity and antiferroelectricity of doped thin HfO2-based films. Adv. Mater. 27, 1811–1831 (2015).

    Article  Google Scholar 

  17. 17.

    Trentzsch, M. et al. A 28 nm HKMG super low power embedded NVM technology based on ferroelectric FETs. In Proc. 2016 IEEE International Electron Devices Meeting 11.5.1–11.5.4 (IEEE, 2016).

  18. 18.

    Dünkel, S. et al. A FeFET based super-low-power ultra-fast embedded NVM technology for 22 nm FDSOI and beyond. In Proc. 2017 IEEE International Electron Devices Meeting 19.7.1–19.7.4 (IEEE, 2017).

  19. 19.

    Mulaosmanovic, H., Mikolajick, T. & Slesazeck, S. Accumulative polarization reversal in nanoscale ferroelectric transistors. ACS Appl. Mater. Interfaces 10, 23997–24002 (2018).

    Article  Google Scholar 

  20. 20.

    Mulaosmanovic, H., Chicca, E., Bertele, M., Mikolajick, T. & Slesazeck, S. Mimicking biological neurons with a nanoscale ferroelectric transistor. Nanoscale 10, 21755–21763 (2018).

    Article  Google Scholar 

  21. 21.

    Nishitani, Y., Kaneko, Y., Ueda, M., Morie, T. & Fujii, E. Three-terminal ferroelectric synapse device with concurrent learning function for artificial neural networks. J. Appl. Phys. 111, 124108 (2012).

    Article  Google Scholar 

  22. 22.

    Mulaosmanovic, H. et al. Novel ferroelectric FET based synapse for neuromorphic systems. In Proc. IEEE 2017 Symposium on VLSI Technology T176–T177 (IEEE, 2017).

  23. 23.

    Mulaosmanovic, H., Mikolajick, T. & Slesazeck, S. Random number generation based on ferroelectric switching. IEEE Electron Device Lett. 39, 135–138 (2018).

    Article  Google Scholar 

  24. 24.

    Breyer, E. T., Mulaosmanovic, H., Mikolajick, T. & Slesazeck, S. Reconfigurable NAND/NOR logic gates in 28 nm HKMG and 22 nm FD-SOI FeFET technology. In Proceedings of the 2017 IEEE International Electron Devices Meeting 28.5.1–28.5.4 (IEEE, 2017).

  25. 25.

    Salahuddin, S. & Datta, S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett. 8, 405–410 (2008).

    Article  Google Scholar 

  26. 26.

    Chen, J., Chan, T. Y., Chen, I. C., Ko, P. K. & Hu, C. Subbreakdown drain leakage current in MOSFET. IEEE Electron Device Lett. 8, 515–517 (1987).

    Article  Google Scholar 

  27. 27.

    Sakai, S. & Ilangovan, R. Metal–ferroelectric–insulator–semiconductor memory FET with long retention and high endurance. IEEE Electron Device Lett. 25, 369–371 (2004).

    Article  Google Scholar 

  28. 28.

    Tanaka, H. et al. Bit cost scalable technology with punch and plug process for ultra high density flash memory. In Proceedings of IEEE 2007 Symposium on VLSI Technology, 14–15 (IEEE, 2007).

  29. 29.

    Ganjipour, B. et al. Electrical properties of GaSb/InAsSb core/shell nanowires. Nanotechnology 25, 425201 (2014).

    Article  Google Scholar 

  30. 30.

    Simon, M. et al. Top-down technology for reconfigurable nanowire FETs with symmetric on-currents. IEEE Trans. Nanotechnol. 16, 812–819 (2017).

    Article  Google Scholar 

  31. 31.

    Mulaosmanovic, H., Breyer, E. T., Mikolajick, T. & Slesazeck, S. Ferroelectric FETs with 20-nm-thick HfO2 layer for large memory window and high performance. IEEE Trans. Electron Devices 66, 3828–3833 (2019).

    Article  Google Scholar 

  32. 32.

    Li, J. et al. Ultrafast polarization switching in thin-film ferroelectrics. Appl. Phys. Lett. 84, 1174–1176 (2004).

    Article  Google Scholar 

  33. 33.

    Krivokapic, Z. et al. 14 nm ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications. In Proceedings of 2017 IEEE International Electron Devices Meeting 15.1.1–15.1.4 (IEEE, 2017).

  34. 34.

    Seo, M. et al. First demonstration of a logic-process compatible junctionless ferroelectric FinFET synapse for neuromorphic applications. IEEE Electron Device Lett. 39, 1445–1448 (2018).

    Article  Google Scholar 

  35. 35.

    Florent, K. et al. Vertical ferroelectric HfO2 FET based on 3-D NAND architecture: towards dense low-power memory. In Proceedings of IEEE 2018 International Electron Devices Meeting 2.5.1–2.5.4 (IEEE, 2018).

  36. 36.

    Singh, J. et al. 14 nm FinFET technology for analog and RF applications. IEEE Trans. Electron Devices 65, 31–37 (2017).

    Article  Google Scholar 

  37. 37.

    Lee, S. et al. Record RF performance of 45 nm SOI CMOS technology. In Proceedings of IEEE 2007 International Electron Devices Meeting 255–258 (IEEE, 2007).

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Acknowledgements

We thank S. Dünkel, S. Beyer, M. Trentzsch and other colleagues from GLOBALFOUNDRIES Fab1 LLC & Co. KG, Dresden for sample fabrication, support and discussions. We also acknowledge V. Havel from NaMLab gGmbH for useful suggestions regarding the measurement set-up. This work was supported financially by the European Fund for Regional Development (EFRD), Europe Supports Saxony and by funds released by the delegates of the Saxon State Parliament.

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H.M. conceived, designed and performed the experiments, analysed the data and wrote the manuscript. All authors contributed to discussing the data and revising the manuscript. All authors have given approval to the final version of the manuscript.

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Correspondence to Halid Mulaosmanovic.

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Mulaosmanovic, H., Breyer, E.T., Mikolajick, T. et al. Reconfigurable frequency multiplication with a ferroelectric transistor. Nat Electron 3, 391–397 (2020). https://doi.org/10.1038/s41928-020-0413-0

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