Designs for a two-dimensional Si quantum dot array with spin qubit addressability

Abstract

Electron spins in Si are an attractive platform for quantum computation, backed with their scalability and fast, high-fidelity quantum logic gates. Despite the importance of two-dimensional integration with efficient connectivity between qubits for medium- to large-scale quantum computation, however, a practical device design that guarantees qubit addressability is yet to be seen. Here, we propose a practical 3 × 3 quantum dot device design and a larger-scale design as a longer-term target. The design goal is to realize qubit connectivity to the four nearest neighbors while ensuring addressability. We show that a 3 × 3 quantum dot array can execute four-qubit Grover’s algorithm more efficiently than the one-dimensional counterpart. To scale up the two-dimensional array beyond 3 × 3, we propose a novel structure with ferromagnetic gate electrodes. Our results showcase the possibility of medium-sized quantum processors in Si with fast quantum logic gates and long coherence times.

Introduction

Semiconductor spin qubits based on electron spins are an attractive candidate for a quantum processor^1,2. As they can be manufactured using existing micro-fabrication techniques, it may be possible to integrate millions of qubits required for fault-tolerant quantum computation^3,4,5. Electron spin qubits in Si in particular have attracted a good deal of attention in recent years because of their long coherence times and high-fidelity quantum logic gates and readout^{6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27}. While one-dimensional qubit arrays have been employed in these pioneering experiments so far, some blueprints of two-dimensional integration have been presented for efficient connectivity between qubits^28,29,30. In order to overcome the wiring issue which poses a bottleneck for qubit integration, previous proposals typically assume advanced fabrication capabilities or device homogeneity that are yet to be developed. However, in the intermediate term, device designs consistent with established fabrication techniques and observed device variabilities would be desirable.

In this study, we propose feasible designs of a two-dimensional Si quantum dot (QD) array with spin qubit addressability. First, we discuss a device design of a 3 × 3 QD array, which is the smallest two-dimensional square array with a QD connected to the four nearest neighbors, by largely relying on device fabrication processes established in academic laboratories^22,24. We assess the effect of improved qubit connectivity against a 2 × 4 counterpart through the performance analysis of a four-qubit Grover's algorithm³¹. Next, as a longer-term approach, we propose a larger scale two-dimensional QD array with Co gates for fast spin manipulation and an additional Co magnet for qubit addressability. We introduce vias to enhance the QD density and connectivity, which is helpful for large quantum circuits. Our results present a potential pathway toward the development of quantum processors in Si comprising more than a thousand of spin qubits, with high-fidelity quantum logic gates and long coherence times.

Results

3 × 3 QD array

Figure 1 illustrates our proposal of a 3 × 3 QD array. Figure 1a shows a model in which nine QDs are formed within a Si/SiGe heterostructure. We assume QD regions of 70-nm squares (red regions) separated by 50-nm barrier gates (deep blue regions) that are used to control exchange interactions between the adjacent QDs. The reservoirs (orange regions) connected to ohmic contacts (not shown) supply electrons to the QDs.

Figure 1

Schematics of a device design with a 3 × 3 QD array (a) Device layer structure and 3 × 3 QD array schematic in Si QW. Silver spheres with arrows represent spins in QDs. Labels B and R in the array represent barrier gates and reservoirs, respectively. (b) Layer stack of overlapping Al gates. The electron spin symbol is displayed when the corresponding control gate electrode is fabricated in the layer. This device can be fabricated with four layers of overlapping gates. An overlay accuracy of 10 nm is assumed. (c), (d) Cross sections of the QDs (A–A′) and barrier gates (B–B′) in (b). The gate thickness increases in the upper layers to ensure gate continuity. In (d), the black and gray areas are both SiO₂, with the Si layer underneath etched in the latter. (e) Electrostatic potential in the Si QW at applied voltages of 0.6 V on plunger gates and 0.4 V (0.3 V) on the barrier gates between QDs (between a QD and a reservoir). (e) is drawn with COMSOL Multiphysics ver. 5.5 (https://www.comsol.com).

We consider two approaches to deplete electrons outside the QDs and reservoirs. The first one is etching followed by SiO₂ deposition and the second one is to use screening gates. Figure 1b shows a layer-by-layer schematic of overlapping Al gates³² in the first approach, and Fig. 1c, d show vertical cross sections at the QD position and the barrier gate centers, respectively. In the first approach, a chemical mechanical polishing process may be used to obtain SiO₂ layer planarization^33,34, easing the deposition of four overlapping gate layers—two for barrier gates (the first- and third-layer gates) and the other two for plunger gates (the second- and fourth-layer gates). Table 1 summarizes the layer indexes, gate names, and colors in Fig. 1b–d and the respective gate sizes. In this approach, we can reduce the number of overlapping gate layers. On the other hand, we do not have to perform etching and SiO₂ deposition in the second approach. In the following, we consider the array architecture realized in the first approach.

Table 1 Overlapping-layer gate characteristics.

We confirm the formation of electrostatic potentials for each QD in a Si quantum well (QW) in the room temperature simulation (Fig. 1e) carried out using COMSOL Multiphysics. It is seen from the figure that nine QDs are formed under every plunger gate, each of them is separated from the neighboring QDs and reservoirs by barrier gates.

Qubit operation in a two-dimensional QD array

In order to utilize this QD array as a quantum processor, it needs to be capable of spin readout, initialization, and manipulation. While this device does not have dedicated change sensor QDs, spin readout can be performed by the gate-based sensing techniques to detect the Pauli spin blockade (PSB) between neighboring QDs^15,20. The spin state can be initialized, for instance, by relaxation to the doubly occupied ground singlet state and rapid adiabatic passage²⁷. For spin manipulation, we employ the electric-dipole spin resonance (EDSR) control based on micromagnets (MMs). The advantage of this scheme is that we can control the resonance frequency difference $\left( {{\Delta }f_{{\text{r}}} } \right)$ between neighboring QDs with the MM design^35,36,37. While spin manipulation can also be implemented with ESR striplines^{7,8,14,25,27,28,29,30}, the control of ${\Delta }f_{{\text{r}}}$ in this case relies on the difference of g-factors between QDs and it may be difficult to obtain controlled ${\Delta }f_{{\text{r}}}$ across a large QD array with device viabilities^7,8,14. In contrast, MMs can potentially control $f_{{\text{r}}}$ and ${\Delta }f_{{\text{r}}}$ in a consistent manner across the qubit array by properly designing them, as we will show through simulations in the following.

Figure 2a shows the MM design for inducing the spatially inhomogeneous magnetic field ($B_{{{\text{MM}}}}$) in which the external magnetic field ($B_{{{\text{ext}}}}$) is applied in the direction of the arrow. The MM field $B_{{{\text{MM}}}}$ contains two essential components¹²: a transverse field ($b_{{{\text{trans}}}}$) perpendicular to $B_{{{\text{ext}}}}$ and a longitudinal field ($B_{{{\text{long}}}}$) parallel to $B_{{{\text{ext}}}}$. $b_{{{\text{trans}}}}$ enables spin rotations combined with a QD displacement ($\Delta x$) by inducing an effective oscillating magnetic field. On the other hand, $B_{{{\text{long}}}}$ provides the qubit addressability by shifting the Zeeman energy at each QD. Moreover, this QD-dependent energy shift is essential for implementing two-qubit gates such as the controlled-not gate^8,9, controlled-phase gate^8,10 and resonant SWAP gate^17,22. For high fidelity single-qubit gates, $f_{{{\text{Rabi}}}}$ faster than 1 MHz is desirable^9,12.

Figure 2

The schematics of MM design and simulation results. (a) MM design. The right panel illustrates the layout of the MM (yellow) along with the 3 × 3 QD array (center), designed so that the values of $\Delta f_{{\text{r}}}$ are robust against misalignment between the QD array and the MM. The magnet is 250 nm thick and 143 nm apart from the bottom of the magnet to the QD. Left panel shows an enlarged view of the region surrounded by the black dashed rectangle in the right. The magnet has a groove in the middle with its shape shown by the red dashed rectangle to make $\Delta f_{{\text{r}}}$ in each QD row moderate. $B_{{{\text{ext}}}}$ indicates the direction of the external magnetic field. (b), (c) Simulation results for $b_{{{\text{trans}}}}$ and $B_{{{\text{long}}}}$ in the Si QW. Magnetization of the MM is 1400 kA/m in the direction parallel to $B_{{{\text{ext}}}}$. (b), (c) are drawn with COMSOL Multiphysics.

Table 2 and Fig. 2b show the simulated transverse field slope ($b_{{{\text{trans}}}}$) at the QD positions. $b_{{{\text{trans}}}}$ at each QD position is calculated to be 0.56–1.2 mT/nm, comparable to the values in the previously demonstrated linear QD arrays¹². We estimate $f_{{{\text{Rabi}}}}$ to be 6.8–14 MHz assuming a conversion factor from $b_{{{\text{trans}}}}$ to $f_{{{\text{Rabi}}}}$ of 12 MHz nm/mT, which is taken from previous experiment⁹. We assume that the MW drive is applied to the barrier gate next to the QD (along $B_{{{\text{ext}}}}$) to maximize $f_{{{\text{Rabi}}}}$. In order to assess the qubit addressability, we calculate $B_{{{\text{long}}}}$ (Fig. 2c and Table 3). The minimum $B_{{{\text{long}}}}$ difference ($\Delta B_{{{\text{long}}}}$) over the set of nine QDs is 6 mT (between Q₂₃ and Q₃₃) and it corresponds to $\Delta f_{{\text{r}}}$ of 160 MHz. This is much larger than our calculated $f_{{{\text{Rabi}}}}$ and therefore large enough to prevent the crosstalk of single-qubit gates. These results show this MM design can induce field gradients necessary for the qubit addressability even in a 3 × 3 QD array.

Table 2 $b_{{{\text{trans}}}}$ and $f_{{{\text{Rabi}}}}$ at each QD position.

Table 3 $B_{{{\text{long}}}}$ and $\Delta f_{{\text{r}}}$ at each QD position; $\Delta f_{{\text{r}}}$ is calculated with respect to the center QD.

Efficient quantum circuit execution in a two-dimensional QD array

One of the potential advantages of two-dimensional qubit arrays is the reduced circuit depth of quantum algorithm implementations thanks to better qubit connectivity³⁸. Here, we discuss the efficiency of the four-qubit Grover’s search algorithm³¹ implemented in our two-dimensional QD array, see Fig. 3a. This algorithm allows one to search for $\left. {\left| {q_{3} q_{2} q_{1} q_{0} } \right.} \right\rangle = \left| {\left. {1101} \right\rangle } \right.$ using the superposition of four qubits with the same probability (we define $\left. {\left| 0 \right.} \right\rangle$ by the spin down state). The four-qubit Toffoli gates play a central role in implementing this circuit and can be synthesized from 15 two-qubit gates including 2 SWAP gates for compensating the lack of direct qubit couplings (Fig. 3b) ^39,40 (see Methods for the details). The spin state of qubit q_X is read out by PSB with a measurement ancilla qubit M_qX. For comparison, we consider a linear array of four QDs which are lined up together with adjacent QDs for spin readout as shown in Fig. 3c. In this qubit layout, 18 two-qubit gates including 5 SWAP gates are necessary to implement a four-qubit Toffoli gate. This shows that the two-dimensional QD array enables efficient quantum circuit execution due to improved qubit connectivity.

Figure 3

Quantum circuits for four-qubit Grover’s search algorithm. (a) Quantum circuit for implementing a four-qubit Grover’s search algorithm. H, X, Z, and M indicate Hadamard gate, Pauli-X gate, Pauli-Z gate, and spin state measurement, respectively. This circuit is optimized to reduce the number of quantum gates³⁹. Four qubits are prepared in an equally weighted superposition state and then the probability of $\left. {\left| {q_{3} q_{2} q_{1} q_{0} } \right.} \right\rangle = \left| {\left. {1101} \right\rangle } \right.$ is amplified once. (b), (c) Implementation examples of a four-qubit Toffoli gate in two-dimensional (b) and one-dimensional (c) QD arrays using SWAP and controlled rotation gates (see Methods). Four red QDs are used for computation and four green QDs host ancillas for spin state initialization and measurement using PSB. Bottom-right QD in (b) is not used in this example.

A larger scale two-dimensional array

The scalability of the EDSR control based on MMs has often been questioned because of its difficulty in inducing strong field gradients over large areas³⁰. We have nevertheless shown that it is possible to induce field gradients in a small two-dimensional QD array. In the following, we propose a longer-term design approach that allows us to apply $B_{{{\text{long}}}}$ while ensuring sufficient $b_{{{\text{trans}}}}$ for each QD in a large two-dimensional array. The simple idea behind this approach is to decouple the magnet inducing $b_{{{\text{trans}}}}$ from the one inducing $B_{{{\text{long}}}}$. Under the device design shown in Fig. 4a, $b_{{{\text{trans}}}}$ is induced by the plunger and barrier gate electrodes made of Co instead of Al, whereas $B_{{{\text{long}}}}$ is induced by a large Co magnet located outside of the QD array. This structure may be amenable to a larger qubit array with fast, MM-mediated electrical spin control at the expense of introducing vias to enhance QD density and connectivity as compared to the 3 × 3 QD array.

Figure 4

Quantum processor with larger numbers of QDs with novel magnet structure. (a) Model of a quantum processor utilizing a novel magnet structure with a large Co magnet and Co gates. The right figure shows a zoom-in of the red dotted area in the left figure. The whole 5 × 5-µm² array contains approximately 1600 QDs. (b) Implementation example of qubits and ancillas for spin state initialization and measurement in a larger two-dimensional array. It only shows a 9 × 9 QD array, but we can straightforwardly scale it up to a larger one. (c), (d) Simulated values of $B_{{{\text{long}}}}$ slope in the x and y directions induced by a large Co magnet (30 × 30 × 5 µm³) located outside the QD array. The yellow square indicates the position of a 5 × 5-µm² QD array, in which ${\Delta }B_{{{\text{long}}}}$ is sufficiently large. By tuning the magnet aspect ratio, it may be possible to control the distribution of the magnetic field so that a larger QD array may be accommodated. (e) Simulated values of $b_{{{\text{trans}}}}$ induced by Co gates. For simulation simplicity, a 5 × 5 QD array is shown, with the positions of spin qubits illustrated by symbols. (c–e) are drawn with COMSOL Multiphysics.

Under this novel magnet structure, it would be possible to integrate about 40 × 40 = 1600 QDs within a 5 × 5-µm² area because each QD occupies only 120 × 120-nm². Assuming that PSB is used for spin state initialization as discussed above, we can consider an example of implementing qubits and ancillas in this QD array as shown in Fig. 4b. In this example, the 3 × 3 QD array consisting of 4 data qubits (red) and 4 ancillas functions as a unit cell. QDs with a cross are not used, so they can be empty, in which case coherent inter-site qubit transport²⁵ may be used to maintain high qubit connectivity. Alternatively, in the case of single occupancy, two-qubit exchange gates¹⁷ would be needed for connection. As can be seen from this example, such a device would be able to host more than a thousand of qubits, a number of qubits much larger than those in any other existing quantum processors^{41,42,43,44,45}, in a way compatible with high qubit connectivity and the spin operation scheme discussed above.

Figures 4c, d show simulated values of $B_{{{\text{long}}}}$ slope in the x and y directions induced by a large Co magnet located outside the QD array (yellow square). In the QD array, the $\Delta f_{{\text{r}}}$ values between the nearest-neighbor QDs are larger than 100 MHz (corresponding to > 0.03 mT/nm), which are sufficient for unconditional single-qubit operations and two-qubit gate manipulations. Figure 4e shows simulated values of $b_{{{\text{trans}}}}$ induced by the Co gates. Although the formation of QDs in such a gate structure may not have been demonstrated, the electrostatic potential of each QD can be controlled independently by the plunger gate and the interaction between neighboring QDs can be adjusted by the barrier gate, ensuring precise manipulation of qubits. This electrical controllability, in conjunction with local magnetic fields, may also be used to compensate for qubit frequency shifts that can potentially be induced by the strain electric and the stray magnetic fields. Here, we use a 5 × 5 QD array for simulation simplicity and assume the gate sizes of Co plunger and barrier gates are 60 nm × 60 nm and 60 nm × 40 nm, respectively. The estimated average value of $f_{{{\text{Rabi}}}}$ for the 25 QDs is 39 MHz (assuming the same conversion factor used in the previous discussion), which is about three times faster than that in the 3 × 3 array discussed above owing to the close proximity of the magnet and QDs. The value of $b_{{{\text{trans}}}}$ induced by the Co gates is more than ten times larger than the transverse component of the field induced by the large Co magnet, so that we can safely approximate it to be due to the Co gates. By applying the proposed magnet fabrication approach, quantum processors with large numbers of qubits may be achieved with high-speed qubit manipulation, leveraging mature fabrication and integration techniques in Si. We anticipate that even larger arrays will be possible by further improving the magnet design.

Discussion

In this study, we discuss the feasible device designs of a two-dimensional Si QD array for multi-qubit quantum processing with qubit addressability. We reveal the possibility to provide qubit addressability in the two-dimensional array of 3 × 3 QDs, which can execute quantum circuits more efficiently compared with the one-dimensional array. We note that this method is essentially based on experimentally realized MM and QD structures with device viabilities. We have furthermore presented a possibility of hosting hundreds of qubits with $f_{{{\text{Rabi}}}}$ increased by roughly three times by employing a novel magnet-incorporated QD structure. We believe both methods will allow to scale up QD array sizes, to a level that was previously thought to be difficult with this scheme, while maintaining consistency with established fabrication techniques and qubit controllability in the presence of observed device variabilities. Our results have shown how to guarantee qubit addressability when electron spin qubits in Si are integrated to a larger scale. Quantum processors with large numbers of qubits, high-fidelity quantum logic gates, and long coherence times might accelerate research on quantum algorithms and architectures, enhancing the potential of quantum computing.

Methods

The method for mapping quantum circuits to QD arrays

We employed Qiskit’s LookaheasSwap routing method⁴⁰ for mapping quantum circuits via insertion of SWAP gates to construct quantum circuits for four-qubit Grover’s search algorithm. This method repeats the process of selecting the SWAP gate that maximizes the number of subsequent executable two-qubit gates when there is a two-qubit gate that cannot be executed in the current physical qubit layout. While Qiskit provides other methods to map circuits by inserting SWAP gates, we chose this method because it produces the circuit with smaller numbers of SWAP gates for both two-dimensional and one-dimensional QD arrays.