A quantitative approach for trap analysis between Al_0.25Ga_0.75N and GaN in high electron mobility transistors

Abstract

The characteristics of traps between the Al_0.25Ga_0.75N barrier and the GaN channel layer in a high-electron-mobility-transistors (HEMTs) were investigated. The interface traps at the Al_0.25Ga_0.75N/GaN interface as well as the border traps were experimentally analyzed because the Al_0.25Ga_0.75N barrier layer functions as a dielectric owing to its high dielectric constant. The interface trap density D_it and border trap density N_bt were extracted from a long-channel field-effect transistor (FET), conventionally known as a FATFET structure, via frequency-dependent capacitance–voltage (C–V) and conductance–voltage (G–V) measurements. The minimum D_it value extracted by the conventional conductance method was 2.5 × 10¹² cm⁻²·eV⁻¹, which agreed well with the actual transistor subthreshold swing of around 142 mV·dec⁻¹. The border trap density N_bt was also extracted from the frequency-dependent C–V characteristics using the distributed circuit model, and the extracted value was 1.5 × 10¹⁹ cm⁻³·eV⁻¹. Low-frequency (1/f) noise measurement provided a clearer picture of the trapping–detrapping phenomena in the Al_0.25Ga_0.75N layer. The value of the border trap density extracted using the carrier-number-fluctuation (CNF) model was 1.3 × 10¹⁹ cm⁻³·eV⁻¹, which is of a similar level to the extracted value from the distributed circuit model.

Introduction

Recently, GaN-based high-electron-mobility-transistors (HEMTs) have gained considerable attention because of their outstanding material properties and device performance, including power and RF applications up to the sub-terahertz regime^1,2,3. These advantageous properties and performance are attributable mainly to the high quality of the epitaxial layer comprising the Al_xGa_1−xN barrier and the GaN channel layer, which causes the formation of two-dimensional electron gas (2DEG) on top of Si, Sapphire, and SiC substrates^4,5. The quality of the Al_xGa_1−xN/GaN interface is crucial to the improvement of the carrier transport in the channel during device operation^6,7. In addition to the performance of AlGaN/GaN HEMTs, their reliability is an ongoing topic of research that requires examination of a variety of factors. Most of the reliability issues are related to the AlGaN layer, which is the surface layer in the gate-to-drain access region and contains deep-level traps⁸. These issues become more critical in deeply scaled transistors for high-frequency applications. Most previous research on the reliability of AlGaN/GaN HEMTs focused mainly on the surface traps in the access region and on their passivation using dielectric materials^9,10. Plasma treatment was also utilized to decrease these deep-level traps in the AlGaN barrier layer¹¹. Characterization of interface traps and deep-level border traps is important for improving the 2DEG carrier concentration and reducing interface roughness scattering to enhance mobility, with the eventual aim of improving device reliability and performance. Previous studies focused on the characterization of traps formed at the insulator/AlGaN interface in a metal–oxide–semiconductor field-effect transistor (MOSFET) structure via frequency-dependent capacitance–voltage (C–V) and conductance–voltage (G–V) measurements^9,10. Some studies even discussed the interface trap states in AlGaN/GaN Schottky-HEMT as well as MOS-HEMT but their results conclude that the trap states are mainly located at the surface interface within the dielectric or the passivation layer^12,13. However, from a device point of view, characterization of the AlGaN/GaN interface would be more beneficial because this interface is directly related to carrier transport.

In this study, we tried to include all types of AlGaN/GaN interfacial trapping analysis for a better understanding. We extracted the interface trap density (D_it) between AlGaN and GaN and the deep-level/border trap density N_bt in the AlGaN barrier layer in a long-channel AlGaN/GaN HEMT fabricated on a SiC substrate. We mainly focused on the trap states inside the AlGaN layer, located at the interface and near the interface of the AlGaN/GaN, and tried to eliminate other probable interfacial trap contributing factors such as dielectric layers for passivation. We used the conventional frequency-dependent C–V and G–V characteristics to understand the interactions of the interface traps^14,15. Along with these characteristics, we also investigated the deep-level/border trap behavior in the accumulation region by examining split C–V characteristics, which are typically observed in the conventional Si MOS structure^16,17. Although some researchers have discussed border/bulk trap extraction with threshold voltage shift profiling, discharging-based trap energy profile technique, etc., the frequency-dependent CV method for border trap density extraction for AlGaN/GaN heterostructure is not present^18,19,20. We further performed low-frequency (1/f) noise measurements as they are a highly powerful tool for analyzing the defects and impurities in semiconductor devices and because they aid in the estimation of the efficiency and reliability of these devices²¹.

Experimental details

Figure 1a illustrates the cross-sectional schematic and the transmission electron microscopy (TEM) image of the HEMT device used in this study. Epitaxial layers were grown on a semi-insulating 330 µm SiC substrate by metal–organic-chemical-vapor-deposition (MOCVD). Layers were deposited from bottom to top in the following order: an AlN nucleation layer, a 2.6 µm high-resistance GaN layer, a 150 nm GaN channel, and a 28 nm Al_0.25Ga_0.75N barrier layer. Hall measurements revealed the mobility (µ_{n_Hall}) and the sheet charge density (2DEG) to be 2200 cm²·V⁻¹·s⁻¹ and 9 × 10¹² cm⁻², respectively. Mesa isolation was carried out with Cl₂ based inductively-coupled-plasma (ICP) etching to isolate the devices. Before ohmic metal deposition, the substrate was diluted with a mixture of HCl and deionized water (1:5) for 30 s to remove any kind of formed native oxide. To facilitate ohmic contact formation, a Si/Ti/Al/Ni/Au (1/25/160/40/100 nm) alloy was deposited on source and drain area using an electron beam (e-beam) evaporator and rapid thermal annealing at 830 °C was subsequently performed in N₂ ambient for 30 s. The contact resistance (R_C) and sheet resistance (R_SH) were extracted by transmission-line-method (TLM) measurements to be 1.2 Ω·mm and 320 Ω/□ respectively. A Ti/Au (20/300 nm) padding layer was deposited using the E-beam evaporator to achieve strong probe contact. Finally, gate metal consisting of Ni/Au (20/400 nm) was also deposited using e-beam evaporator. The gate length (L_g), gate width (W_g), and source-to-drain distance (L_sd) of the fabricated devices were 14, 50, and 18 µm, respectively. All the devices had the same source-to-gate (L_sg) distance and gate-to-source distance (L_gd) of 2 µm. From the high-resolution TEM image shown in Fig. 1a, the well deposited Al_0.25GaN_0.75N/GaN interface can be observed. The thickness of Al_0.25GaN_0.75N was well around 28 nm (27.8 nm) and formed a good interface with the GaN channel layer.

Figure 1

(a) Schematic cross-section and high-resolution TEM image of Al_0.25Ga_0.75N/GaN device. (b) Equivalent circuit diagram representing metal–insulator–semiconductor structure in depletion mode. (c) Equivalent circuit representing distributed bulk-oxide trap model^16,17.

Extraction model

Interface trap model

In conventional Si MOSFET devices, the conductance method is one of the most popular methods for determining the interface trap density (D_it)^14,22. Typically, the interface between the dielectric and the semiconductor is analyzed for trap extraction. In our study, we applied the conductance method to our device structure. Because the Al_0.25Ga_0.75N barrier layer has a wide band gap (~ 4 eV) and a high dielectric constant (~ 9.4), it can act as an insulator and perform comparably to a dielectric material. The conductance method relies on the extraction of the equivalent parallel conductance (G_P) from the measured frequency-dependent C–V and G–V characteristics. Figure 1b shows the equivalent circuit of a MOSFET in the depletion region, where C_it, C_S and R_S represents the interface trap capacitance, the semiconductor capacitance, and series resistance, respectively. The interface trap capacitance can be expressed as C_it = qD_it (where q denotes the elemental charge). G_P can be determined by the following equation:

$$G_{p} = \frac{{\omega^{2} C_{ins}^{2} G_{c} }}{{G_{c}^{2} + \omega^{2} \left( {C_{ins} - C_{c} } \right)^{2} }}$$

(1)

Here, C_ins is the insulator capacitance; ω is the angular frequency; and C_c and G_c are, respectively, the corrected measured capacitance and conductance corresponding to the series resistance R_S.

Using the normalized (G_P/ω)_max value, we can determine the value of D_it as follows²³:

$$D_{it} \approx \frac{2.5}{{Aq}}\left( {\frac{{G_{p} }}{\omega }} \right)_{\max }$$

(2)

Here, A denotes the device area.

The trap response of the interface states can be determined from the Shockley–Read–Hall statistics of capture and emission²⁴:

$$\tau = \frac{1}{2\pi f} = \frac{1}{\omega } = \frac{{e^{{\left( {\frac{\Delta E}{{K_{B} T}}} \right)}} }}{{\sigma \nu_{th} D_{dos} }}$$

(3)

Here, ΔE denotes the difference of energy between the conduction band E_C and trap energy level E_T. K_B and T are the Boltzmann constant and temperature. σ, v_th and D_dos represent the cross–section of traps, the average thermal velocity, and the effective density of states, respectively.

Border trap model

The distributed circuit model shown in Fig. 1c was used for the extraction of border traps^16,17. It can provide information on the border trap states inside the insulator bulk with frequency-dependent C-V measurement. This model can be represented by the following first-order differential equation:

$$\frac{\partial Y}{{\partial x}} = - \frac{{Y^{2} }}{{j\omega \varepsilon_{ins} }} + \frac{{q^{2} N_{bt} \ln \left( {1 + j\omega \tau } \right)}}{\tau }$$

(4)

This equation has a boundary condition of x = 0, Y = jωC_S, while Y being the total admittance. N_bt in the above equation denotes the density of border traps in the insulator layer.

Usually, the carriers in the channel region and the border traps in the insulator layer can exchange charge through tunneling¹⁶. The average time (τ) required for an empty trap to capture electron can be calculated as²⁵

$$\tau = \tau_{ \circ } e^{2kx}$$

(5)

$${\text{where,}}\;k = \frac{{\sqrt {2m* \times E_{b} } }}{\hbar }$$

Here, τ_o denotes the time constant of the capture and emission of a trap. x denotes the distance between the interface and the trap. m* and k denote the effective mass of the Al_0.25Ga_0.75N layer and the attenuation coefficient respectively. The barrier height between the Al_0.25Ga_0.75N and the GaN channel conduction band is denoted by E_b and the reduced Plank’s constant by ħ.

τ_o can be characterized as

$$\tau_{ \circ } = \left( {n_{s} v_{th} \sigma } \right)^{ - 1}$$

(6)

where n_s, v_th and σ are the electron density of the channel surface, the average thermal velocity of the electron, and the border trap cross-section area of capture/emission, respectively.

Equation 4, can be simplified into the following equation for the total capacitance, C_tot²⁶,

$$C_{tot} = \frac{1}{{\frac{1}{{C_{ins} }} + \frac{1}{{2k\varepsilon_{ins} }}C_{2} (\omega )}}$$

(7)

$$C_{2} (\omega ) = 2k\sqrt {\frac{{\varepsilon_{ins} }}{{qN_{bt} }}} \coth (B) + \ln (\omega \tau_{o} ) - \coth^{2} (B)$$

(8)

$$B = a\tanh \left( {\sqrt {\frac{1}{{qN_{bt} \varepsilon_{ins} }}C_{s} } } \right) - \frac{1}{2k}\sqrt {\frac{{qN_{bt} }}{{\varepsilon_{ins} }}} \ln (\omega \tau_{o} )$$

(9)

Using N_bt and τ_o as fitting parameters, the best-fitted curve of C_tot with respect to frequency can be generated for the measured capacitance which will be discussed more in the results and discussion section.

The probing distance (X_p) of a border trap with a fixed frequency (f) while, ωτ = 1, can be described as²⁷

$$X_{p} = \frac{1}{2k}\ln \frac{1}{{2\pi f\tau_{ \circ } }}$$

(10)

Results and discussion

Figure 2a shows the results of the frequency-dependent C–V measurements of the Al_0.25GaN_0.75N/GaN HEMT where frequency dispersion is evident. Frequency dispersion can be caused by various reasons. Some of the main causes of frequency dispersion during C–V measurement are parasitic effect, lossy interfacial layer, surface roughness, and quantum mechanical confinement etc²⁸. Among them, the most influential reason is the lossy interfacial layer of AlGaN/GaN. The trap states in the AlGaN layer are mostly the reason behind the dispersion. The frequency dispersion in the depletion region indicates that this region is the dominant region for interface traps, whereas the dispersion in the accumulation region indicates the dominant region of the border traps. We used the Nextnano simulation tool (one-dimensional Poisson–Schrodinger solver) to compare the measured and simulated capacitance with respect to a constant gate overdrive (V_GS − V_T), as shown in Fig. 2b. It is evident that both the measured and the simulated C–V curves are similar which indicates lower leakage current effect on the measured data. Thus, the AlGaN layer can be treated as an insulator owing to its high dielectric constant, similar to the MIS/MOS structure. Figure 2c, d show the band diagrams (determined via simulation) in the depletion and accumulation regions, respectively. In the depletion region, the interface traps above the Fermi level E_F are mostly active; this causes the capture and emission of the carriers in the channel region. In the accumulation region, where E_F penetrates the conduction band E_C, the electrons on the surface are captured and emitted by the border traps via tunneling.

Figure 2

(a) Results of frequency-dependent C–V measurements showing active response region of traps. (b) Comparison between measured and simulated C–V characteristics. Simulated band diagram showing trap behavior (c) in depletion and (d) in accumulation.

A Keysight B1500A semiconductor device analyzer and an Agilent 4384A precision LCR meter were used for all DC measurements. 1/f measurements were performed using a setup comprising battery operated SRS SR570 low-noise current preamplifier, HP 35670A dynamic signal analyzer, and a 1 Hz filter unit.

The insulator capacitance was determined by the following equation:

$$C_{ins} = \frac{{\varepsilon_{ \circ } \varepsilon_{ins} }}{{t_{ins} }}$$

(11)

Here, ε_o is the permittivity of free space and ε_ins is the relative permittivity of the Al_0.25Ga_0.75N layer. As it is known from the literature, the value of ε_ins as calculated from ε =  − 0.5x + 9.5—where x denotes the Al content of the Al_xGa_1−xN layer—for x = 25% is around 9.375^29,30. The tensor components of AlN and GaN’s {0001} relative permittivity are linearly interpolated to obtain the relation. The parallel equivalent conductance G_p was calculated using Eq. 1 with correction of the measured capacitance and conductance for the series resistance. Figure 3b shows a plot of the parallel conductance G_p/ω versus the angular frequency ω. D_it was measured from the (G_p/ω)_max peak, using Eq. 2; The extracted value of D_it using the conductance method was in the range of 2.5 × 10¹² cm⁻²·eV⁻¹ to 7.1 × 10¹² cm⁻²·eV⁻¹ which is well within the range of 10¹¹–10¹⁴ cm⁻² eV⁻¹ for S-HEMT and MOS-HEMT from literature^10,12,31. Figure 3a shows the active D_it with respect to the trap energy (ΔE), which was determined from Eq. 3. For this calculation, the frequency corresponding to (G_p/ω)_max was considered. At room temperature (300 K), the average thermal velocity v_th and the effective density of states (D_dos) of the GaN material were considered to be 2.6 × 10⁷ cm·s⁻¹ and 1.2 × 10¹⁸ cm⁻³, respectively³¹. The value of the capture cross-section σ was assumed to be 3.4 × 10⁻¹⁵ cm² from the literature³². The reliability of the extracted value of D_it was determined via a theoretical calculation of the subthreshold swing (SS) using the following equation³³:

$$SS = \frac{kT}{q}\ln 10.\left( {1 + \frac{{qD_{it} }}{{C_{ins} }}} \right)$$

(12)

Figure 3

(a) Distribution of interface traps as a function of band energy state. (b) Equivalent parallel conductance (G_P/ω) with respect to frequency at different gate bias points. (c) Basic transfer curve (log(I_D)–V_GS) showing SS of device.

The value of the SS calculated from the lowest extracted D_it was around 143 mV·dec⁻¹, whereas the value determined by the basic I–V measurement was found to be 142 mV·dec⁻¹ (Fig. 3c). This similarity of the measured and calculated values confirms the reliability of the extracted value of D_it.

We used the parameters in Table 1 to extract the border trap density N_bt. For the calculation of the attenuation coefficient, the effective mass of Al_0.25Ga_0.75N was considered to be 0.19m_o (where m_o denotes the electron mass at rest)³⁴. The semiconductor capacitance C_S was estimated via Nextnano simulation at an accumulation gate bias of − 3.5 V, which was the primary N_bt extraction voltage considered in this study. From Eq. 4, the best-fitted capacitance curves were obtained at − 3.5 V under consideration of N_bt and τ_o as variable fitting parameters. The best-fitted curve was obtained at N_bt = 1.5 × 10¹⁹ cm⁻³·eV⁻¹ and τ_o = 1 × 10⁻¹² s, as shown in Fig. 4a. Here, C_M denotes the capacitances measured at various applied frequencies at − 3.5 V and C_tot represents the fitted curve. The spatial distribution of N_bt as a function of both the applied V_GS and the probing distance into the Al_0.25Ga_0.75N layer from the Al_0.25Ga_0.75N/GaN interface is shown in Fig. 4b. The N_bt values were extracted at various applied voltages at a particular applied frequency. The probing depth into the Al_0.25Ga_0.75N layer from the interface was calculated by Eq. 10 using different τ_o values associated with the N_bt values. Because the border traps exhibit more dominant characteristics at lower frequencies, we employed a low frequency of 10 kHz to extract the probing depth. With an increase in V_GS, the Fermi level E_F tended to penetrate to a greater depth into the conduction band E_C. As a result, more electrons tended to tunnel into the deep-level traps. As all parameters except τ_o were fixed, τ_o showed an inverse relation with the probing depth.

Table 1 Parameters used and extracted values of D_it and N_bt.

Figure 4

(a) Fitting curves generated using distributed circuit model at V_GS =  − 3.5 V. (b) Contour mapping of border trap distribution in Al_0.25Ga_0.75N layer from Al_0.25Ga_0.75N/GaN interface.

1/f noise measurements were performed by varying the gate voltage V_GS and fixing the drain bias V_DS at 0.5 V. Figure 5a shows the normalized S_ID/I_D² (drain current noise spectral density) with respect to frequency up to 10⁴ Hz under varying V_GS from the linear region. It is evident that as V_GS increased, and the device transitioned from weak inversion to strong inversion, noise level (S_ID/I_D²) decreases. Plotting of the normalized S_ID/I_D² as a function of I_D (drain current) provided results that were more explanatory. Figure 5b shows a plot of the normalized S_ID/I_D² (blue spheres) as a function of I_D at a frequency of 10 Hz. The channel carrier trapping phenomenon of the gate dielectric can be explained using the carrier number fluctuation (CNF) model by the following equations^21,35,36:

$$\frac{{S_{ID} }}{{I_{D}^{2} }} = \left( {\frac{{g_{m} }}{{I_{D} }}} \right)^{2} S_{Vfb}$$

(13)

$$S_{Vfb} = \frac{{q^{2} N_{t} kT\lambda }}{{WLC_{d}^{2} f}}$$

(14)

Figure 5

(a) Noise spectral density (S_ID/I_D²) with respect to frequency at various gate bias (V_GS) points. (b) Noise spectral density (S_ID/I_D²) and (g_m/I_D)² as functions of drain current I_D.

Here, S_Vfb denotes the flatband voltage power spectral density; kT, the thermal energy; WL, the channel area; C_d, the dielectric capacitance; f, the frequency; and N_t, the bulk/border trap density. λ denotes the tunneling attenuation distance of the dielectric, which is expressed as λ = [4π(2 m*Ф_B)^1/2/h]⁻¹, where Ф_B is the dielectric barrier height³⁷. According to the CNF model, the terms S_ID/I_D² and (g_m/I_D)² vary in similar ranges with the drain current or gate voltage. From Fig. 5b, it is evident that both S_ID/I_D² (blue spheres) and (g_m/I_D)² (red line) vary similarly over several decades under varying I_D. The S_Vfb value was calculated to be 10⁻¹⁰ V²·Hz⁻¹ from Eq. 13. Using Eq. 14, we then calculated the border trap density N_t to be around 1.3 × 10¹⁹ cm⁻³·eV⁻¹; this value is of a similar level to the values of the border trap density N_bt extracted from the distributed circuit model and well comparable to the data from literature of 10¹⁸–10²² cm⁻³ eV^−120,36,38.

Conclusion

Unlike previous studies, which focused mainly on the insulator/AlGaN interface for trap extraction, the present study attempted to investigate the AlGaN/GaN interface for this purpose. We used modified versions of conventional MOS trap extraction methods to extract the interface trap density D_it and border trap density N_bt of the Al_0.25Ga_0.75N/GaN interface. We performed the extractions by considering the Al_0.25Ga_0.75N layer to be comparable to the insulator of the MOS structure on account of the relatively high dielectric constant of the former. The D_it value extracted by the conductance method was in the range of 2.5 × 10¹² cm⁻²·eV⁻¹ to 7.1 × 10¹² cm⁻²·eV⁻¹, and the N_bt value extracted using the distributed circuit model was 1.5 × 10¹⁹ cm⁻³·eV⁻¹ with τ_o of 1 × 10⁻¹² s. The border trap density N_t extracted using the CNF model via 1/f noise measurements was 1.3 × 10¹⁹ cm⁻³·eV⁻¹ (same level as the extracted value of N_bt), which confirmed the validity and reliability of our trap extraction method.