A quantitative approach for trap analysis between Al0.25Ga0.75N and GaN in high electron mobility transistors

The characteristics of traps between the Al0.25Ga0.75N barrier and the GaN channel layer in a high-electron-mobility-transistors (HEMTs) were investigated. The interface traps at the Al0.25Ga0.75N/GaN interface as well as the border traps were experimentally analyzed because the Al0.25Ga0.75N barrier layer functions as a dielectric owing to its high dielectric constant. The interface trap density Dit and border trap density Nbt were extracted from a long-channel field-effect transistor (FET), conventionally known as a FATFET structure, via frequency-dependent capacitance–voltage (C–V) and conductance–voltage (G–V) measurements. The minimum Dit value extracted by the conventional conductance method was 2.5 × 1012 cm−2·eV−1, which agreed well with the actual transistor subthreshold swing of around 142 mV·dec−1. The border trap density Nbt was also extracted from the frequency-dependent C–V characteristics using the distributed circuit model, and the extracted value was 1.5 × 1019 cm−3·eV−1. Low-frequency (1/f) noise measurement provided a clearer picture of the trapping–detrapping phenomena in the Al0.25Ga0.75N layer. The value of the border trap density extracted using the carrier-number-fluctuation (CNF) model was 1.3 × 1019 cm−3·eV−1, which is of a similar level to the extracted value from the distributed circuit model.

www.nature.com/scientificreports/ the dielectric or the passivation layer 12,13 . However, from a device point of view, characterization of the AlGaN/ GaN interface would be more beneficial because this interface is directly related to carrier transport. In this study, we tried to include all types of AlGaN/GaN interfacial trapping analysis for a better understanding. We extracted the interface trap density (D it ) between AlGaN and GaN and the deep-level/border trap density N bt in the AlGaN barrier layer in a long-channel AlGaN/GaN HEMT fabricated on a SiC substrate. We mainly focused on the trap states inside the AlGaN layer, located at the interface and near the interface of the AlGaN/GaN, and tried to eliminate other probable interfacial trap contributing factors such as dielectric layers for passivation. We used the conventional frequency-dependent C-V and G-V characteristics to understand the interactions of the interface traps 14,15 . Along with these characteristics, we also investigated the deep-level/ border trap behavior in the accumulation region by examining split C-V characteristics, which are typically observed in the conventional Si MOS structure 16,17 . Although some researchers have discussed border/bulk trap extraction with threshold voltage shift profiling, discharging-based trap energy profile technique, etc., the frequency-dependent CV method for border trap density extraction for AlGaN/GaN heterostructure is not present [18][19][20] . We further performed low-frequency (1/f) noise measurements as they are a highly powerful tool for analyzing the defects and impurities in semiconductor devices and because they aid in the estimation of the efficiency and reliability of these devices 21 . Figure 1a illustrates the cross-sectional schematic and the transmission electron microscopy (TEM) image of the HEMT device used in this study. Epitaxial layers were grown on a semi-insulating 330 µm SiC substrate by metal-organic-chemical-vapor-deposition (MOCVD). Layers were deposited from bottom to top in the following order: an AlN nucleation layer, a 2.6 µm high-resistance GaN layer, a 150 nm GaN channel, and a 28 nm Al 0.25 Ga 0.75 N barrier layer. Hall measurements revealed the mobility (µ n_Hall ) and the sheet charge density (2DEG) to be 2200 cm 2 ·V −1 ·s −1 and 9 × 10 12 cm −2 , respectively. Mesa isolation was carried out with Cl 2 based inductivelycoupled-plasma (ICP) etching to isolate the devices. Before ohmic metal deposition, the substrate was diluted with a mixture of HCl and deionized water (1:5) for 30 s to remove any kind of formed native oxide. To facilitate ohmic contact formation, a Si/Ti/Al/Ni/Au (1/25/160/40/100 nm) alloy was deposited on source and drain area using an electron beam (e-beam) evaporator and rapid thermal annealing at 830 °C was subsequently performed in N 2 ambient for 30 s. The contact resistance (R C ) and sheet resistance (R SH ) were extracted by transmissionline-method (TLM) measurements to be 1.2 Ω·mm and 320 Ω/□ respectively. A Ti/Au (20/300 nm) padding layer was deposited using the E-beam evaporator to achieve strong probe contact. Finally, gate metal consisting of Ni/Au (20/400 nm) was also deposited using e-beam evaporator. The gate length (L g ), gate width (W g ), and source-to-drain distance (L sd ) of the fabricated devices were 14, 50, and 18 µm, respectively. All the devices had the same source-to-gate (L sg ) distance and gate-to-source distance (L gd ) of 2 µm. From the high-resolution TEM image shown in Fig. 1a, the well deposited Al 0. 25 14,22 . Typically, the interface between the dielectric and the semiconductor is analyzed for trap extraction. In our study, we applied the conductance method to our device structure. Because the Al 0.25 Ga 0.75 N barrier layer has a wide band gap (~ 4 eV) and a high dielectric constant (~ 9.4), it can act as an insulator and perform comparably to a dielectric material. The conductance method relies on the extraction of the equivalent parallel conductance (G P ) from the measured frequencydependent C-V and G-V characteristics. Figure 1b shows the equivalent circuit of a MOSFET in the depletion region, where C it , C S and R S represents the interface trap capacitance, the semiconductor capacitance, and series resistance, respectively. The interface trap capacitance can be expressed as C it = qD it (where q denotes the elemental charge). G P can be determined by the following equation:

Experimental details
Here, C ins is the insulator capacitance; ω is the angular frequency; and C c and G c are, respectively, the corrected measured capacitance and conductance corresponding to the series resistance R S .
Using the normalized (G P /ω) max value, we can determine the value of D it as follows 23 : Here, A denotes the device area. The trap response of the interface states can be determined from the Shockley-Read-Hall statistics of capture and emission 24 : Here, ΔE denotes the difference of energy between the conduction band E C and trap energy level E T . K B and T are the Boltzmann constant and temperature. σ, v th and D dos represent the cross-section of traps, the average thermal velocity, and the effective density of states, respectively. Fig. 1c was used for the extraction of border traps 16,17 . It can provide information on the border trap states inside the insulator bulk with frequency-dependent C-V measurement. This model can be represented by the following first-order differential equation:

Border trap model. The distributed circuit model shown in
This equation has a boundary condition of x = 0, Y = jωC S , while Y being the total admittance. N bt in the above equation denotes the density of border traps in the insulator layer.
Usually, the carriers in the channel region and the border traps in the insulator layer can exchange charge through tunneling 16  (1) www.nature.com/scientificreports/ Using N bt and τ o as fitting parameters, the best-fitted curve of C tot with respect to frequency can be generated for the measured capacitance which will be discussed more in the results and discussion section.
The probing distance (X p ) of a border trap with a fixed frequency (f) while, ωτ = 1, can be described as 27 www.nature.com/scientificreports/ and accumulation regions, respectively. In the depletion region, the interface traps above the Fermi level E F are mostly active; this causes the capture and emission of the carriers in the channel region. In the accumulation region, where E F penetrates the conduction band E C , the electrons on the surface are captured and emitted by the border traps via tunneling. A Keysight B1500A semiconductor device analyzer and an Agilent 4384A precision LCR meter were used for all DC measurements. 1/f measurements were performed using a setup comprising battery operated SRS SR570 low-noise current preamplifier, HP 35670A dynamic signal analyzer, and a 1 Hz filter unit.

Results and discussion
The insulator capacitance was determined by the following equation: Here, ε o is the permittivity of free space and ε ins is the relative permittivity of the Al 0.25 Ga 0.75 N layer. As it is known from the literature, the value of ε ins as calculated from ε = − 0.5x + 9.5-where x denotes the Al content of the Al x Ga 1−x N layer-for x = 25% is around 9.375 29,30 . The tensor components of AlN and GaN's {0001} relative permittivity are linearly interpolated to obtain the relation. The parallel equivalent conductance G p was calculated using Eq. 1 with correction of the measured capacitance and conductance for the series resistance. Figure 3b shows a plot of the parallel conductance G p /ω versus the angular frequency ω. D it was measured from the (G p /ω) max peak, using Eq. 2; The extracted value of D it using the conductance method was in the range of 2.5 × 10 12 cm −2 ·eV −1 to 7.1 × 10 12 cm −2 ·eV −1 which is well within the range of 10 11 -10 14 cm −2 eV −1 for S-HEMT and MOS-HEMT from literature 10,12,31 . Figure 3a shows the active D it with respect to the trap energy (ΔE), which was determined from Eq. 3. For this calculation, the frequency corresponding to (G p /ω) max was considered. At room temperature (300 K), the average thermal velocity v th and the effective density of states (D dos ) of the GaN material were considered to be 2.6 × 10 7 cm·s −1 and 1.2 × 10 18 cm −3 , respectively 31 . The value of the capture cross-section σ was assumed to be 3.4 × 10 −15 cm 2 from the literature 32 . The reliability of the extracted value of D it was determined via a theoretical calculation of the subthreshold swing (SS) using the following equation 33 : www.nature.com/scientificreports/ The value of the SS calculated from the lowest extracted D it was around 143 mV·dec −1 , whereas the value determined by the basic I-V measurement was found to be 142 mV·dec −1 (Fig. 3c). This similarity of the measured and calculated values confirms the reliability of the extracted value of D it .
We used the parameters in Table 1 to extract the border trap density N bt . For the calculation of the attenuation coefficient, the effective mass of Al 0.25 Ga 0.75 N was considered to be 0.19m o (where m o denotes the electron mass at rest) 34 . The semiconductor capacitance C S was estimated via Nextnano simulation at an accumulation gate bias of − 3.5 V, which was the primary N bt extraction voltage considered in this study. From Eq. 4, the best-fitted capacitance curves were obtained at − 3.5 V under consideration of N bt and τ o as variable fitting parameters. The best-fitted curve was obtained at N bt = 1.5 × 10 19 cm −3 ·eV −1 and τ o = 1 × 10 −12 s, as shown in Fig. 4a. Here, C M denotes the capacitances measured at various applied frequencies at − 3.5 V and C tot represents the fitted curve. The spatial distribution of N bt as a function of both the applied V GS and the probing distance into the Al 0.25 Ga 0.75 N layer from the Al 0.25 Ga 0.75 N/GaN interface is shown in Fig. 4b. The N bt values were extracted at various applied voltages at a particular applied frequency. The probing depth into the Al 0.25 Ga 0.75 N layer from the interface was calculated by Eq. 10 using different τ o values associated with the N bt values. Because the border traps exhibit more dominant characteristics at lower frequencies, we employed a low frequency of 10 kHz to extract the probing depth. With an increase in V GS , the Fermi level E F tended to penetrate to a greater depth into the conduction band E C . As a result, more electrons tended to tunnel into the deep-level traps. As all parameters except τ o were fixed, τ o showed an inverse relation with the probing depth.
1/f noise measurements were performed by varying the gate voltage V GS and fixing the drain bias V DS at 0.5 V. Figure 5a shows the normalized S ID /I D 2 (drain current noise spectral density) with respect to frequency up to 10 4 Hz under varying V GS from the linear region. It is evident that as V GS increased, and the device transitioned from weak inversion to strong inversion, noise level (S ID /I D 2 ) decreases. Plotting of the normalized (12) SS = kT q ln 10. 1 + qD it C ins  Here, S Vfb denotes the flatband voltage power spectral density; kT, the thermal energy; WL, the channel area; C d , the dielectric capacitance; f, the frequency; and N t , the bulk/border trap density. λ denotes the tunneling attenuation distance of the dielectric, which is expressed as λ = [4π(2 m*Ф B ) 1/2 /h] −1 , where Ф B is the dielectric barrier height 37 . According to the CNF model, the terms S ID /I D 2 and (g m /I D ) 2 vary in similar ranges with the drain current or gate voltage. From Fig. 5b, it is evident that both S ID /I D 2 (blue spheres) and (g m /I D ) 2 (red line) vary similarly over several decades under varying I D . The S Vfb value was calculated to be 10 −10 V 2 ·Hz −1 from Eq. 13. Using Eq. 14, we then calculated the border trap density N t to be around 1.3 × 10 19 cm −3 ·eV −1 ; this value is of a similar level to the values of the border trap density N bt extracted from the distributed circuit model and well comparable to the data from literature of 10 18 -10 22 cm −3 eV −120,36,38 .

Conclusion
Unlike previous studies, which focused mainly on the insulator/AlGaN interface for trap extraction, the present study attempted to investigate the AlGaN/GaN interface for this purpose. We used modified versions of conventional MOS trap extraction methods to extract the interface trap density D it and border trap density N bt of the Al 0.25 Ga 0.75 N/GaN interface. We performed the extractions by considering the Al 0.25 Ga 0.75 N layer to be comparable to the insulator of the MOS structure on account of the relatively high dielectric constant of the former. The D it value extracted by the conductance method was in the range of 2.5 × 10 12 cm −2 ·eV −1 to 7.1 × 10 12 cm −2 ·eV −1 , and the N bt value extracted using the distributed circuit model was 1.5 × 10 19 cm −3 ·eV −1 with τ o of 1 × 10 −12 s. The border trap density N t extracted using the CNF model via 1/f noise measurements was 1.3 × 10 19 cm −3 ·eV −1 (same level as the extracted value of N bt ), which confirmed the validity and reliability of our trap extraction method.

Data availability
The datasets generated during and/or analysed during the current study are available from the corresponding author on reasonable request.