Abstract
In the field of semiconductors, three-dimensional (3D) integration not only enables packaging of more devices per unit area, referred to as ‘More Moore’1 but also introduces multifunctionalities for ‘More than Moore’2 technologies. Although silicon-based 3D integrated circuits are commercially available3,4,5, there is limited effort on 3D integration of emerging nanomaterials6,7 such as two-dimensional (2D) materials despite their unique functionalities7,8,9,10. Here we demonstrate (1) wafer-scale and monolithic two-tier 3D integration based on MoS2 with more than 10,000 field-effect transistors (FETs) in each tier; (2) three-tier 3D integration based on both MoS2 and WSe2 with about 500 FETs in each tier; and (3) two-tier 3D integration based on 200 scaled MoS2 FETs (channel length, LCH = 45 nm) in each tier. We also realize a 3D circuit and demonstrate multifunctional capabilities, including sensing and storage. We believe that our demonstrations will serve as the foundation for more sophisticated, highly dense and functionally divergent integrated circuits with a larger number of tiers integrated monolithically in the third dimension.
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Data availability
Data on samples produced in the 2DCC-MIP facility are available at https://doi.org/10.26207/khwb-rr73. These include growth recipes and characterization data. Additional datasets generated and/or analysed during this study are available from the corresponding authors on reasonable request.
Code availability
The codes used for plotting the data are available from the corresponding authors.
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Acknowledgements
We thank M. Labella and T. F. Schranghamer for developing the scaled lift-off process, and all staff of the Nanofabrication Lab at the Pennsylvania State University for their assistance. The MOCVD samples were grown in the 2D Crystal Consortium Materials Innovation Platform (2DCC-MIP) facility at the Pennsylvania State University, which is supported by the National Science Foundation under cooperative agreement DMR-2039351. This work was supported by the Army Research Office (ARO) through Contract Number W911NF1810268 and National Science Foundation (NSF) through CAREER Award under Grant Number ECCS-2042154. T.V.M. and J.M.R. acknowledge the support of the U.S. Air Force Office of Scientific Research and Clarkson Aerospace Corp. under Award no. FA9550-21-0460.
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Contributions
S.D., R.P. and D.J. conceived the idea and designed the experiments. D.J., R.P., N.U.S. and M.U.K.S. fabricated all the 3D chips. S.D., D.J., R.P., N.U.S., M.U.K.S. and A.P. performed the experiments, analysed the data, discussed the results and agreed on their implications. N.T., C.C. and T.V.M. grew and characterized the 2D materials under the supervision of J.M.R. S.K. performed the 2-inch MoS2 transfer and characterized the 2D materials under the supervision of J.M.R. Y.Y. and Y.H. performed the FIB and TEM for the 3D chip. All authors contributed to the preparation of the paper.
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Extended data figures and tables
Extended Data Fig. 1 Device Schematic of the 2D FET.
Schematic of the 2D FET device consisting of a 9 nm Al2O3/3 nm HfO2/3 nm Al2O3 floating gate-like stack, the 2D channel (either MoS2 or WSe2), and the source/drain contacts, consisting of 20 nm Ni/10 nm Au for MoS2, or 20 nm Pd/10 nm Au for WSe2.
Extended Data Fig. 2 Fabrication flow for 3D Integration of 2D FETs.
a) Fabrication flow to realize 2 tier and 3 tier 3D integrated chips based on 2D FETs. Note that any nonconductive carrier substrate can be used to realize a 3D integrated chip. b) Table showing the number of unique fabrication steps required to realize each tier.
Extended Data Fig. 3 2-tier and 3-tier integrated 3D chips based on 2D FETs.
a) Optical image of a 2-tier chip based on MoS2 FETs. Each cell within the array contains 4 FETs, with two devices in each tier that are stacked vertically. b) Optical image of a 3-tier chip based on MoS2 FETs. Each cell contains 5 FETs with two devices in tier 1, two devices in tier 2, and one device in tier 3, with three devices stacked vertically. Note that the limitation in integrating more devices in each cell is due to geometric constraints in contact pad placement for subsequent measurements.
Extended Data Fig. 4 Electrical characteristics of the 2-tier wafer scale MoS2 devices.
Transfer characteristics and corresponding histograms of SS, ION, and VTH from devices in (a) die 1, (b) die 2, (c) die 3, (d) die 4, (e) die 5 of tier 1, and those in (f) die 1, (g) die 2, (h) die 3, (i) die 4, (j) die 5 of tier 2 is given.
Extended Data Fig. 5 TEM and EDS analysis of the vertically stacked 3-tier MoS2.
a) Zoomed in HAADF-STEM image of each tier shows the thin MoS2 layer between gate dielectric and contact pads. b) Corresponding EDS elemental mapping shows the presence of Mo and S in each tier.
Extended Data Fig. 6 Electrical characteristics of 3-Tier stack of MoS2 and WSe2 FETs.
Transfer characteristics of a) 500 tier 1, b) 500 tier 2, and c) 250 MoS2 FETs with \({L}_{{\rm{CH}}}\) = 300 nm. Transfer characteristics of d) 300 tier 1, e) 300 tier 2, and f) 200 tier 3 MoS2 FETs with \({L}_{{\rm{CH}}}\) = 1000 nm. Transfer characteristics of g) 500 tier 1, h) 500 tier 2, and i) 250 WSe2 FETs with \({L}_{{\rm{CH}}}\) = 300 nm and j) 300 tier 1, k) 300 tier 2, and l) 200 tier 3 WSe2 FETs with \({L}_{{\rm{CH}}}\) = 1000 nm. Note that the WSe2 FETs demonstrate ambipolar transport, with dominant p-type conduction, which is complementary to the n-type conduction observed in MoS2 FETs. 20 nm Ni/10 nm Au stack was used as source/drain contact electrodes for MoS2 FETs and 20 nm Pd/10 nm Au stack was used as source/drain contact electrodes for WSe2 FETs. All transfer characteristics were measured using \({V}_{{\rm{DS}}}\) = 1 V. (*Note that the limitation in the number of devices in tier 3 is due to less contact pad space available, after the fabrication of both tier 1 and tier 2.).
Extended Data Fig. 7 Extracted device parameters for the 3-tier 3D integrated MoS2 and WSe2 FETs.
Distribution of \(SS\), \({I}_{{\rm{ON}}}\), and \({V}_{{\rm{TH}}}\) of 200 MoS2 FETs for a) tier 1, b) tier 2, and c) tier 3, corresponding to the transfer characteristics given in Fig. 3d-f. Distribution of \(SS\), \({I}_{{\rm{ON}}}\), and \({V}_{{\rm{TH}}}\) of 200 WSe2 FETs for d) tier 1, e) tier 2, and f) tier 3 corresponding to the transfer characteristics given in Fig. 3g-i.
Extended Data Fig. 8 Impact of 3D topography on 2D FETs.
AFM scan of a 2-tier MoS2 chip. a) without and b) with an underlying MoS2 device. AFM line scan across the devices show c) 30 nm step height between the channel and the contact for 2nd tier devices and d) 60 nm step height between the channel to the contact for the 3rd tier devices. This is also highlighted in the schematics showing the surface topography prior to the fabrication of e) 2-tier and f) 3-tier devices. Clearly, with increasing number of tiers, the surface topography becomes increasingly complex, which can lead to strain and other mechanical challenges for the transferred 2D films.
Extended Data Fig. 9 Multifunctional 2D FETs.
a) Schematic of a 2-tier MoS2 chip with a via connection between the two tiers, enabling the realization of a 3D integrated inverter. b) Characteristics of the inverter consisting of tier 1 and tier 2 MoS2 FETs. The memory capabilities exhibited by the MoS2 FETs are shown with c) transfer characteristics for ten devices that are programmed in a low conduction state (LCS), and a high conduction state (HCS), d) retention of HCS and LCS for 300 s, and e) endurance taken for 1000 read/write cycles for a \({V}_{{\rm{Program}}}\)= −5 V, \({V}_{{\rm{Program}}}\)= 4 V, and a \({V}_{{\rm{Read}}}\)= −0.5 V for a pulse time of 1 ms. Finally, the photo-sensing capabilities of MoS2 FETs are shown with f) transfer characteristics from 50 devices measured under dark and illuminated conditions (white light, \({P}_{{\rm{IN}}}\) = 15 Wm−2). The extracted g) responsivity (\(R\)) and h) specific detectivity (\({D}^{* }\)).
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Jayachandran, D., Pendurthi, R., Sadaf, M.U.K. et al. Three-dimensional integration of two-dimensional field-effect transistors. Nature 625, 276–281 (2024). https://doi.org/10.1038/s41586-023-06860-5
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DOI: https://doi.org/10.1038/s41586-023-06860-5
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