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Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors


With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage1. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO2 (ref. 2), which remains the material of choice to date. Here we report HfO2–ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric–antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal–oxide–semiconductor capacitors is equivalent to an effective SiO2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-dielectric-constant gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current3. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO2–ZrO2 multilayers, stabilized with competing ferroelectric–antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO2-based high-dielectric-constant materials.

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Fig. 1: Atomic-scale design of negative capacitance in ultrathin HfO2–ZrO2.
Fig. 2: Enhanced capacitance in ultrathin HfO2–ZrO2 mixed-ferroic heterostructures.
Fig. 3: Device performance benefits from using ultrathin mixed-ferroic HfO2–ZrO2 gate stacks.

Data availability

The experimental data contained in the manuscript are available for download at


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This research was supported in part by the Berkeley Center for Negative Capacitance Transistors (BCNCT), the DARPA Technologies for Mixed-mode Ultra Scaled Integrated Circuits (T-MUSIC) programme, the University of California Multicampus Research Programs and Initiatives (UC MRPI) project and the US Department of Energy, Office of Science, Office of Basic Energy Sciences, Materials Sciences and Engineering Division under contract no. DE-AC02-05-CH11231 (Microelectronics Co-Design programme) for the development of materials for low-power microelectronics. This research used resources of the Advanced Photon Source, a US Department of Energy (DOE) Office of Science User Facility at Argonne National Laboratory and is based on research supported by the US DOE Office of Science, Basic Energy Sciences, under contract no. DE-AC02-06CH11357. V.A.S. and J.W.F. were supported by the US Department of Energy, Office of Science, Basic Energy Sciences, under award number DE-SC-0012375. Use of the Stanford Synchrotron Radiation Light source, SLAC National Accelerator Laboratory, is supported by the US Department of Energy, Office of Science, Office of Basic Energy Sciences under contract no. DE-AC02-76SF00515. This research used resources of the Advanced Light Source, which is a DOE Office of Science User Facility under contract no. DE-AC02-05CH11231. Electron microscopy was performed at the Molecular Foundry, LBNL, supported by the Office of Science, Office of Basic Energy Sciences, US Department of Energy (DE-AC02-05CH11231). Device fabrication was performed at the Marvell Nanofabrication Laboratory at UC Berkeley. This material is based upon work supported by the Secretary of Defense for Research and Engineering under Air Force contract no. FA8702-15-D-0001. Any opinions, findings, conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the Secretary of Defense for Research and Engineering.

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Authors and Affiliations



S.S.C. and S.S. designed the research. S.S.C. performed design, synthesis, and optimization of the superlattice oxide heterostructure and its ferroic characterization. N.S. and C.-H.H. performed capacitor fabrication. C.-H.H. helped optimize annealing treatments. N.S. and S.S.C. performed capacitor measurements and analysis. L.-C.W. fabricated the transistors and performed d.c. characterization. D.W.K. and J.B. developed the initial processes for transistor fabrication. Y.-H.L. performed simulations including EOT estimation, series resistance determination and mobility and transconductance analysis. M.S.J., J.G. and W.L. contributed to radio-frequency electrical measurements and analysis. N.S. performed MOSCAP stress measurements. W.C. and N.S. performed MOSFET reliability measurements under the guidance of S.D., S.M. and S.S. M.M., R.R., C.S., D.P., G.P., M.C. and B.T. contributed to capacitor fabrication and characterization at MIT LL. S.-L.H. performed TEM. S.S.C. and S.-L.H. performed TEM analysis. Y.R. performed second-harmonic generation. S.K.V. performed X-ray photoelectron spectroscopy. S.S.C. and C.-H.H. performed synchrotron soft X-ray spectroscopy at ALS. S.S.C., V.A.S. and J.W.F. performed synchrotron X-ray spectroscopy at APS. S.S.C., C.-H.H., V.A.S. and Z.Z. performed synchrotron in-plane diffraction at APS. S.S.C. and N.S. performed synchrotron X-ray reflectivity and 2D diffraction at SSRL. S.S.C. and S.S. co-wrote the original manuscript; S.S.C., N.S. and S.S. revised the manuscript. S.S. supervised the research. All authors contributed to discussions and manuscript preparations.

Corresponding authors

Correspondence to Suraj S. Cheema or Sayeef Salahuddin.

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Nature thanks Takashi Ando, Thomas Mikolajick and Burc Misirlioglu for their contribution to the peer review of this work.

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Extended data figures and tables

Extended Data Fig. 1 Atomic-scale multilayer structure.

a, Schematic of the HfO2–ZrO2 multilayer structure on SiO2-buffered Si. b, Synchrotron X-ray reflectivity (XRR) of thicker HZH heterostructures (left) repeated with the same periodicity as the thinner trilayer structure; XRR fitting (right) demonstrates the presence of well separated HfO2–ZrO2 layers, that is, not a solid solution, for three different multilayer repeats of fixed periodicity, all approximately following the expected 4 Å–12 Å–4 Å HZH structure. c, Layer-resolved electron energy loss spectroscopy (EELS) of the 2-nm HZH trilayer, demonstrating clear separation of HfO2 and ZrO2 layers. The exact layer thicknesses are extracted from XRR, which spans a wider sample footprint, rather than the local EELS measurement in which the apparent width increase can be due to beam spreading and local thickness variation. d, Angle-resolved X-ray photoelectric spectroscopy (XPS) of the 2-nm HZH trilayer (left) and the extracted atomic composition (right). The presence of increasing Zr content as the grazing angle increases is expected from the multilayer structure in which Zr content increases after the surface Hf-rich layer. Therefore XRR, EELS and XPS data all indicate the presence of a multilayer structure in which the HfO2 layer is directly on the SiO2 layer.

Extended Data Fig. 2 Ferroic phase insights from structural characterization.

a, Left, in-plane synchrotron grazing-incidence diffraction (IP-GiD) of a bare 2-nm HZH trilayer indexed to the tetragonal P42/nmc and orthorhombic Pca21 phases. Right, magnification of the spectrum about the orthorhombic (111)o and tetragonal (101)t reflections, confirming the co-existing structural polymorphs in the 2-nm film. These two peaks were differentiated via self-consistent indexing of the entire spectrum, in which interplanar lattice spacings—determined from the {200}o family of reflections—closely match the d spacings for all other reflections—(111)o, (120)o, (211)o, (202)o—determined by Bragg’s law (Methods). b, Two-dimensional reciprocal space map of the bare 2-nm HZH trilayer, indexed by integrating the diffraction spectrum. The lack of fully polycrystalline rings illustrates that the 2-nm HZH trilayer is highly oriented, consistent with TEM imaging. c, Synchrotron spectroscopy (XAS) of the bare 2-nm HZH trilayer at the Hf M3 edge (left) and Zr L3,2 edge (centre); right, the presence of linear dichroism (orbital polarization) provides further evidence of symmetry-breaking in these oriented thin films. d, Second harmonic generation (SHG) mapped across the bare 2-nm HZH trilayer; the presence of SHG intensity confirms broken inversion symmetry in these ultrathin ferroic films. e, f, Additional cross-sectional TEM providing complementary evidence of the tetragonal P42/nmc (e) and orthorhombic Pca21 (f) phases, in which the extracted (101)t lattice spacing (~2.95 Å) and (111)o lattice spacing (~3.08 Å) extracted from IP-GiD are consistent with the average lattice spacings extracted from the periodicity of the TEM-imaged planes. The white scale bars in all the TEM images represent 1 nm.

Extended Data Fig. 3 Ferroic phase insights: proximity to temperature-dependent phase transition.

a, Schematic of temperature-dependent AFE–FE phase evolution in fluorite-structure oxides. At lower temperatures, the higher symmetry tetragonal phase is expected to transition to the lower symmetry orthorhombic phase. b, Schematic crystal field splitting diagram for fluorite-structure polymorphs; the symmetry-induced e-splitting (rhombic distortion, ∆R), besides the typical t2-e splitting (tetrahedral distortion, ∆T) present in all fluorite-structure phases, provides a spectroscopic signature for the polar O phase (Methods). c, Temperature-dependent XAS at the oxygen K edge for a 2-nm HZH bare film demonstrating clearer spectroscopic signatures of the FE O phase emerge slightly below room temperature.d, Simulated oxygen K-edge XAS spectra (Materials Project) for the respective O and T phases. XAS provides spectroscopic signatures to distinguish between the O and T phases (difficult to resolve from GI-XRD). e, Prototypical CV behaviour for mixed AFE–FE (shoulder-like features in addition to the characteristic butterfly-like shape) and FE films (just butterfly-like) in MIM capacitor structures. f, Temperature-dependent CV for thicker HZH multilayers of the same periodicity (in MIM capacitor structure) demonstrating an evolution from mixed-ferroic to FE-like hysteresis upon cooling slightly below room temperature. Thinner HZH multilayers films suffer from leakage limitations, preventing such hysteretic CV measurements. The thicker HZH multilayers of the same periodicity—annealed at the same low-temperature condition to maintain the multilayer structure—demonstrate a similar mixed ferroic to FE phase transition slightly below room temperature as the thinner 2-nm multilayer (c).

Extended Data Fig. 4 Solid solutions versus superlattice structure: role of ALD period and Zr content.

a, Schematic of HZH multilayer and Zr-rich Hf:ZrO2 solid-solution films. With shorter ALD periods, the mixed FE–AFE multilayer structure transitions towards a Hf:ZrO2 solid solution with AFE-like behaviour. In the solid-solution state, the loss of the mixed ferroic order yields diminished capacitance, owing to the lack of mixed-ferroic-induced capacitance enhancement (Fig. 1a). b, MOS accumulation CV of the HZH trilayer (60% Zr) compared to solid-solution films of the same thickness (2 nm) and composition (60% Zr), as well as solid-solution films of the same thickness and higher Zr composition (67%–100% Zr). c, MIM CV hysteresis loops of the HZH superlattice (60% Zr) compared to solid-solution films of the same thickness (6 nm) and composition (60% Zr), as well as solid-solution films of the same thickness and higher Zr composition (67%–100% Zr). Hf:ZrO2 solid-solution films with higher Zr content (60%–75%) are around the range attributed to the ‘MPB’ in thicker Hf:ZrO2 alloys35,55,90,91,92,93. These results indicate that the capacitance enhancement in multilayer films is not simply driven by Zr content32,38,57,63, but instead the atomic-scale stacking, as the solid-solution films with subatomic superlattice period do not demonstrate the same mixed-ferroic behaviour and enhanced capacitance as the superlattices.

Extended Data Fig. 5 Solid solutions versus superlattice structure: role of annealing temperature.

a, Schematic of HfO2–ZrO2 multilayer and Hf:ZrO2 solid-solution films. Under a high-temperature anneal, the multilayer structure transitions towards a Hf:ZrO2 solid-solution-like structure demonstrating more FE-like behaviour. The solid-solution state yields diminished capacitance owing to the lack of both the higher-permittivity AFE phase and the mixed-ferroic-induced capacitance enhancement (Fig. 1a). b, Comparison of MOS capacitor accumulation CV characteristics in HZH multilayers, where the superstructure was repeated (left) one, (centre) two, or (right) three times, under both low- and high-temperature anneals. c, Comparison of mixed-ferroic behaviour in low-temperature treated MIM HZH multilayers versus FE behaviour in the same multilayers annealed at high temperatures, where the superstructure was repeated (left) three, (centre) four, or (right) five times. In all instances, the high-temperature anneal (>500 °C) results in diminished accumulation capacitance compared to the low-temperature anneals, as the multilayered mixed-ferroic films presumably transition to more FE-like solid-solution alloys.

Extended Data Fig. 6 SiO2 interlayer thickness.

a, Wide field-of-view (FOV) cross-sectional TEM images of the HZH multilayer structure and its corresponding intensity line scan (bottom right) averaged across the entire top cross-sectional image FOV (~150 nm, teal-coloured box). Note the vertical teal-coloured lines in the intensity line scan correspond to the inner teal-coloured box in the wide-FOV image, which delineate the SiO2 interlayer boundaries. The bottom cross-sectional TEM image highlights the thin SiO2 interlayer (white region) without obfuscation by the teal-coloured box. A physical SiO2 thickness of 8.6 Å is extracted from analysis of the averaged intensity line scan of the wide FOV TEM (Methods). b, d, CV measurements of HfO2 (b) and Al2O3 (d) thickness series in MOS capacitor structures (left), extracted inverse capacitance versus thickness at different charge values (centre), and extracted QV relation Si charge layer and SiO2 interlayer (SiL; right), which fits to TCAD simulations for 8.0 Å SiO2. The SiL QV relation was found by integrating the extracted capacitance equivalent thickness of SiL versus charge (right, inset). This electrical interlayer thickness (8.0 Å) is slightly less than the physical thickness determined by TEM (8.6 Å). As a sanity check, the extracted permittivity from this methodology for HfO2 and Al2O3 corresponds to 19 and 9, respectively, as is expected (Methods section ‘Permittivity extraction’). c, e, QV curves for HfO2 (c) and Al2O3 (e) thickness series obtained from integrating MOS CV measurements (left), extracted voltage versus thickness at various charge values (centre), and extracted QV relation of SiL (right). The SiL QV relation is consistent with the QV relation extracted from the CV data (inset). f, Consistency in the SiL QV relation extracted from the CV data from both the HfO2 and Al2O3 thickness series, which both fit to 8.0 Å SiO2 interlayer thickness.

Extended Data Fig. 7 Capacitance and charge enhancement.

a, MOS schematic of the 20 Å HZH mixed-ferroic trilayer sample on lightly doped Si (1015 cm−3) considered for the following CV and pulsed IV measurements. b, Accumulation CV curves for 2-nm HZH grown on sub-nm SiO2 fit to equivalent oxide thickness (EOT) simulations (Methods). Inset, externally verified MOS accumulation CV of the same trilayer stack (Methods), demonstrating 6.5 Å EOT. The 2-nm trilayer on top of SiO2 demonstrates lower EOT than the thickness of SiO2 interlayer alone, carefully extracted via physical (8.5 Å) and electrical (8.0 Å) methodologies (Extended Data Fig. 6), providing evidence of capacitance enhancement. c, The applied voltage pulse (top), measured current response (centre), and integrated charge (bottom) as a function of time for 2-nm HZH in MOS capacitors. d, The maximum charge Qmax, the residual charge Qres, and their difference, Qrev, derived from the charge versus time curve for each of the voltage pulses (Methods). e, The reversible charge of the MOS layer (top) compared against the extracted charge of the Si charge layer plus SiO2 interlayer (SiL) derived electrically (Extended Data Fig. 6f). The charge boost (bottom) present in the total MOS structure (SiL plus HZH capacitors) compared to just the SiL is a signature of negative capacitance26,69. f, The polarization–electric field (PEF) relationship for just the 2-nm HZH layer, extracted from the charge–voltage relationship in e. Note that the presence of a negative slope regime in the extracted PEF relation corresponds to negative capacitance stabilization26,69. g, Scatter plot of reported FE–dielectric systems demonstrating capacitance or charge enhancement at the capacitor-level, via CV or pulsed IV measurements, respectively. The plot considers fluorite-structure bilayers26,69 (red), perovskite-structure bilayers29,94 (blue, BL), and perovskite-structure superlattices30,31,47,48 (blue, SL). This work marks, to our knowledge, the thinnest demonstration of negative capacitance.

Extended Data Fig. 8 Mobility and reliability.

a, Intrinsic Cgg versus Vgs − Vfb for ~20 Å HZH and HfO2 gate stacks, which fit to 7.5 Å and 9.5 Å, respectively, extracted from SOI transistors. b, Id versus Vgs − VT at Vd = 50 mV for transistors implementing HZH and HfO2 gate stacks. c, EOT and mobility (at 5 × 1012 cm−2) for HZH and HfO2, demonstrating no mobility degradation. d, Normalized mobility versus EOT for transistors integrating the 2-nm HZH mixed-ferroic gate stack (blue) versus a 2-nm HfO2 standard high-κ dielectric gate stack (black) of higher EOT, demonstrating no mobility degradation. These results are also benchmarked against reported HKMG literature3 implementing interlayer-scavenged 2-nm HfO2 (red). Inset, SiO2 interlayer thickness versus EOT for 6.5 Å EOT HZH stack against notable HKMG literature employ interlayer scavenging3. This scatter plot highlights the underlying reason for the improved leakage-EOT and mobility-EOT behaviour in the ultrathin HZH gate stacks: achieving low EOT without reducing the SiO2 interlayer thickness. e, Measure–stress–measure scheme used in PBTI reliability measurements. f, g, ΔVT versus stress time for long-channel bulk transistors integrating HZH (f) and HfO2 (g) at varying stress conditions (up to 9 MV cm−1), measured at 85 °C. The extracted time exponent, n, is similar to reported high-κ HfO2 stacks67, which is expected considering the similar interfacial (IL) oxide and IL-high-κ interface46; both stacks with different EOT have HfO2 sitting on the same SiO2 IL (Extended Data Fig. 1). h, d.c. lifetime (stress time needed to induce a 50 mV ΔVT shift) versus electric field for HZH and HfO2, demonstrating similar rates of degradation. i, j, Evolution of MOSCAP accumulation CV curves as a function of stress time at a stress of Vfb − 1 V for HZH (i) and HfO2 (j).

Extended Data Fig. 9 Radio frequency device characterization.

a, De-embedding procedure for extracting corrected admittance parameters (Ycorr) by decoupling parasitic shunt capacitance and series resistance and inductance by measuring scattering parameters for the device under test (DUT) as well as open and short structures. More details can be found in Methods. b, Small-signal model for transistor used to extract transconductance (gm) and total gate capacitance (Cgg = Cgs + Cgd). c, De-embedded (2πf)−1Re(Y21) points extrapolated to the zero frequency limit (dotted lines) to extract the radio frequency gm. All data shown were extracted from bulk transistors (LG = 1 μm) integrating the 2-nm HZH ferroic gate stack.

Extended Data Fig. 10 Transconductance extraction.

a, Threshold voltage extraction by linear extrapolation for various channel lengths. All channel lengths give nearly constant VT (~0.42 V), satisfying the assumption for the line resistance method. b, Source/drain series resistance extracted using the 1/Vov method (Methods). By performing a linear interpolation of the total resistance for Vov = 0.5–0.6 V, the extracted series resistance is ~500 Ω μm. c, Source/drain series resistance extracted using the line resistance method (Methods). The trend is considered down to LG = 90 nm, which intersects at ~500–600 Ω μm—consistent with the 1/Vov method—with an LG offset of ~50 nm. d, e, Measured (left) and extracted (right) transconductance (d) and output conductance (e) versus Vg for Vds = 0.9–1.1 V, assuming Rs = Rd = 250 Ω μm for LG = 90 nm. The de-embedding of intrinsic gm,i and gds,i from extrinsic gm and gds is described in Methods. All data shown were measured on SOI short-channel transistors integrating the 2-nm HZH ferroic gate stack.

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Cheema, S.S., Shanker, N., Wang, LC. et al. Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors. Nature 604, 65–71 (2022).

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