Integration of paper in electronics has sparked great interest due to the unique properties of paper despite fabrication challenges. The key features of paper are its recyclability, biodegradability, high porosity, importance for bio-chemical sensor applications1,2,3 and low price (0.13 €/dm2, Powercoat®HD) compared to low-cost polymer alternatives such as polyethylene naphthalate (PEN, 2.58 €/dm2, Goodfellow) and polyethylene terephthalate (PET, 1.14 €/dm2, Goodfellow). However, fabrication challenges arise as a result of the high porosity and surface roughness. In addition, the material cannot be exposed to temperatures higher than ~150 °C.1 These limitations significantly impact the performance of electronics employing this substrate type. To avoid these limitations there have been reports of silicon electronics fabricated separately and transferred onto a paper substrate by pick & place methods.4 Although this approach provides the best electronic performance, it falls short on economical advantages. For electronics directly fabricated on top of the substrate, although vacuum-based deposition on paper has been reported,5,6 printing of liquid inks is the most economically desirable as it can be scaled up to roll-to-roll processes and has an additive patterning nature.7

Typical semiconducting ink materials, such as organic and metal-oxide semiconductors, lack in electronic performance compared to polycrystalline silicon (poly-Si).8,9 Their typical field-effect mobilities are ~1 and ~10 cm2/V s for organic and metal-oxide transistors, respectively. Although advances have been made in recent years, the device reliability is low due to their sensitivity to oxygen and moisture for organic,10 and to light for metal-oxide devices.11 Finally, these materials do not have balanced electron and hole mobilities, which prevents their implementation in complementary MOS (CMOS) circuits, and therefore makes them energy inefficient. Poly-Si on the other hand exhibits at least an order of magnitude higher mobilities (~100 cm2/V s), is stable, and has both strong electron and hole devices enabling high-speed low-power applications.

Silicon inks were first reported in 200612 and employed at a relatively high annealing temperature (>350 °C), which obstructed their usage on low-cost flexible substrates, that typically have low-thermal budgets (<120–200 °C).13 In 2015 an alternative process was reported which, synthesized poly-Si from the silicon ink by using an excimer laser.14 Due to the short laser pulse duration (several nanoseconds) and high material absorption, the treatment is limited to the top several tens of nanometers of the silicon ink, avoiding significant damage to underlying substrates. Fabrication of transistors on top of paper remained challenging15 as a result of the additional complexity when employing the substrate, such as avoiding high temperatures, wet chemicals other than the silicon ink, and additive patterning. In this work, we have successfully fabricated thin-film transistors (TFTs) directly on top of a paper substrate. We show a significant improvement in NMOS TFT by employing a blanket oxide etching prior to ion implantation, which limited the sample heating. In addition, we highlight solutions to three main challenges in the fabrication process: silicon ink coating, additive Si patterning, and metallic contact formation.


The type of paper used in this work has a limited RMS roughness of less than 20 nm due to a protective coating on top of the substrate. Cyclopentasilane (CPS) was used as the liquid silicon precursor. This liquid was blade coated on the paper surface while being exposed to UV light, which gradually increases the viscosity of the ink through molecular ring-open polymerization.16 After a stable film is formed, the film is solidified by a high-intensity UV light treatment for several seconds. This method was employed because the liquid has a poor wettability towards the substrate surface. The liquid must therefore be solidified before the film ruptures as a result of surface energy minimization. The rupture growth time is described by Eq. (1).17

$${\tau _{{\rm{max}}}} = \frac{{48{\pi ^2}{\gamma _{{\rm{LA}}}}\eta {L^5}}}{{{{\left| {{A_{{\rm{ALS}}}}} \right|}^2}}}$$

where τ max is the maximum rupture growth time, γ LA the surface free energy of the liquid–air boundary, η the viscosity of the liquid, L the thickness of the film, and A ALS the Hamaker constant. The thickness of the liquid and its viscosity are two variables that are controlled. Although the thickness of the liquid has a strong impact in increasing the rupture growth time, there is a limitation to the amount of liquid to be used, since stresses in the film can cause it to crack as a result of hydrogen and silane radical effusion in the solidification process.18 The viscosity is manipulated by photopolymerization of the CPS during coating. As soon as the rupture growth time reaches several seconds, a more intense UV light source can be employed to swiftly solidify the existing film. This process is illustrated in Fig. 1a.

Fig. 1
figure 1

Coating and crystallization of Si ink. a Diagram of the cyclopentasilane coating process on paper. Through continuous blade coating during UV polymerization, the liquid rupture time increases, resulting in an increasingly stable film. By using a high-intensity UV freeze, the film remains uniformly coated and is solidified. b Diagram of local crystallization of the polycrystalline silicon channel through a shadow mask, resulting in an additive patterning process. Red line in the microscope image inset indicates a size of 50 μm. c Raman spectroscopy measurement results of different laser crystallization recipes indicating numbers of pulses from 1 to 100 at laser fluences of 40 (left) and 50 (right) mJ/cm2. Crystallization observed by the increasing Raman signal at 520 cm−1. (Panel c reproduced with permission from ref. 15)

For low-cost fabrication and also due to the liquid absorptive nature of paper, additive formation of poly-Si TFT patterns is desired. Polysilane can be crystallized in channel patterns by excimer-laser annealing through a shadow mask as shown in Fig. 1b. When left in open air, unexposed polysilane oxidizes into the insulating SiO2 and electrically isolates the poly-Si channels. This method has been demonstrated by Okamoto et al.19 for vacuum-based polysilane on a rigid substrate. Here we have applied the technique on solution-based polysilane on top of a paper substrate. Crystallization was confirmed by Raman spectroscopy as shown in Fig. 1c. Multiple laser pulses at a fluence of 50 mJ/cm2 successfully crystallized the film. The color of the film changed from transparent to colorful, as a result of the material bandgap narrowing from 6.5 to ~2 eV.20 Higher fluences would also lead to crystallization, although the film roughness will significantly increase due to hydrogen and silane radical outgassing and ablation.14

In order to imitate an additive metallic contact fabrication process, such as that used for printing, the desired Al shapes were directly formed by evaporation through a shadow mask, thereby avoiding the need to remove material in undesired locations. The mask was attached to the sample by an adhesive that has a melting temperature of ~80–100 °C. The adhesive was locally heated with a soldering iron around the edge of a carrier wafer in order to prevent the heat from reaching the paper. For the source and drain electrodes, prior to metal contact evaporation, oxide is removed by plasma etching through the same mask.

The full TFT fabrication process comprises eight main steps: CPS/polysilane coating, local excimer laser crystallization, low-temperature oxide deposition, shadow-mask gate evaporation, self-aligned ion implantation, laser dopant activation, shadow-mask oxide etching, and contact evaporation. All process steps were conducted below a maximum process temperature of ~100 °C. To limit the implantation energy of the n-type device, oxide was blanket stripped prior to implantation. A schematic of this process is shown in Fig. 2a. For a detailed description of the process, please refer to the “Methods” section. The TFT cross-section schematic and a microscope image are presented in Fig. 2b. An image of the final result is shown in Fig. 2c.

Fig. 2
figure 2

Full liquid-Si-based TFT on paper fabrication process and results. a Diagram of the fabrication process of solution-based poly-Si TFTs on a paper substrate, starting with coating of CPS with UV light, excimer laser crystallization of the poly-Si channel, low-temperature oxide deposition, shadow mask gate evaporation, self-aligned ion-implantation, excimer laser dopant activation, shadow mask oxide etching, and finally shadow mask contact evaporation. b Diagram of the TFT cross-section with a microscope image of the fabricated TFT, red line indicating a size of 50 μm. c Optical image of the final sample of electronics on a paper substrate


Transfer and output characteristics of two of the best performing P-type MOS transistor (PMOS) and N-type MOS transistor (NMOS) TFTs are shown in Fig. 3. With respect to the charge carrier mobility, the NMOS (2.0 cm2/V s) performed had a lower value than the PMOS (6.2 cm2/V s). This is attributed to the implantation damage by the heavier phosphorus ions that had not been effectively restored by the subsequent laser annealing step. According to calculations, the swing of the PMOS device surpasses the theoretical limit. We believe that the physics behind such a low swing is impact ionization-induced floating body effect, which imposes such an abrupt increase in drain current.21 For a thorough understanding a further investigation in this behavior is necessary. A high leakage current of 10−9 A is observed for the PMOS as a result of defects in the oxide from the sample heating by ion implantation. Since for the NMOS, the oxide layer was removed prior to implantation, lower energies could be used. As a result, heat production from implantation was limited, which minimized paper expansion, and the gate oxide of the NMOS stayed intact. Therefore, the NMOS performed significantly better in terms of leakage. Threshold voltages of approximately −7 and 8 V for the PMOS and NMOS devices, respectively, were observed. Limited I on/I off ratios of 103 were obtained as a result of charge carrier scattering from the rough channels due to laser ablation and outgassing. The output characteristics of both the devices show low contact resistances, and a parasitic resistance for device operation in the saturation regime. A summary of the device performance is shown in Table 1.

Fig. 3
figure 3

Electric measurement results of liquid-Si-based TFTs produced on paper. a Transfer properties of PMOS TFT at a drain voltage of −5 V, showing both the drain current (blue), as well as the leakage current (orange). b Transfer properties of the NMOS TFT with a drain voltage of 5 V. c Output properties of the PMOS TFT with gate voltage ranging from −5 to −10 V in steps of 1.25 V. d Output properties of the NMOS TFT with gate voltages ranging from 0 to 10 V in steps of 1 V. All devices had a channel size of 50×50 μm. (Panels a and b reproduced, with permission, from ref. 15)

Table 1 TFT properties of silicon ink-based PMOS and NMOS TFT fabricated on top of a paper substrate


We have demonstrated poly-Si transistors created directly on top of a paper substrate employing a silicon ink. We have successfully surpassed printed organic devices and are competing with printed indium–gallium–zinc-oxide (IGZO) TFTs. The issue with IGZO however, is the absence of a strong p-type counterpart,22 and their inclusion of In as one of the elements, which is a rare and expensive material.23 For the devices fabricated in this work, there is still room for optimization to improve the silicon device performance. Two key elements require special attention. The first is the possible effect of paper contaminating the silicon channel. Since no barrier layer was formed on top of the coated paper, prior to the silicon ink coating, and due to the excimer laser crystallization, it is plausible that contaminants from the coating may enter the silicon channel disrupting the electronic device operation. In general, contamination would need to be limited during the process, since no chemical cleaning treatment can be applied, unlike in fabrication processes for conventional devices. The second element would be to further limit the maximum processing temperature, since the paper substrate is prone to expansion, which leads to alignment errors as well as stresses in the devices.

As a proof of concept, besides the silicon islands, vacuum-based processes have been used in this work; however, solution-based alternatives can potentially be used. For the gate insulator a viable solution-based option is still necessary; however, atomic layer deposition (ALD) systems have shown to be applicable in roll-to-roll processing systems.24 Additionally, the methods developed in this work could also be applied on low-cost polymer substrates. This work presents an important milestone in terms of solution-based silicon electronics, paving a way toward reliable, low power, extreme low cost, flexible, and disposable electronics.


Shadow masks

Two types of shadow masks were used in the fabrication process of the TFT on paper, one for the local crystallization of polysilane, and one for the metallic contact deposition. For the local crystallization, a 4″ quartz wafer was used with a thickness of 700 μm. A thickness of 100 nm of 99% Al with 1% Si was created by physical vapor deposition (PVD) on top of the substrate at 50 °C. Island patterns were created by etching the metallic film after patterning by photolithography. A combination of phosphoric, nitric, and acetic acid (PES-77) was used to chemically etch the Al film followed by a 5 min rinse in demineralized water. The mask is cleaned at 40 °C with acetone for 1 min, with 99% HNO3 at room temperature for 10 min, and a final rinsing step with demineralized water for 5 min. For the shadow mask used for metal evaporation, a 4″, 550 μm thick silicon wafer is used as the starting substrate. Four micrometers thick 99% Al with 1% Si was created by PVD on the backside of the wafer, and 6 μm thick SiO2 was created on the front side by plasma-enhanced chemical vapor deposition (PECVD) of tetraethyl orthosilicate. The oxide layer forms a hard mask for the following deep reactive ion-etching (DRIE) process. The oxide was patterned by photolithography and dry etching. Using a large over-etching time, the patterns through the silicon wafer were created, regardless of the sidewalls. The polymer deposited in the DRIE process was removed by 30 min of oxygen plasma treatment at 1000 W. The backside aluminum was removed by 30 min of PES-77, wet-chemical etching. Finally, the wafer was cleaned in 99% HNO3 for 10 min followed by a 5 min rinse.

Thin-film transistors

The paper substrate (Powercoat®HD, Arjowiggins Creative Papers) was taped on a 4″ Si wafer using carbon tape. Inside a glovebox (MBraun, N2), the paper is coated with 12.5 μL of pure CPS with a doctor blade, while at the same time being cured with a 10 mW/cm2 UV light source (UV AHAND GS). Once the film stays stable for a few seconds, it is rapidly solidified by a UV light (Flood UV curing system, Loctite) with 300 mW/cm2 intensity for 30 s. The film is subsequently further cured with the intensity of 10 mW/cm2 for 30 min to ensure solidification throughout the thickness of the film. The lower intensity light source is chosen since it also irradiates heat and allows a larger fraction of the film to be polymerized while the degree of cross-linking is limited. In the case of high-intensity UV light, the degree of cross-linking would be so severe that the film will start to change color and behave like a semiconductor instead of an insulator. A quartz shadow mask is placed, metal side down, onto the sample and is fixed by a tape. A KrF excimer laser (248 nm, 20 ns) is used to crystallize the polysilane islands while leaving the parts covered by metal untreated. Laser fluences ranging from 40 to 100 mJ/cm2 and numbers of pulses ranging from 1 to 100 are used. The sample is then exposed to open air for 1 day to allow the untreated polysilane to oxidize. A gate oxide of 100 nm thick SiO2 is deposited by radio frequency plasma enhanced chemical vapor deposition (RF-PECVD) (AMIGO, Elettrorava) at 120 °C radiative heating. Compared to other low temperature alternative processes such as ALD, the RF-PECVD oxide performed best as shown in the Supplementary Information. The temperature experienced by the wafer in this process is ~100 °C. A through-wafer etched shadow mask was aligned by hand with an optical microscope for monitoring alignment markers. The mask was attached to the silicon carrier wafer of the paper sample by melting a wax (Crystalbond™ 590, Ted Pella. Inc.) locally around the edges of the wafers with a soldering iron. The 500 nm thick Al gate metal was deposited by evaporation. The temperature reached by the wafer is ~60 °C. The mask is subsequently removed by elevating the temperature of the edges to ~100 °C. Wax residues are removed by manual wiping with methanol. Ion implantation was used to dope the source and drain regions of the poly-Si channel. The gate metal blocks dopant ions from entering the channel directly underneath the gate, resulting in a self-aligning process. Boron ions were used to implant at an energy of 30 keV, with a dose of 3.0·1015 ions/cm2 for p-type devices. Phosphorus ions were used to implant at an energy of 10 keV with a dose of 5.0·1015 ions/cm2 for n-type devices. Prior to the implantation of the phosphorus ions, oxide was removed by a blanket plasma-etching step. This allowed the reduction in ion implantation energy. Dopants were activated by the same KrF excimer laser as used for the crystallization process. The same range of fluences and numbers of pulses were used. A second through-wafer etched shadow mask was aligned and attached to the carrier wafer by the wax. This time, patterns expose contact locations, and a dry etching process was employed to remove the oxide at the specific locations. Immediately after this etching process, 500 nm Al contact metal was deposited by evaporation without removing the mask, allowing the metal to reach the silicon channel in the exact locations where the oxide was removed. Finally, the shadow mask is removed and the paper may be peeled off the carrier wafer.

Material and device characterization

In order to assess the crystallinity of the excimer laser-annealed polysilane samples, Raman spectroscopy (Renishaw InVia, 514 nm) was employed. Additionally a change in color from transparent to light brown reveals the change in material bandgap, giving an indication of the transformation process. The process was repeated over at least 20 samples, with each sample exposed to various excimer laser treatments on predefined locations. The reproducibility of the results depended on the condition of the laser, the substrate, and the starting material in terms of thickness, curing, and aging. For this work, stated results met our assumptions and were the most reproducible with a standard deviation in the optimized crystallization laser fluence of ~10 mJ/cm2, and hence chosen for further analysis. For electrical measurements, a semiconductor parameter analyzer (HP4156) was used under ambient conditions. Since this work was aiming for a proof of concept, sacrificial design structures were used due to a large misalignment between layers due to the shadow masks being aligned manually. Therefore, a limited number of devices within a sample were operational. Statistical conclusions could therefore not be taken from these results alone. Therefore, in order to assess the potential of these devices, the best-performing ones were chosen and are still subject to further process optimization.

Data availability statement

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.