Abstract
Charge noise in the host semiconductor degrades the performance of spinqubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gatedefined quantum dots to improve charge noise systematically. Here, we address the semiconductordielectric interface and the buried quantum well of a ^{28}Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick ^{28}Si quantum wells, we find that improvements in the scattering properties and uniformity of the twodimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 μeV/Hz^{½} at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to CZgate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating longlived and highfidelity spin qubits into a larger system.
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Introduction
Spinqubits in silicon quantum dots are a promising platform for building a scalable quantum processor because they have a small footprint^{1}, long coherence times^{2,3}, and are compatible with advanced semiconductor manufacturing^{4}. Furthermore, rudimentary quantum algorithms have been executed^{5} and quantum logic at highfidelity performed^{6,7,8,9}. As the qubit count is increasing, with a sixqubit processor demonstrated^{10}, significant steps have been taken to couple silicon spin qubits at a distance, via microwave photons or spin shuttling^{11,12,13,14,15,16}, towards networked spinqubit tiles^{17}. However, electrical fluctuations associated with charge noise in the host semiconductor can decrease qubit readout and control fidelity^{18}. Reducing charge noise independently of the device location on a wafer is pivotal to achieving the ubiquitous highfidelity of quantum operations, within and across qubit tiles, necessary to execute more complex quantum algorithms.
Charge noise is commonly associated with twolevel fluctuators (TLF)^{19} in the semiconductor host. In gated heterostructures with buried quantum wells, TLF may arise from impurities in several locations: within the quantum well, the semiconductor barrier, the semiconductor/dielectric interface, and the dielectrics layers above^{20,21,22,23,24,25,26}. Furthermore, previous work on strainedSi MOSFETs^{27,28,29}, with strainedSi channels deposited on SiGe strain relaxed buffers, has associated charge noise with dislocations arising from strain relaxation, either deep in the SiGe buffer or at the quantum well/buffer interface. Since these impurities and dislocations are randomly distributed over the wafer and are also a main scattering source for electron transport in buried quantum wells^{30}, a holistic approach to materials engineering should be taken to address disorder in twodimensional electron gases and charge noise in quantum dots.
In this work, we demonstrate thin quantum wells in ^{28}Si/SiGe heterostructures with low and uniform charge noise, measured over several gatedefined quantum dot devices. By linking charge noise measurements to the scattering properties of the twodimensional electron gas, we show that a quiet environment for quantum dots is obtained by improving the semiconductor/dielectric interface and the crystalline quality of the quantum well. We feed the measured charge noise into a theoretical model, benchmark the model against recent experimental results^{6,10}, and predict that these optimized heterostructures may support longlived and highfidelity spin qubits.
Results
Description of ^{28}Si/SiGe heterostructures
Figure 1a illustrates the undoped ^{28}Si/SiGe heterostructures, grown by reducedpressure chemical vapor deposition, and the gatestack above. From bottom to top, the material stack comprises a 100 mm Si substrate, a strainrelaxed SiGe buffer layer, a strained ^{28}Si quantum well, a 30 nm thick SiGe barrier, a Si cap oxidized in air to form a SiO_{x} layer, an AlO_{x} layer formed by atomic layer deposition, and metallic gates. The SiGe layers above and below the quantum well have a Ge concentration of ≃0.3 (Methods).
We consider three ^{28}Si/SiGe heterostructures (A, B, C) to improve, in sequence, the semiconductor/dielectric interface (from A to B) and the crystalline quality of the quantum well (from B to C). Heterostructure A has an ≃9 nm thick quantum well and is terminated with an epitaxial Si cap grown by dichlorosilane at 675 °C. This kind of heterostructure has already produced high performance spinqubits^{6,10,31}. Heterostructure B misses a final epitaxial Si cap but features an amorphous Sirich layer obtained by exposing the SiGe barrier to dichlorosilane at 500 °C. Compared to A, heterostructure B supports a twodimensional electron gas with enhanced and more uniform transport properties across a 100 mm wafer, owing to a more uniform SiO_{x} layer with less scattering centers^{32}. Finally, we introduce here heterostructure C, having the same amorphous Sirich termination as in heterostructure B, but a thinner quantum well of ≃5 nm (Supplementary Fig. 1). This is much thinner than the MatthewsBlakeslee critical thickness^{33,34}, which is ≃10 nm^{35} for the relaxation of tensile Si on Si_{0.7}Ge_{0.3} via the formation of misfit dislocation at the bottom interface of the quantum well. In light of recent morphological characterization by electron channeling constrast imaging of Si/SiGe heterostructures with similar quantum well thickness and SiGe chemical composition^{36}, we expect misfit dislocation segments in heterostructure B because the quantum well approaches the MatthewsBlakeslee critical thickness. Due to the much thinner quantum well, instead, the epitaxial planes may adapt to the SiGe buffer much better in heterostructure C than in heterostructure B, meaning that misfit dislocations are, in principle, suppressed.
Figure 1b, c shows brightfield scanning transmission electron microscopy (BFSTEM) images from heterostructure C after fabrication of a Hall bar shaped heterostructure field effect transistors (HFET). We observe a sharp SiGe/SiO_{x} semiconductor/dielectric interface (Fig. 1b), characterized by a minor Ge pile up (dark line) in line with ref. ^{32}. The ≃5 nm thick quantum well (Fig. 1c, Supplementary Fig. 1) is uniform, has sharp interfaces to the nearby SiGe, and appears of high crystalline quality.
Electrical characterization of heterostructure field effect transistors
We evaluate the scattering properties of the twodimensional electron gases by waferscale electrical transport measured on Hallbar shaped HFETs operated in accumulation mode (Methods). For each heterostructure, multiple HFETs over a wafer are measured in the same cooldown at a temperature of 1.7 K in refrigerators equipped with cryomultiplexers^{37}. Figure 1d, e shows typical mobilitydensity and conductivitydensity curves for heterostructure C, from which we extract the mobility measured at high density (n = 6 × 10^{11} cm^{−2}) and the percolation density (n_{p})^{38}. The mobility rises steeply at low density due to progressive screening of scattering from remote impurities and flattens at higher density (n > 5 × 10^{11} cm^{−2}), limited by scattering from impurities within or nearby the quantum well, for example uniform background charges, surface roughness, or crystalline defects such as threading or misfit dislocations^{30,39}.
Charge noise measurements in quantum dots
For charge noise measurements, we use devices comprising a double quantum dot and a charge sensor quantum dot nearby, illustrated in Fig. 2a. Using the same device design, twoqubit gates with fidelity above 99% were demonstrated^{6}, silicon quantum circuits were controlled by CMOSbased cryogenic electronics^{31}, and energy splittings in ^{28}Si/SiGe heterostructures were studied with statistical significance^{40}.
Here, we electrostatically define a multielectron quantum dot in the charge sensor by applying gate voltages to the accumulation gates SDRAcc and SDLAcc, the barriers SDLB and SDRB, and the plunger gate P. All other gates (red in Fig. 2a) are set to 0 V for measurements of heterostructure B and C, whereas they are positively biased in heterostructure A to facilitate charge accumulation in the sensor (Methods). Figure 2b shows typical Coulomb blockade oscillations of the sourcedrain current I_{SD} for a charge sensor from heterostructure C measured at a dilution refrigerator base temperature of 50 mK. We follow the same tuneup procedure (Methods) consistently for all devices and we measure charge noise at the flank of each Coulomb peak within the V_{P} range defined by the first peak observable in transport and the last one before onset of a background channel (Supplementary Figs. 2–4). For example, in Fig. 2b we consider Coulomb peaks within the V_{P} range from 260 mV to 370 mV. The data collected in this systematic way is taken as a basis for comparison between the three different heterostructures in this study.
For each charge noise measurement at a given V_{P} we acquire 60 s (heterostructure A) or 600 s (heterostructures B, C) long traces of I_{SD} and split them into 10 (heterostructure A) or 15 windows (heterostructures B, C). We obtain the current noise spectrum S_{I} by averaging over the 10 (15) windows the discrete Fourier transform of the segments (Methods). We convert S_{I} to a charge noise spectrum S_{ϵ} using, for each measurement at a given V_{P}, the unique lever arm from the corresponding Coulomb diamonds and slope of the Coulomb peak to take into account a possible deformation of the charge sensor with the increasing electron number (inset Fig. 2b, Methods, and Supplementary Fig. 5). A representative charge noise spectrum S_{ϵ} measured at V_{P} = 360.3 mV is shown in Fig. 2c. We observe an approximate 1/f trend at low frequency, pointing towards an ensemble of TLF with a broad range of activation energies affecting charge noise around the charge sensor^{41,42}. Figure 2e shows the charge noise S_{ϵ} at 1 Hz as a function of V_{P}. The charge noise decreases, with a linear trend, with increasing V_{P}, suggesting that, similar to scattering in 2D, screening by an increased electron density shields the electronically active region from noise arising from the heterostructure and the gate stack^{43}. From this measurement we extract, for a given device, the minimum measured charge noise at 1 Hz (S_{ϵ,min} circled data point in Fig. 2e) upon variation of V_{P} in our experimental range. We use S_{ϵ,min} as an informative metric to compare charge noise levels from device to device in a given heterostructure. For a given device, all charge noise spectra S_{ϵ} are plotted in 3D as a function of f and V_{P} (Fig. 2d). To quantify our observations, we fit the data to the plane \(\log {S}_{\epsilon }=\alpha \log f+\beta {V}_{P}+\gamma\) (Supplementary Note 4). Coefficient α = 0.84 ± 0.01 indicates the spectrum power law exponent and coefficient β = − 15.6 ± 0.1 mV^{−1} quantifies the change in noise spectrum with increasing plunger gate and, consequently, the susceptibility of charge noise to the increasing electron number in the sensor.
Distribution of transport properties and charge noise
We have introduced key metrics for 2D electrical transport (μ, n_{p}) and charge noise (α, β and S_{ϵ,min}) from Hall bar and quantum dot measurements, respectively. In Fig. 3a–e we compare the distributions of all these metrics for the three heterostructures A, B, C. Each boxplot is obtained from the analysis of measurements in Figs. 1d, e, and 2d repeated on multiple HFETs or quantum dots, on dies randomly selected from different locations across the 100 mm wafers (Methods). To facilitate a comparison with previous studies, the minimum charge noise at 1 Hz is plotted in Fig. 3e as \({S}_{\epsilon,min}^{1/2}\) and therefore in units of μeV/Hz^{½}.
As reported earlier in ref. ^{32}, the improvement in both mean values and spread for μ and n_{p} was associated with a reduction of remote impurities when replacing the epitaxial Si cap in heterostructure A with a Sirich passivation layer in heterostructure B. Moving to heterostructure C, we measure a high mean mobility of (2.10 ± 0.08) × 10^{5} cm^{2}/Vs and a low mean percolation density of (7.68 ± 0.37) × 10^{10} cm^{−2}, representing an improvement by a factor ≃1.4 and ≃1.3, respectively (compared to heterostructure A). Most strikingly, the 99% confidence intervals of the mean for μ and n_{p} are drastically reduced by a factor ≃9.8 and ≃4.8, respectively. We speculate that these improvements in heterostructure C are associated with the suppression of misfit dislocations at the quantum well/buffer interface, thereby reducing short range scattering and increasing uniformity on a waferscale. This interpretation is supported by previous studies of mobility limiting mechanisms as a function of the quantum well thickness in strained Si/SiGe heterostructures^{39}. We speculate that further reducing the quantum well thickness could increase surface roughness scattering from the bottom interface, and therefore disorder. Instead, finetuning the quantum well thickness between 5 nm and 9 nm might minimize surface roughness scattering whilst still avoiding the formation of misfit dislocations.
We now shift our attention to the results of charge noise measurements. First, the power law exponent α (Fig. 3c) shows a mean value ≃1, however the 99% confidence interval and interquartile range increase when moving from heterostructure A to B and C. Next, we observe a decreasing trend for the absolute mean value of coefficient β (Fig. 3d), meaning that the noise spectrum is less susceptible to changes in V_{P}. Finally, Fig. 3e shows the distributions for \({S}_{\epsilon,min}^{1/2}\), the minimum charge noise at 1 Hz upon varying V_{P}. We find in heterostructure C an almost order of magnitude reduction in mean \({S}_{\epsilon,min}^{1/2}\) to 0.29 ± 0.02 μeV/Hz^{½}. This trend is confirmed by plotting the distributions of maximum charge noise at 1 Hz upon varying V_{P} (Supplementary Fig. 4). Furthermore, within the distribution of \({S}_{\epsilon,min}^{1/2}\) for heterostructure C, the minimum value of the measured charge noise as a function of V_{P} and across quantum dots is 0.15 μeV/Hz^{½}. These charge noise values are on par or compare favorably to the best values reported previously at 1 Hz in gate defined quantum dots. In multielectron quantum dots, charge noise of 0.47 μeV/Hz^{½} was reported for Si/SiGe^{44}, 0.6 μeV/Hz^{½} (average value, with a minimum of ≤0.2 μeV/Hz^{½}) for Ge/SiGe^{45}, 0.49 ± 0.1 μeV/Hz^{½} for Si/SiO_{2}^{46}, and 1 μeV/Hz^{½} for InSb^{47}. In singleelectron quantum dots, charge noise of 0.33 μeV/Hz^{½} was reported for Si/SiGe^{48} and 7.5 μeV/Hz^{½} for GaAs^{49}.
We understand the charge noise trends in Fig. 3c–e by relating them to the evolution of the disorder landscape moving from heterostructures A to B and C, as inferred by the electrical transport measurements in Fig. 3a, b. The narrow distribution of α in heterostructure A points to charge noise being dominated from many TLFs possibly located at the low quality semiconductor/dielectric interface and above, albeit other sources of charge noise in the surrounding environment of the quantum dot may be present, such as highly localized misfit dislocations arising from partial strain relaxation in the quantum well or other nearby fluctuators. With a better semiconductor/dielectric interface, the effect of these other nearby fluctuators emerges in heterostructure B and C as a larger spread of the frequency exponent α, indicating a nonuniform distribution of activation energies according to the DuttaHorn model^{50}. Yet, the noise spectra still follow a 1/flike behavior (Supplementary Fig. 3), suggesting that TLFs also experience slow temperature fluctuations^{42}. The electrical transport measurements support this interpretation: scattering from many remote impurities is dominant in heterostructure A, whereas with a better semiconductor/dielectric interface remote scattering has less impact in the transport metrics of heterostructures B and C.
The decreasing trend in ∣β∣ is in line with the observation from electrical transport. As the impurity density decreases from heterostructure A to B and C, charge noise is less affected by an increasing V_{P}, since screening of electrical noise through adding electrons to the charge sensor becomes less effective. While we are not able to measure directly the electron number in the charge sensor, we deem unlikely the hypothesis that charge sensors in heterostructure A are operated with considerably fewer electrons than in heterostructure C. This is because all operation gate voltages in heterostructure A are consistently larger than in heterostructure C (Supplementary Fig. 4), due to the higher disorder.
Finally, the drastic reduction in mean value and spread of \({S}_{\epsilon,min}^{1/2}\) mirrors the evolution of mean value and spread of n_{p} and μ. From heterostructure A to B, a reduction in scattering from remote impurities is likely to result in less charge noise from longrange TLFs. From heterostructure B to C, the reduction in the possible number of dislocations at the quantum well/buffer interface, further reduces the charge noise picked up by quantum dots. This explanation is based on earlier studies of charge noise in strained SiMOSFETs^{27,28,29}, which showed a correlation between lowfrequency noise spectral density and static device parameters. Dislocations at the bottom of the strained channel may act as scattering centers that degrade mobility and as traps for the capture and release of carriers, which causes noise similarly to traps at the dielectric interface.
Calculated dephasing time and infidelity
To emphasize the improvement of the electrical environment in the semiconductor host, we calculate the dephasing time \({T}_{2}^{\star }\) of charge and spin qubits assuming these qubits experience the same fluctuations as our ^{28}Si/SiGe quantum dots. The dephasing time of a qubit (in the quasistatic limit and faroff from a sweet spot) is given by^{51,52}
with the Planck constant h and the standard deviation
Importantly, both the charge noise amplitude \({S}_{\epsilon }^{2}(f)\) and the noise exponent α have a strong impact on the dephasing time while the low and high frequency cutoff, f_{low} and f_{high}, given by the duration of the experiment have a weaker impact. The prefactor \(\left\frac{\partial {{{{{{{\mathcal{E}}}}}}}}}{\partial \mu }\right\) translates shifts in chemical potential of the charge sensor into energy shifts of the qubit and depends on many parameters such as the type of qubit and the device itself. We find \(\left\frac{\partial {{{{{{{\mathcal{E}}}}}}}}}{\partial \mu }\right =1\) for a charge qubit^{53} and \(\left\frac{\partial {{{{{{{\mathcal{E}}}}}}}}}{\partial \mu }\right\approx 1{0}^{5}\) for an uncoupled spin qubit^{44} (see Supplementary Note 7 for a derivation of these numbers and the used frequency bandwidths).
Figure 4a shows the computed dephasing times of charge qubits (circle) and spin qubits (star) for all three heterostructures. These calculations represent a best case scenario, since we use the distribution of measured S_{ϵ,min} from Fig. 3 as input parameter for each heterostructure. The improvements in our material can be best seen by investigating \({T}_{2}^{\star }\) of the charge qubit since it is directly affected by charge noise. Our theoretical extrapolation shows two orders of magnitude improvement in \({T}_{2}^{\star }\) by switching from heterostructures A to heterostructures B and C. One order is gained from the reduced charge noise amplitude and another order is gained through a more beneficial noise exponent α > 1. Note, that the integration regimes differ for spin and charge qubits due to the different experimental setups and operation speeds^{44,53}. For potential spin qubits in heterostructure A the calculated \({T}_{2}^{\star }\) shows an average \({\overline{T}}_{2}^{\star }=8.4\pm 5.6\) μs. This distribution compares well with the distribution \({\overline{T}}_{2}^{\star }=6.7\pm 5.6\) μs of experimental \({T}_{2}^{\star }\) data from stateoftheart semiconductor spin qubits in materials with similar stacks as in heterostructure A^{6,10}. Note that while such comparisons oversimplify actual semiconductor spinqubit devices by reducing them to a single number, they fulfill two aims. They allow us to benchmark the computed performance of heterostructure A to past experiments and provide a prognosis on the qubit quality in novel material stacks. Heterostructures B and C, in this case, may support average dephasing times of \({\overline{T}}_{2}^{\star }=24.3\pm 12.5\) μs and \({\overline{T}}_{2}^{\star }=36.7\pm 18\) μs, respectively. The highest values \({T}_{2}^{\star }=70.1\) μs hints towards a possible long dephasing time for spin qubits, previously only reported in ref. ^{2}.
Figure 4b shows the simulated infidelity, a metric to measure the closeness to the ideal operation, of a universal CZgate between two spin qubits following ref. ^{6} and Supplementary Note 7. Note that the device used in ref. ^{6} has the same architecture as our test devices. In the CZgate simulation, noise couples in dominantly via barrier voltage fluctuations which affects the interaction between the electron spins. Again, we use the charge noise amplitude S_{ϵ,min} and exponent α from the quantum dot experiments in Fig. 3 as input for the simulations. The simulations show an averaged average gate infidelity \(1{\overline{F}}_{{\scriptstyle{{{{{\rm{CZ}}}}}}}}=0.02\pm 0.01\%\) which means on average a single error every 5000 runs. We also observe a saturation value close to 1 − F = 10^{−4} which arises from singlequbit dephasing \({T}_{2}^{\star }=20\) μs used in the simulations estimated from nuclear spin noise due to a 800 ppm concentration of the ^{29}Si silicon isotope which has a nonzero nuclear spin^{44}.
Discussion
In summary, we have measured electron transport and charge noise in ^{28}Si/SiGe heterostructures where we improve the semiconductor/dielectric interface, by adopting an amorphous Sirich passivation, and the structural quality of the quantum well, by reducing the quantum well thickness significantly below the MatthewBlakeslee critical thickness for strain relaxation. We relate disorder in 2D to charge noise in quantum dots by following a statistical approach to measurements. A reduction of remote impurities and dislocations nearby the quantum well is connected with the key improvements in the scattering properties of the 2D electron gas, such as mobility and percolation density, and their uniformity across a 100 mm wafer. The trend observed from electron transport in 2D is compatible with the observations from measurements of charge noise in quantum dots. As remote impurities are reduced, charge noise becomes more sensitive to local fluctuators nearby the quantum well and less subject to screening by an increased number of electrons in the dot. Furthermore, with this materials optimization, we achieve a statistical improvement of nearly one order of magnitude in the charge noise supported by quantum dots. Using the charge noise distribution as input parameter and benchmarking against published spinqubit data, we predict that our optimized semiconductor host could support longlived and highfidelity spin qubits. We envisage that further materials improvements in the structural quality of the quantum well, in addition to the commonly considered semiconductor/dielectric interface, may lead systematically to quantum dots with less noise and to better qubit performance.
Methods
Si/SiGe heterostructure growth
The ^{28}Si/SiGe heterostructures are grown on a 100mm ntype Si(001) substrate using an Epsilon 2000 (ASMI) reduced pressure chemical vapor deposition reactor. The reactor is equipped with a ^{28}SiH_{4} gas cylinder (1% dilution in H_{2}) for the growth of isotopically enriched ^{28}Si. The ^{28}SiH_{4} gas was obtained by reducing ^{28}SiF_{4} with a residual ^{29}Si concentration of 0.08%^{54}. Starting from the Si substrate, the layer sequence of all heterostructures comprises a 3 μm stepgraded Si_{(1−x)}Ge_{x} layer with a final Ge concentration of x = 0.3 achieved in four grading steps (x = 0.07, 0.14, 0.21, and 0.3), followed by a 2.4 μm Si_{0.7}Ge_{0.3} strainrelaxed buffer. The heterostructures differ for the active layers on top of the strainrelaxed buffer. Heterostructure A has a 9 nm tensile strained ^{28}Si quantum well, a 30 nm Si_{0.7}Ge_{0.3} barrier, and a sacrificial 1 nm epitaxial Si cap. Heterostructure B has an 9 nm tensile strained ^{28}Si quantum well, a 30 nm Si_{0.7}Ge_{0.3} barrier, and a sacrificial passivated Si cap grown at 500 °C. Heterostructure C has a 5 nm tensile strained ^{28}Si quantum well, a 30 nm Si_{0.7}Ge_{0.3} barrier, and a sacrificial passivated Si cap grown at 500 °C. A typical secondary ions mass spectrometry of our heterostructures is reported in Supplementary Fig. S13 of ref. ^{40} and the Ge concentration in the SiGe layers is confirmed by quantitative electron energy loss spectroscopy (EELS).
Device fabrication
The fabrication process for Hallbar shaped heterostructure field effect transistors (HFETs) involves: reactive ion etching of mesatrench to isolate the twodimensional electron gas; Pion implantation and activation by rapid thermal annealing at 700 °C; atomic layer deposition of a 10nmthick Al_{2}O_{3} gate oxide; deposition of thick dielectric pads to protect gate oxide during subsequent wire bonding step; sputtering of Al gate; electron beam evaporation of Ti:Pt to create ohmic contacts to the twodimensional electron gas via doped areas. All patterning is done by optical lithography. Double quantum dot devices are fabricated on wafer coupons from the same HFET fabrication run and share the process steps listed above. Doublequantum dot devices feature a single layer gate metallization and further require electron beam lithography, evaporation of Al (27 nm) or Ti:Pd (3:17 nm) thin film metal gate, liftoff, ALD of a 5 nm thick Al_{2}O_{3} insulating layer, and a global topgate.
Electrical characterization of HFETs
Hallbar HFETs measurements are performed in an attoDRY2100 variable temperature insert refrigerator at a base temperature of 1.7 K^{32}. We apply a sourcedrain bias of 100 μV and measure the sourcedrain current I_{SD}, the longitudinal voltage V_{xx}, and the transverse Hall voltage V_{xy} as function of the top gate voltage V_{g} and the external perpendicular magnetic field B. From here we calculate the longitudinal resistivity ρ_{xx} and transverse Hall resistivity ρ_{xy}. The Hall electron density n is obtained from the linear relationship ρ_{xy} = B/en at low magnetic fields. The carrier mobility μ is extracted from the relationship σ_{xx} = neμ, where e is the electron charge. The percolation density n_{p} is extracted by fitting the longitudinal conductivity σ_{xx} to the relation \({\sigma }_{xx}\propto {(n{n}_{p})}^{1.31}\). Here σ_{xx} is obtained via tensor inversion of ρ_{xx} at B = 0. The box plots in Fig. 3a, b for heterostructure A (red) and B (blue) expand previously published data in Fig. 2f, e of ref. ^{32} by considering measurements of 4 additional HFETs for heterostructure A (20 HFETs in total) and of 2 additional HFETs for heterostructure B (16 HFETs in total).
Electrical characterization of quantum dots
Measurements of the multielectron quantum dots defined in the charge sensor are performed in a Leiden cryogenic dilution refrigerator with a mixing chamber base temperature T_{MC} = 50 mK^{40}. The devices are tuned systematically with the following procedure. We sweep all gate voltages (V_{SDRAcc}, V_{SDRB}, V_{P}, V_{SDLB}, and V_{SDLAcc}) from 0 V towards more positive bias, until a sourcedrain current I_{SD} of ≈1 nA is measured, indicating that a conductive channel has formed in the device. We then reduce the barrier voltages to find the pinchoff voltages for each barrier. Subsequently, we measure I_{SD} as a function of V_{SDLB} and V_{SDRB} and from this 2D map we find a set of gate voltage parameters so that Coulomb blockade peaks are visible. We then fix the barrier voltages and sweep V_{P} to count how many clearly defined Coulomb peaks are observed before onset of a background current. The quantum dot is tuned to show at least 9 Coulomb peaks, so that noise spectra may be fitted as in Fig. 2d with meaningful error bars. If we see less than 9 Coulomb peaks we readjust the accumulation gate voltages V_{SDRAcc}, and V_{SDLAcc}, and repeat the 2D scan of V_{SDLB} against V_{SDRB}. In one case (device 2 of heterostructure A), we tuned device to show past 5 Coulomb peaks and still performed the fit of the charge noise spectra similar to the one shown in Fig. 2d. Further details on the extraction of the lever arms and operation gate voltages of the devices are provided in Supplementary Figs 4 and 5. We estimate an electron temperature of 190 mK by fitting Coulomb blockade peaks (see Supplementary Fig. 2 in ref. ^{32}) measured on quantum dot devices.
For heterostructure A we apply a source drain bias of 100 μV (1 device) or 150 μV (3 devices) across the quantum dot, finite gate voltages across the operation gates of the dot, and finite gate voltages across the screening gates. We measure the current I_{SD} and the current noise spectrum S_{I} on the left side of the Coulomb peak where ∣dI/dV_{P}∣ is largest. We use a sampling rate of 1 kHz for 1 min using a Keithley DMM6500 multimeter. The spectra are then divided into 10 segments of equal length and we use a Fourier transform to convert from timedomain to frequencydomain for a frequency range of 167 mHz–500 Hz. We set the upper limit of the frequency spectra at 10 Hz, to avoid influences from a broad peak at around 150 Hz coming from the setup (Supplementary Fig. 3). A peak in the power spectral density at 9 Hz is removed from the analysis since it is an artifact of the preamplifier. To convert the current noise spectrum to a charge noise spectrum, we use the formula^{20}
where a is the lever arm and ∣dI/dV_{P}∣ is the slope of the Coulomb peak at the plunger voltage used to acquire the time trace.
The charge noise measurements conditions have been slightly modified from sample A to sample B, C to extend the probed frequency range from 100 μHz to 10 μHz. For heterostructures B and C we apply a source drain bias of 150 μV across the quantum dot, finite gate voltages across the operation gates of the quantum dot, and we apply 0 V to all other gates. We measure the current I_{SD} and the current noise spectrum S_{I} on the left side of the Coulomb peak where ∣dI/dV_{P}∣ is largest. We use a sampling rate of 1 kHz for 10 min using a Keithley DMM6500 multimeter. The spectra are then divided into 15 segments of equal length and we use a Fourier transform to convert from timedomain to frequencydomain for a frequency range of 25 mHz–500 Hz. We set the upper limit of the frequency spectra at 10 Hz, to avoid influences from a broad peak at around 150 Hz coming from the setup. We use Eq. (3) to convert the current noise spectrum to a charge noise spectrum.
(Scanning) Transmission Electron Microscopy
For structural characterization with (S)TEM, we prepared crosssections of the quantum well heterostructures by using a Focused Ion Beam (Helios 600 dual beam microscope). Atomically resolved HAADF STEM data was acquired in a probe corrected TITAN microscope operated at 300 kV. Quantitative EELS was carried out in a TECNAI F20 microscope operated at 200 kV with approximately 2 eV energy resolution and 1 eV energy dispersion. Principal Component Analysis (PCA) was applied to the spectrum images to enhance S/N ratio.
Data availability
All data included in this work are available from the 4TU.ResearchData international data repository at https://doi.org/10.4121/20418579.
Change history
06 April 2023
A Correction to this paper has been published: https://doi.org/10.1038/s4146702337548z
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Acknowledgements
We acknowledge helpful discussions with G. Isella, D. Paul, M. Mehmandoost, the Scappucci group and the Vandersypen group. This research was supported by the European Union’s Horizon 2020 research and innovation programme under the Grant Agreement No. 951852 (QLSI project) and in part by the Army Research Office (Grant No. W911NF1710274). The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the Army Research Office (ARO), or the U.S. Government. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation herein. M.R. acknowledges support from the Netherlands Organization of Scientific Research (NWO) under Veni grant VI.Veni.212.223. ICN2 acknowledges funding from Generalitat de Catalunya 2021SGR00457. ICN2 is supported by the Severo Ochoa program from Spanish MCIN / AEI (Grant No.: CEX2021001214S) and is funded by the CERCA Programme / Generalitat de Catalunya and ERDF funds from EU. Part of the present work has been performed in the framework of Universitat Autònoma de Barcelona Materials Science PhD program. Authors acknowledge the use of instrumentation as well as the technical advice provided by the National Facility ELECMI ICTS, node “Laboratorio de Microscopias Avanzadas" at University of Zaragoza. M.B. acknowledges support from SUR Generalitat de Catalunya and the EU Social Fund; project ref. 2020 FI 00103. We acknowledge support from CSIC Interdisciplinary Thematic Platform (PTI+) on Quantum Technologies (PTIQTEP+).
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A.S. grew and designed the 28Si/SiGe heterostructures with B.P.W. and G.S.. M.R. developed the theory. A.S. and D.D.E. fabricated heterostructure field effect transistors measured by B.P.W. and D.D.E.. M.B and J.A. performed TEM characterization. S.A and D.D.E. fabricated quantum dot devices. B.P.W. and D.D.E. measured the quantum dot devices with contributions from A.M.J.Z.. G.S. conceived and supervised the project. B.P.W, D.D.E, M.R, and G.S. wrote the manuscript with input from all authors.
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Paquelet Wuetz, B., Degli Esposti, D., Zwerver, AM.J. et al. Reducing charge noise in quantum dots by using thin silicon quantum wells. Nat Commun 14, 1385 (2023). https://doi.org/10.1038/s4146702336951w
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DOI: https://doi.org/10.1038/s4146702336951w
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