Reducing charge noise in quantum dots by using thin silicon quantum wells

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a $^{28}$Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick $^{28}$Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29$\pm$0.02 $\mu$eV/sqrt(Hz) at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to cz-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system.

Spin-qubits in silicon quantum dots are a promising platform for building a scalable quantum processor because they have a small footprint [1], long coherence times [2,3], and are compatible with advanced semiconductor manufacturing [4].Furthermore, rudimentary quantum algorithms have been executed [5] and quantum logic at high-fidelity performed [6][7][8][9].As the qubit count is increasing, with a six-qubit processor demonstrated [10], significant steps have been taken to couple silicon spin qubits at a distance, via microwave photons or spin shuttling [11][12][13][14][15][16], towards networked spin-qubit tiles [17].However, electrical fluctuations associated with charge noise in the host semiconductor can decrease qubit readout and control fidelity [18].Reducing charge noise independently of the device location on a wafer is pivotal to achieving the ubiquitous high-fidelity of quantum operations, within and across qubit tiles, necessary to execute more complex quantum algorithms.
Charge noise is commonly associated with two-level fluctuators (TLF) [19] in the semiconductor host.In gated heterostructures with buried quantum wells, TLF may arise from impurities in several locations: within the quantum well, the semiconductor barrier, the semiconductor/dielectric interface, and the dielectrics layers above [20][21][22][23][24][25][26].Furthermore, previous work on strained-Si MOSFETs [27][28][29], with strained-Si channels deposited on SiGe strain relaxed buffers, has associated charge noise with dislocations arising from strain relaxation, either deep in the SiGe buffer or at the quantum well/buffer interface.Since these impurities and dislocations are randomly distributed over the wafer and are also a main scattering source for electron transport in buried quantum wells [30], a holistic approach to mate-rials engineering should be taken to address disorder in two-dimensional electron gases and charge noise in quantum dots.
In this work, we demonstrate thin quantum wells in 28 Si/SiGe heterostructures with low and uniform charge noise, measured over several gate-defined quantum dot devices.By linking charge noise measurements to the scattering properties of the two-dimensional electron gas, we show that a quiet environment for quantum dots is obtained by improving the semiconductor/dielectric interface and the crystalline quality of the quantum well.We feed the measured charge noise into a theoretical model, benchmark the model against recent experimental results [6,10], and predict that these optimized heterostructures may support long-lived and high-fidelity spin qubits.

Description of Si/SiGe heterostructures
Figure 1a illustrates the undoped 28 Si/SiGe heterostructures, grown by reduced-pressure chemical vapour deposition, and the gate-stack above.From bottom to top, the material stack comprises a 100 mm Si substrate, a strain-relaxed SiGe buffer layer, a strained 28 Si quantum well, a 30 nm thick SiGe barrier, a Si cap oxidized in air to form a SiO x layer, an AlO x layer formed by atomic layer deposition, and metallic gates.The SiGe layers above and below the quantum well have a Ge concentration of 0.3 (Methods).
We consider three 28 Si/SiGe heterostructures (A, B, C) to improve, in sequence, the semiconductor/dielectric interface (from A to B) and the crystalline quality of the quantum well (from B to C). Heterostructure A has an 9 nm thick quantum well and is terminated with an epitaxial Si cap grown by dichlorosilane at 675 • C.This kind of heterostructure has already produced high performance spin-qubits [6,10,31].Heterostructure B misses a final epitaxial Si cap but features an amorphous Si-rich layer obtained by exposing the SiGe barrier to dichlorosilane at 500 • C. Compared to A, heterostructure B supports a two-dimensional electron gas with enhanced and more uniform transport properties across a 100 mm wafer, owing to a more uniform SiO x layer with less scattering centers [32].Finally, we introduce here heterostructure C, having the same amorphous Si-rich termination as in heterostructure B, but a thinner quantum well of 5 nm (Supplementary Fig. 1).This is much thinner than the Matthews-Blakeslee critical thickness [33,34], which is 10 nm [35] for the relaxation of tensile Si on Si 0.7 Ge 0.3 via the formation of misfit dislocation at the bottom interface of the quantum well.
Figures 1b, c show bright-field scanning transmis-sion electron microscopy (BF-STEM) images from heterostructure C after fabrication of a Hall bar shaped heterostructure field effect transistors (H-FET).We observe a sharp SiGe/SiO x semiconductor/dielectric interface (Fig. 1b), characterised by a minor Ge pile up (dark line) in line with Ref. [32].The 5 nm thick quantum well (Fig. 1c) is uniform and has sharp interfaces to the nearby SiGe.No structural defects such as misfit dislocations are visible, suggesting they are, at most, scarce.By analysing Raman spectra (Supplementary Fig. 2), we estimate a tensile strain for the 28 Si quantum wells in heterostrucure B and C of (0.93±0.02)% and (1.22±0.02)%,respectively, compared the expected strain of 1.2% for the given stoichiometry of the heterostructures.These measurements point to significant strain relaxation in heterostructure B compared to C. In heterostructure B, the quantum wells approach the Matthews-Blakeslee critical thickness and therefore misfit dislocation segments are expected, in light of recent morphological characterisation of Si/SiGe heterostructures with similar quantum well thickness and SiGe chemical composition [36].Due to the ∼ 2× thinner quantum well, instead, heterostructure C adapts the epitaxial planes to the SiGe buffer much better than heterostructure B, meaning that misfit dislocations arising from strain-relaxation are, in principle, suppressed.

Electrical characterisation of H-FETs
We evaluate the scattering properties of the twodimensional electron gases by wafer-scale electrical transport measured on Hall-bar shaped H-FETs operated in accumulation mode (Methods).For each heterostructure, multiple H-FETs over a wafer are measured in the same cool-down at a temperature of 1.7 K in refrigerators equipped with cryo-multiplexers [37].Figures 1d,  e show typical mobility-density and conductivity-density curves for heterostructure C, from which we extract the mobility measured at high density (n = 6 × 10 11 cm −2 ) and the percolation density (n p ) [38].The mobility rises steeply at low density due to progressive screening of scattering from remote impurities and flattens at higher density (n > 5 × 10 11 cm −2 ), limited by scattering from impurities within or nearby the quantum well, for example uniform background charges, surface roughness, or crystalline defects such as threading or misfit dislocations [30,39].

Charge noise measurements in quantum dots
For charge noise measurements, we use devices comprising a double quantum dot and a charge sensor quantum dot nearby, illustrated in Fig. 2a.Using the same device design, two-qubit gates with fidelity above 99% were demonstrated [6], silicon quantum circuits were controlled by CMOS-based cryogenic electronics [31], and energy splittings in 28 Si/SiGe heterostructures were studied with statistical significance [40].
Here, we electrostatically define a multi-electron quantum dot in the charge sensor by applying gate voltages to the accumulation gates SDRAcc and SDLAcc, the barriers SDLB and SDRB, and the plunger gate P. All other gates (red in Fig. 2a) are set to 0 V for measurements of heterostructure B and C, whereas they are positively biased in heterostructure A to facilitate charge accumulation in the sensor (Methods).Figure 2b shows typical Coulomb blockade oscillations of the source-drain current I SD for a charge sensor from heterostructure C measured at a dilution refrigerator base temperature of 50 mK.We follow the same tune-up procedure (Methods) consistently for all devices and we measure charge noise at the flank of each Coulomb peak within the V P range defined by the first peak observable in transport and the last one before onset of a background channel (Supplementary Figs.3,4).For example, in Figure 2b we consider Coulomb peaks within the V P range from 260 mV to 370 mV.The data collected in this systematic way is taken as a basis for comparison between the three different heterostructures in this study.
For each charge noise measurement at a given V P we acquire 60 s (heterostructure A) or 600 s (heterostructures B, C) long traces of I SD and split them into 10 (heterostructure A) or 15 windows (heterostructures B, C).We obtain the current noise spectrum S I by averaging over the 10 (15) windows the discrete Fourier transform of the segments (Methods).We convert S I to a charge noise spectrum S using lever arms from Coulomb diamond measurements and the slope of the Coulomb peaks (inset Fig. 2b, Methods, and Supplementary Fig. 5).A representative charge noise spectrum S measured at V P = 360.3mV is shown in Fig. 2c.We observe an approximate 1/f trend at low frequency, pointing towards an ensemble of TLF with a broad range of activation energies affecting charge noise around the charge sensor [41,42].Figure 2e shows the charge noise S 1/2 at 1 Hz as a function of V P .The charge noise decreases, with a linear trend, with increasing V P , suggesting that, similar to scattering in 2D, screening by an increased electron density shields the electronically active region from noise arising from the heterostructure and the gate stack [43].From this measurement we extract, for a given device, the minimum measured charge noise at 1 Hz (S 1/2 ,min ) upon variation of V P in our experimental range.We use S 1/2 ,min , as an informative metric to compare charge noise levels from device to device in a given heterostructure.For a given device, all charge noise spectra S are plotted in 3D as a function of f and V P (Fig. 2d).To quantify our observations, we fit the data to the plane log S = −α log f + βV P + γ with coefficient α = 0.84 ± 0.01 indicating the spectrum power law exponent and coefficient β = −15.6 ± 0.1 µeV 2 /VHz quantifying the change in noise spectrum with increasing plunger gate and, consequently, the susceptibility of charge noise to the increasing electron number in the sensor.

Distribution of transport properties and charge noise
We have introduced key metrics for 2D electrical transport (µ, n p ) and charge noise (α, β and S 1/2 ,min ) from Hall bar and quantum dot measurements, respectively.In Figs.3a-e we compare the distributions of all these metrics for the three heterostructures A, B, C. Each boxplot is obtained from the analysis of measurements in Figs.1d,e, and Fig. 2d repeated on multiple H-FETs or quantum dots, on dies randomly selected from different locations across the 100 mm wafers (Methods).As reported earlier in Ref. [32], the improvement in both mean values and spread for µ and n p was associated with a reduction of remote impurities when replacing the epitaxial Si cap in heterostructure A with a Si-rich passivation layer in heterostructure B. Moving to heterostructure C, we measure a high mean mobility of (2.10 ± 0.08) × 10 5 cm 2 /Vs and a low mean percolation density of (7.68 ± 0.37) × 10 10 cm −2 , representing an improvement by a factor 1.4 and 1.3, respectively (compared to heterostructure A).Most strikingly, the 99% confidence intervals of the mean for µ and n p are drastically reduced by a factor 9.8 and 4.8, respectively.We speculate that these improvements in heterostructure C are associated with the suppression of misfit dislocations at the quantum well/buffer inter-  ,min within the range of VP investigated for heterostructure A (red, 4 devices measured), B (blue, 7 devices measured), and C (green, 5 devices measured).Quartile box plots, mode (horizontal line), means (diamonds), 99% confidence intervals of the mean (dashed whiskers), and outliers (circles) are shown.
face, thereby reducing short range scattering and increasing uniformity on a wafer-scale.This interpretation is supported by the strain characterisation discussed above and by previous studies of mobility limiting mechanisms as a function of the quantum well thickness in strained Si/SiGe heterostructures [39].
We now shift our attention to the results of charge noise measurements.First, the power law exponent α (Fig. 3c) shows a mean value 1, however the 99% confidence interval and interquartile range increase when moving from heterostructure A to B and C. Next, we observe a decreasing trend for the absolute mean value of coefficient β (Fig. 3d), meaning that the noise spectrum is less susceptible to changes in V P .Finally, we plot in Fig. 3e the distributions for S 1/2 ,min , the minimum charge noise at 1 Hz upon varying V P .We find in heterostructure C an almost order of magnitude reduction in mean S  [46], and 1 µeV/ √ Hz for InSb [47].In singleelectron quantum dots, charge noise of 0.33 µeV/ √ Hz was reported for Si/SiGe [48] and 7.5 µeV/ √ Hz for GaAs [49].
We understand the charge noise trends in Figs.3c-e by relating them to the evolution of the disorder landscape moving from heterostructures A to B and C, as inferred by the electrical transport measurements in Figs.3a,b.The narrow distribution of α in heterostructure A points to charge noise from many TLFs possibly located at the low quality semiconductor/dielectric interface and above.Instead, the larger spread in α in heterostructure B and C implies that deviations from 1/f behaviour become more frequent, possibly originating from a non-uniform distribution of TLF or from one low frequency TLF in the surrounding environment of the quantum dot that dominates the power spectrum in the measured interval.The electrical transport measurements support this interpretation: scattering from many remote impurities is dominant in heterostructure A, whereas with a better semiconductor/dielectric interface remote scattering has less impact in the transport metrics of heterostructures B and C.
The decreasing trend in |β| is in line with the observation from electrical transport.As the impurity density decreases from heterostructure A to B and C, charge noise is less affected by an increasing V P , since screening of electrical noise through adding electrons to the charge sensor becomes less effective, possibly due to a smaller TLF-per-volume ratio.While we are not able to measure directly the electron number in the charge sensor, we deem unlikely the hypothesis that charge sensors in heterostructure A are operated with considerably fewer electrons than in heterostructure C.This is because all operation gate voltages in heterostructure A are consistently larger than in heterostructure C (Supplementary Fig. 4), due to the higher disorder.
Finally, the drastic reduction in mean value and spread of S 1/2 ,min mirrors the evolution of mean value and spread of n p and µ.From heterostructure A to B, a reduction in scattering from remote impurities is likely to result in less charge noise from long-range TLFs.From heterostructure B to C, the larger strain, and consequently the reduction in the possible number of dislocations at the quantum well/buffer interface, further reduces the charge noise picked up by quantum dots.This explanation is based on earlier studies of charge noise in strained Si-MOSFETs [27][28][29], which showed a corre-lation between low-frequency noise spectral density and static device parameters.Dislocations at the bottom of the strained channel may act as scattering centers that degrade mobility and as traps for the capture and release of carriers, which causes noise similarly to traps at the dielectric interface.

Calculated dephasing time and infidelity
To emphasize the improvement of the electrical environment in the semiconductor host, we calculate the dephasing time T 2 of charge and spin qubits assuming these qubits experience the same fluctuations as our 28 Si/SiGe quantum dots.The dephasing time of a qubit (in the quasistatic limit and far-off from a sweet spot) is given by [50] with the Planck constant h and the standard deviation Importantly, both the charge noise amplitude S 2 (f ) and the noise exponent α have a strong impact on the dephasing time while the low and high frequency cut-off, f low and f high , given by the duration of the experiment have a weaker impact.The prefactor ∂E ∂µ translates shifts in chemical potential of the charge sensor into energy shifts of the qubit and depends on many parameters such as the type of qubit and the device itself.We find ∂E ∂µ = 1 for a charge qubit [51] and ∂E ∂µ ≈ 10 −5 for an uncoupled spin-qubit [44] (see Supplementary Information for a derivation of these numbers and the used frequency bandwidths).
Figure 4a shows the computed dephasing times of charge qubits (circle) and spin qubits (star) for all three heterostructures.The improvements in our material can be best seen by investigating T 2 of the charge qubit since it is directly affected by charge noise.Our theoretical extrapolation shows two orders of magnitude improvement in T 2 by switching from heterostructures A to heterostructures B and C [52].Note, that the integration regimes differ for spin and charge qubits due to the different experimental setups and operation speeds [44,51].For potential spin qubits in heterostructure A the calculated T 2 shows an average T 2 = 8.4 ± 5.6 µs.This distribution compares well with the distribution T 2 = 6.7 ± 5.6 µs of experimental T 2 data from stateof-the-art semiconductor spin qubits in materials with similar stacks as in heterostructure A [6,10].Note that while such comparisons oversimplify actual semiconductor spin-qubit devices by reducing them to a single number, they fulfill two aims.They allow us to benchmark (circle) and a spin-qubit (star) using S ,min from heterostructure A (red), B (blue), C (green).Eq. ( 1) was used to compute T 2 as a function of S and α from Fig. 3. Literature values (squares) are taken from Refs.[6,10].b Simulated infidelity of a cz-gate between two spin qubits following the Ref. [6] using S and α from heterostructure A (red), B (blue), C (green) in Fig. 3 as input for barrier fluctuations.
the computed performance of heterostructure A to past experiments and provide a prognosis on the qubit quality in novel material stacks.Heterostructures B and C, in this case, may support average dephasing times of T 2 = 24.3 ± 12.5 µs and T 2 = 36.7 ± 18 µs, respectively.The highest values T 2 = 70.1 µs hints towards a long spin qubit dephasing times previously only reported in Ref. [2].
Figure 4b shows the simulated infidelity, a metric to measure the closeness to the ideal operation, of a universal cz-gate between two spin qubits following Ref.[6] and Section 5 in the Supplementary Information.Note, that the device used in Ref. [6] has the same architecture as our test devices.In the cz-gate simulation noise dominantly couples in via barrier voltage fluctuations which affects the interaction between the electron spins.Again, we assume the charge noise amplitude and exponents measured in our quantum dot experiments as input for the simulations.The simulations show an averaged average gate infidelity 1 − F cz = 0.02 ± 0.01 % which means on average a single error every 5000 runs.We also observe a saturation value close to 1 − F = 10 −4 which arises from single-qubit dephasing T 2 = 20 µs used in the simulations estimated from nuclear spin noise due to a 800 ppm concentration of the 29 Si silicon isotope which has a non-zero nuclear spin [44].

DISCUSSION
In summary, we have measured electron transport and charge noise in 28 Si/SiGe heterostructures where we improve the semiconductor/dielectric interface, by adopting an amorphous Si-rich passivation, and the structural quality of the quantum well, by reducing the quantum well thickness significantly below the Matthew-Blakeslee critical thickness for strain relaxation.We relate disorder in 2D to charge noise in quantum dots by following a statistical approach to measurements.A reduction of remote impurities and dislocations nearby the quantum well is connected with the key improvements in the scattering properties of the 2D electron gas, such as mobility and percolation density, and their uniformity across a 100 mm wafer.The trend observed from electron transport in 2D is compatible with the observations from measurements of charge noise in quantum dots.As remote impurities are reduced, charge noise becomes more sensitive to local fluctuators nearby the quantum well and less subject to screening by an increased number of electrons in the dot.Furthermore, with this materials optimization, we achieve a statistical improvement of nearly one order of magnitude in the charge noise supported by quantum dots.Using the charge noise distribution as input parameter and benchmarking against published spinqubit data, we predict that our optimized semiconductor host could support long-lived and high-fidelity spin qubits.We envisage that further materials improvements in the structural quality of the quantum well, in addition to the commonly considered semiconductor/dielectric interface, may lead systematically to quantum dots with less noise and to better qubit performance.

METHODS
Si/SiGe heterostructure growth.The 28 Si/SiGe heterostructures are grown on a 100-mm n-type Si(001) substrate using an Epsilon 2000 (ASMI) reduced pressure chemical vapor deposition reactor.The reactor is equipped with a 28 SiH 4 gas cylinder (1% dilution in H 2 ) for the growth of isotopically enriched 28 Si.The 28 SiH 4 gas was obtained by reducing 28 SiF 4 with a residual 29 Si concentration of 0.08% [53].Starting from the Si substrate, the layer sequence of all heterostructures comprises a 3 µm step-graded Si (1−x) Gex layer with a final Ge concentration of x = 0.3 achieved in four grading steps (x = 0.07, 0.14, 0.21, and 0.3), followed by a 2.4 µm Si 0.7 Ge 0.3 strain-relaxed buffer.The heterostructures differ for the active layers on top of the strain-relaxed buffer.Heterostructure A has a 9 nm tensile strained 28 Si quantum well, a 30 nm Si 0.7 Ge 0.3 barrier, and a sacrificial 1 nm epitaxial Si cap.Heterostructure B has an 9 nm tensile strained 28 Si quantum well, a 30 nm Si 0.7 Ge 0.3 barrier, and a sacrificial passivated Si cap grown at 500 • C. Heterostructure C has a 5 nm tensile strained 28 Si quantum well, a 30 nm Si 0.7 Ge 0.3 barrier, and a sacrificial passivated Si cap grown at 500 • C. A typical secondary ions mass spectrometry of our heterostructures is reported in Fig. S13 of [40] and the Ge concentration in the SiGe layers is confirmed by quantitative electron energy loss spectroscopy (EELS).
Device fabrication.The fabrication process for Hall-bar shaped heterostructure field effect transistors (H-FETs) involves: reactive ion etching of mesa-trench to isolate the two-dimensional electron gas; P-ion implantation and activation by rapid thermal annealing at 700 • C; atomic layer deposition of a 10-nm-thick Al 2 O 3 gate oxide; deposition of thick dielectric pads to protect gate oxide during subsequent wire bonding step; sputtering of Al gate; electron beam evaporation of Ti:Pt to create ohmic contacts to the two-dimensional electron gas via doped areas.All patterning is done by optical lithography.Double quantum dot devices are fabricated on wafer coupons from the same H-FET fabrication run and share the process steps listed above.Double-quantum dot devices feature a single layer gate metallization and further require electron beam lithography, evaporation of Al (27 nm) or Ti:Pd (3:27 nm) thin film metal gate, lift-off, and the global top-gate layer.
Electrical characterization of H-FETs.Hall-bar H-FETs measurements are performed in an attoDRY2100 variable temperature insert refrigerator at a base temperature of 1.7 K [32].We apply a source-drain bias of 100 µV and measure the source-drain current I SD , the longitudinal voltage Vxx, and the transverse Hall voltage Vxy as function of the top gate voltage Vg and the external perpendicular magnetic field B. From here we calculate the longitudinal resistivity ρxx and transverse Hall resistivity ρxy.The Hall electron density n is obtained from the linear relationship ρxy = B/en at low magnetic fields.The carrier mobility µ is extracted from the relationship σxx = neµ, where e is the electron charge.The percolation density np is extracted by fitting the longitudinal conductivity σxx to the relation σxx ∝ (n − np) 1.31 .Here σxx is obtained via tensor inversion of ρxx at B = 0.The box plots in Figs.3a,b for heterostructure A (red) and B (blue) expand previously published data in Figs.2f,e of Ref. [32] by considering measurements of 4 additional H-FETs for heterostructure A (20 H-FETs in total) and of 2 additional H-FETs for heterostructure B (16 H-FETs in total).
Electrical characterization of quantum dots.Measurements of the multi-electron quantum dots defined in the charge sensor are performed in a Leiden cryogenic dilution refrigerator with a mixing chamber base temperature T MC = 50 mK [40].The devices are tuned systematically with the following procedure.We sweep all gate voltages (V SDRAcc , V SDRB , V P , V SDLB , and V SDLAcc ) from 0 V towards more positive bias, until a source-drain current I SD of ≈ 1 nA is measured, indicating that a conductive channel has formed in the device.We then reduce the barrier voltages to find the pinch-off voltages for each barrier.Subsequently, we measure I SD as a function of V SDLB and V SDRB and from this 2D map we find a set of gate voltage parameters so that Coulomb blockade peaks are visible.We then fix the barrier voltages and sweep V P to count how many clearly defined Coulomb peaks are observed before onset of a background current.The quantum dot is tuned to show at least 9 Coulomb peaks, so that noise spectra may be fitted as in Fig. 2d with meaningful error bars.If we see less than 9 Coulomb peaks we readjust the accumulation gate voltages V SDRAcc , and V SDLAcc , and repeat the 2D scan of V SDLB against V SDRB .In one case (device 2 of heterostructure A), we tuned device to show past 5 Coulomb peaks and still performed the fit of the charge noise spectra similar to the one shown in Fig. 2d.Further details on the extraction of the lever arms and operation gate voltages of the devices are provided in Supplementary Figs 4,5.We estimate an electron temperature of 190 mK by fitting Coulomb blockade peaks (see Supplementary Fig. 2 in Ref. [32]) measured on quantum dot devices.
For heterostructure A we apply a source drain bias of 100 µV (1 device) or 150 µV (3 devices) across the quantum dot, finite gate voltages across the operation gates of the dot, and finite gate voltages across the screening gates.We measure the current I SD and the current noise spectrum S I on the left side of the Coulomb peak where |dI/dV P | is largest.We use a sampling rate of 1 kHz for 1 minute using a Keithley DMM6500 multimeter.The spectra are then divided into 10 segments of equal length and we use a Fourier transform to convert from time-domain to frequency-domain for a frequency range of 167 mHz-500 Hz.We set the upper limit of the frequency spectra at 10 Hz, to avoid influences from a broad peak at around 150 Hz coming from the setup (Supplementary Fig. 3).A peak in the power spectral density at 9 Hz is removed from the analysis since it is an artifact of the pre-amplifier.To convert the current noise spectrum to a charge noise spectrum we use the formula where a is the lever arm and |dI/dV P | is the slope of Coulomb peak around the center of the Coulomb peak.
For heterostructures B and C we apply a source drain bias of 150 µV across the quantum dot, finite gate voltages across the operation gates of the quantum dot, and we apply 0 V to all other gates.We measure the current I SD and the current noise spectrum S I on the left side of the Coulomb peak where |dI/dV P | is largest.We use a sampling rate of 1 kHz for 10 minutes using a Keithley DMM6500 multimeter.The spectra are then divided into 15 segments of equal length and we use a Fourier transform to convert from time-domain to frequency-domain for a frequency range of 25 mHz-500 Hz.We set the upper limit of the frequency spectra at 10 Hz, to avoid influences from a broad peak at around 150 Hz coming from the setup.We use Eq. 3 to convert the current noise spectrum to a charge noise spectrum.
(Scanning) Transmission Electron Microscopy.For structural characterization with (S)TEM, we prepared cross-sections of the quantum well heterostructures by using a Focused Ion Beam (Helios 600 dual beam microscope).HR-TEM micrographs were acquired in a TECNAI F20 microscope operated at 200 kV.Atomically resolved HAADF STEM data was acquired in a probe corrected TITAN microscope operated at 300 kV.EELS mapping was carried out in a TECNAI F20 microscope operated at 200 kV with approximately 2 eV energy resolution and 1 eV energy dispersion.Principal Component Analysis (PCA) was applied to the spectrum images to enhance S/N ratio.To avoid possible errors associated with calibration, we measure the thickness of the Si layer in the quantum wells (t qw ) for heterostructures B and C by considering the interplanar spacing of the horizontal planes (002) of the quantum well (d qw ) and of the underlying the strain-relaxed SiGe buffer layer (d buf f er ).For the Si 1−x Ge x buffer layer, we consider the stoichiometry x as measured by means of quantitative EELS and calculate the theoretical expected cell parameter a cell using the following approximation of Vegard's law:

MEASUREMENT OF THE THICKNESS OF THE QUANTUM WELLS
where a Si = 5.431 Å is the cell parameter of the diamond cubic Si crystal phase.To calculate d buf f we use the formula for the interplanar distance of the desired plane (002) of a diamond cubic system: Since the quantum well is strained, d qw is found by considering the average dilatation δ of the quantum well (002) planes with respect the (002) planes of the buffer.The dilatation δ is obtained experimentally by Geometrical Phase Analysis (GPA).The standard deviation of GPA is high for dilatation close to 0, as happens with the (220) epitaxial planes, for which the method is not the preferred choice.Nevertheless, for the larger dilatation of the (002) planes, the relatively smaller standard deviation makes the measurement significative.As a result, d qw is computed by: Finally, the thickness of the quantum well is given by: where we count the number of planes forming the quantum well (n qw ) and multiply by d qw .Therefore, the expected uncertainty of the thickness measurement lies in whether the initial and last plane of the well are being considered or not, i.e. the standard deviation is given by σ = 2d qw .With this in mind, for heterostructure B, where x = 0.31, three different measurements counting the (002) planes were performed in different regions of the quantum well, n qw = 34, 35 and 36.With an average experimental δ of -1.4±0.4 %, we obtain d qw = 2.709 ± 0.012 Å, resulting in an average thickness t qw = 9.5 ± 0.5 nm.
For heterostructure C, x = 0.31 and two measurements counting the (002) planes were performed, n qw = 19 and 20.With an average experimental δ of -1.7±0.5 %, we obtain d qw = 2.701 ± 0.014 Å, resulting in an average thickness t qw = 5.3 ± 0.5 nm.We calculate the strain of the Si quantum wells in heterostructures B and C by converting phonon frequency shifts into biaxial strain values [1,2]

STRAIN ANALYSIS WITH RAMAN SPECTROSCOPY
where ω 0 = 520 cm −1 is the Raman shift associated with the Si-Si vibration from the unstrained Si substrate from Ref. [3], b Si = 723 ± 15 cm −1 is the strain-shift coefficient for Si reported in Ref. [4], and ω( ) is the Raman shift associated with the Si-Si vibration from the strained quantum well.For heterostructure B we measure ω( ) = 513.25 cm −1 , corresponding to a tensile strain = (0.93 ± 0.02)%.For heterostructure C we measure ω( ) = 511.12cm −1 , corresponding to a tensile strain = (1.22 ± 0.02)%.The errors on the strain estimate arise from the 2% error reported for b Si .) ,min values make up the distributions plotted in Fig. 2e of the main text.We recall that heterostructure A features a 9 nm thick quantum well and is terminated with an epitaxial Si cap grown by dichlorosilane at 675 • C. Heterostructure B has also a 9 nm thick quantum well but features an amorphous Si-rich layer obtained by exposing the SiGe barrier to dichlorosilane at 500 • C. Heterostructure C, having the same amorphous Si-rich termination as in heterostructure B, but a thinner quantum well of 5 nm.b-g Distributions of the operation gate voltages of the plunger, SDLAcc, SDLB, SDRB, SDRAcc, and screening gates, respectively (see Fig. 1f in the main text) for heterostructure A (red, 4 devices measured), B (blue, 8 devices measured), and C (green, 5 devices measured).With the exception of gate SDLB, all operation voltages of the charge sensor are highest in heterostructure A and lowest in heterostructure C with a difference of up to 600 mV.Note that a global screening gate is only used for the operation of heterostructure A. Quartile box plots, mode (horizontal line), means (diamonds), 99% confidence intervals of the mean (dashed whiskers), and outliers (circles) are shown.

SIMULATIONS OF DEPHASING TIMES AND GATE FIDELITIES
Charge noise as measured in this paper leads to a loss of coherence for all kinds of quantum states.For qubit systems such decoherence can be described by 2 reference numbers.The qubit's relaxation time T 1 and it's dephasing time T 2 .Low frequency charge noise as measured dominantly affects the dephasing time T 2 of a qubit.Here, T 2 references the free induction decay of a Ramsey experiment and describes the decay of a superposition state due to fluctuations in the qubit's resonance frequency.The dephasing time T 2 depends on the characteristics of the noise as well as the susceptibility of the qubit to the fluctuations.In short, charge qubits are more susceptible to charge noise than spin qubits.For a general qubit with energies E the dephasing time can be expressed as where S is the measured noise spectral density of the chemical potential µ and f hf,(lf) are the high (low-) frequency cut-off frequency.Note, that this simple expression for the dephasing time only holds away from a sweet spot [5,6], ∂E ∂µ = 0.

Dephasing of charge qubit
A charge qubit in general consist of two charge states with a difference in chemical potential = µ 2 − µ 1 that are coupled via a tunnel matrix element t c .Such a system can be described by the simple Hamiltonian where σ x , σ y , and σ z are the three Pauli matrices.Charge noise couples to the charge qubit directly via their chemical potentials.As a consequence a charge qubit is maximally susceptible to charge noise and we find ∂E ∂µ = 1 in the regime t c .We take the values for the frequency cut-offs f hf = 33 GHz and f lf = 20 Hz from Ref. [7] for our simulation to ease comparison.

Dephasing of spin qubit
A spin qubit is ideally not affected by changes in the electrostatic environment from charge noise.However, due to intrinsic spin-orbit interaction (SOI) and artificial SOI through a micromagnet charge noise can couple to the spin degree of freedom.For a spin qubit made in SiGe using a micromagnet we find with the voltage displacement ∂x ∂V = 0.024 nm/mV, field gradient ∂Bz ∂x = 0.08 mT/nm, Bohr's Magneton µ B = 0.0579 µeV/mT, g-factor g = 2, lever arm α sensor = 0.07 eV/V, and frequency cut-offs f hf = 10 kHz and f lf = 1.6 mHz all taken from Ref. [8].

Gate fidelity simulations
In order to extrapolate the performance of a two-qubit cz gate from the measured charge noise we perform numerical simulations.The details of the simulations are described in Ref. [9] using the measured charge noise as an input.We simulate the unitary evolution operator of a cz two-qubit gate using adiabatic barrier control at the detuning charge noise sweet spot.Colored charge noise is numerically generated using the Fourier filter method [10,11] and added to the control pulses.For the simulation we use an additional heuristic lever arm α barrier = 1 mV/µeV into consideration to translate the measured fluctuations in chemical potential to fluctuations in barrier voltage in the simulation.With this specification the charge noise measured in Ref. [9] would translate to S 1/2 = 0.4 µeV/Hz 1/2 , a reasonable assumption.To benchmark the performance we compute the average gate infidelity a commonly used metric for the quality of gates for all measured spectral densities S (f ) = S /f α .

Figure 1 .
Figure1. a Schematics of the28 Si/SiGe heterostructure and dielectric stack above.z indicates the heterostructure growth direction.Circles represent remote impurities at the semiconductor/dielectric interface and perpendicular symbols represent misfit dislocations that might arise at the quantum well/buffer interface due to strain relaxation.b, c BF-STEM images from heterostructure C highlighting the semiconductor/dielectric interface and the 5 nm thick28 Si quantum well, respectively.d Mobility µ and e conductivity σxx measured as a function of density n at a temperature of 1.6 K in a Hall bar H-FET from heterostructure C. The red curve in e is a fit to percolation theory.

Figure 2 .
Figure 2. a False colored SEM-image of a double quantum dot system with a nearby charge sensor.Charge noise is measured in the multi-electron quantum dot defined by accumulation gates SDLAcc and SDRAcc (blue), plunger P (blue), with the current going along the black arrow.In these experiments, the gates defining the double quantum dot (red) are used as screening gates.There is an additional global top gate (not shown) to facilitate charge accumulation when needed.b Source-drain current ISD through a charge sensor device fabricated on heterostructure C against the plunger gate voltage VP .Colored dots mark the position of the flank of the Coulomb peak where charge noise measurements are performed.The inset shows Coulomb diamonds from the same device, plotted as the differential of the current dI/dV as a function of VP and the source drain bias VSD.c Charge noise spectrum S measured at the Coulomb peak at VP 345 mV in b and extracted using lever arms from Coulomb diamonds.d Charge noise spectrum S for the same device in b, plotted in 3D as a function of VP and f .The dark gray plane is a fit through the datasets.e Charge noise at f = 1 Hz obtained from data in d.The grey line is a line cut through the plane in i at f = 1 Hz.

Figure 3 .
Figure 3. a, b Distributions of mobility µ measured at n = 6×1011 cm −2 and percolation density np for heterostructure A (red, 20 H-FETs measured, of which 16 reported in Ref.[32]), B (blue, 16 H-FETs measured of which 14 reported in Ref.[32]), and C (green, 22 H-FETs measured).c-e Distributions of noise spectrum power law exponent α, coefficient β indicating the change in noise spectrum with increasing VP , and minimum charge noise S

2 *Figure 4 .
Figure4. a Computed dephasing times T 2 of a charge qubit (circle) and a spin-qubit (star) using S ,min from heterostructure A (red), B (blue), C (green).Eq. (1) was used to compute T 2 as a function of S and α from Fig.3.Literature values (squares) are taken from Refs.[6, 10].b Simulated infidelity of a cz-gate between two spin qubits following the Ref.[6]   using S and α from heterostructure A (red), B (blue), C (green) in Fig.3as input for barrier fluctuations.

Figure S1 .
Figure S1.Method for computing the thickness of the quantum well based on the counting of the (002) horizontal planes, which reduces the uncertainty and bias associated to properly detecting the margins of the quantum well.The images are from heterostructure C. Scale bars are 10 nm (left image) and 2 nm (center image))

Figure S2 .
Figure S2.Baseline corrected Raman spectra taken with a laser wavelength λ = 532 nm for heterostructure B and C, respectively.Spectra are band-fitted with Lorentzian-Gaussian bands, to accurately represent the values of each vibration and the shifts due to the strained structures.The inset shows the peaks due to the buried strained Si quantum well for heterostructure B and C. The blue shift of the peak for heterostructure B indicates strain relaxation compared to heterostructure C.

Figure S4. a Charge noise S 1 / 2 at 1 2 ,min at 1
Figure S4. a Charge noise S 1/2 at 1 Hz as a function of the plunger gate voltage VP for all measured devices of heterostructure A (red), B (blue), C (green).The circled dots highlight the minimum S 1/2 ,min at 1 Hz for each device upon varying VP within the range considered.For a given heterostructure, these S 1/2

Figure S5 .
Figure S5.Differential conductance (dI/dV ) showing representative Coulomb blockade diamonds as a function of the sourcedrain voltage (VSD) and plunger gate voltage (VP ) for heterostructure C. We derive the two slopes mS and mD on both sides of each Coulomb diamond.Using the equation a = | m S m D m S −m D |, we extract a lever arm of a = 0.12 eV/V for the Coulomb peak at VP ≈ 308 mV, where we indicate mS and mD with magenta lines.The dashed line indicates the source-drain voltage used for the charge noise measurements.