Over the past several years, the inherent scaling limitations of silicon (Si) electron devices have fuelled the exploration of alternative semiconductors, with high carrier mobility, to further enhance device performance1,2,3,4,5,6,7,8. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied7,9,10: such devices combine the high mobility of III–V semiconductors and the well established, low-cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored9,11,12,13—but besides complexity, high defect densities and junction leakage currents present limitations in this approach. Motivated by this challenge, here we use an epitaxial transfer method for the integration of ultrathin layers of single-crystal InAs on Si/SiO2 substrates. As a parallel with silicon-on-insulator (SOI) technology14, we use ‘XOI’ to represent our compound semiconductor-on-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high-quality InAs/dielectric interface is obtained by the use of a novel thermally grown interfacial InAsO x layer (~1 nm thick). The fabricated field-effect transistors exhibit a peak transconductance of ~1.6 mS µm−1 at a drain–source voltage of 0.5 V, with an on/off current ratio of greater than 10,000.
Subscribe to Journal
Get full journal access for 1 year
only $3.90 per issue
All prices are NET prices.
VAT will be added later in the checkout.
Rent or Buy article
Get time limited or full article access on ReadCube.
All prices are NET prices.
Lundstrom, M. Moore’s law forever? Science 299, 210–211 (2003)
Heyns, M. & Tsai, W. Ultimate scaling of CMOS logic devices with Ge and III–V materials. Mater. Res. Soc. Bull. 34, 485–488 (2009)
Theis, T. N. & Solomon, P. M. It’s time to reinvent the transistor!. Science 327, 1600–1601 (2010)
Chau, R., Doyle, B., Datta, S., Kavalieros, J. & Zhang, K. Integrated nanoelectronics for the future. Nature Mater. 6, 810–812 (2007)
Javey, A., Guo, J., Wang, W., Lundstrom, M. & Dai, H. Ballistic carbon nanotube transistors. Nature 424, 654–657 (2003)
Wong, P. H.-S. Beyond the conventional transistor. Solid-State Electron. 49, 755–762 (2005)
Wu, Y. Q., Xu, M., Wang, R. S., Koybasi, O. & Ye, P. Y. High performance deep-submicron inversion-mode InGaAs MOSFETs with maximum Gm exceeding 1.1 mS/um: new HBr pretreatment and channel Engineering. IEEE IEDM Tech. Digest 2009, 323–326 (2009)
Bryllert, T., Wernersson, L. E., Froberg, L. E. & Samuelson, L. Vertical high-mobility wrap-gated InAs nanowire transistor. IEEE Electron Device Lett. 27, 323–325 (2006)
Liu, Y. et al. in Fundamentals of III–V Semiconductor MOSFETs (eds Oktyabrsky, S. & Ye, P.) 31–46 (Springer, 2010)
Radosavljevic, M. et al. Advanced high-k gate dielectric for high-performance short-channel In0. 7Ga0. 3As quantum well field effect transistors on silicon substrate for low power logic applications. IEEE IEDM Tech. Digest 2009, 319–322 (2009)
Javorka, P. et al. AlGaN/GaN HEMTs on (111) silicon substrates. IEEE Electron Device Lett. 23, 4–6 (2002)
Balakrishnan, G. et al. Room-temperature optically-pumped GaSb quantum well based VCSEL monolithically grown on Si (100) substrate. Electron. Lett. 42, 350–351 (2006)
Yonezu, H. Control of structural defects in group III–V-N alloys grown on Si. Semicond. Sci. Technol. 17, 762–768 (2002)
Celler, G. K. & Cristoloveanu, S. Frontiers of silicon-on-insulator. J. Appl. Phys. 93, 4955–4978 (2003)
Yablonovitch, E., Hwang, D. M., Gmitter, T. J., Florez, L. T. & Harbison, J. P. Van der Waals bonding of GaAs epitaxial liftoff films onto arbitrary substrates. Appl. Phys. Lett. 56, 2419–2421 (1990)
Kim, D.-H. et al. Ultrathin silicon circuits with strain-isolation layers and mesh layouts for high-performance electronics on fabric, vinyl, leather, and paper. Adv. Mater. 21, 3703–3707 (2009)
Melosh, N. et al. Ultrahigh density nanowire lattices and circuits. Science 300, 112–115 (2003)
Yokoyama, M. et al. III–V-semiconductor-on-insulator n-channel metal-insulator-semiconductor field-effect transistors with buried Al2O3 layers and sulfur passivation: Reduction in carrier scattering at the bottom interface. Appl. Phys. Lett. 96, 142106 (2010)
Yuan, H.-C. & Ma, Z. Microwave thin-film transistors using Si nanomembranes on flexible polymer substrate. Appl. Phys. Lett. 89, 212105 (2006)
Kim, D.-H. et al. Stretchable and foldable silicon integrated circuits. Science 320, 507–511 (2008)
Yoon, J. et al. GaAs photovoltaics and optoelectronics using releasable multilayer epitaxial assemblies. Nature 465, 329–333 (2010)
Chueh, Y.-L. et al. Formation and characterization of NixInAs/InAs nanowire heterostructures by solid source reaction. Nano Lett. 8, 4528–4533 (2008)
Kim, D.-H. et al. Scalability of sub-100 nm InAs HEMTs on InP substrate for future logic applications. IEEE Trans. Electron. Dev. 57, 1504–1511 (2010)
Lundstrom, M. Fundamentals of Carrier Transport 54–118 (Cambridge Univ. Press, 2000)
Mikhailova, M. P. in Handbook Series of Semiconductor Parameters Vol. 1, Elementary Semiconductors and A3B5 Compounds Si, Ge C, GaAs, GaP, GaSb InAs, InP, InSb (eds Levinshtein, M., Rumyantsev, S. & Shur, M.) 31–46 (World Scientific, 1996)
Martens, K. et al. On the correct extraction of interface trap density of MOS devices with high-mobility semiconductor substrates. IEEE Trans. Electron. Dev. 55, 547–556 (2008)
DeSalvo, G. C., Kaspi, R. & Bozada, C. A. Citric acid etching of GaAs1-xSbx, Al0. 5Ga0. 5Sb, and InAs for heterostructure device fabrication. J. Electrochem. Soc. 141, 3526–3531 (1994)
Yoh, K., Kiyomi, K., Nishida, A. & Inoue, M. Indium arsenide quantum wires fabricated by electron beam lithography and wet-chemical etching. Jpn. J. Appl. Phys. 31, 4515–4519 (1992)
Meitl, M. A. et al. Transfer printing by kinetic control of adhesion to an elastomeric stamp. Nature Mater. 5, 33–38 (2006)
This work was funded by the MARCO/MSD Focus Center, Intel Corporation and BSAC. The materials characterization part of this work was partially supported by an LDRD from Lawrence Berkeley National Laboratory. A.J. acknowledges a Sloan research fellowship, an NSF CAREER award, and support from the World Class University programme at Sunchon National University. R.K. and M.M. acknowledge respectively an NSF graduate fellowship and a postdoctoral fellowship from the Danish Research Council for Technology and Production Sciences. S.K. acknowledges support from AFOSR contract FA9550-10-1-0113. Y.-L.C. acknowledges support from the National Science Council, Taiwan, through grant no. NSC 98-2112-M-007-025-MY3.
The authors declare no competing financial interests.
About this article
Cite this article
Ko, H., Takei, K., Kapadia, R. et al. Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors. Nature 468, 286–289 (2010). https://doi.org/10.1038/nature09541
Carrier transport and dielectric permittivity of SiO2 films containing ion-beam synthesized InSb nanocrystals
Journal of Alloys and Compounds (2020)
Microsystems & Nanoengineering (2020)
Nano-Micro Letters (2020)
Atomic Investigation on the Facet‐Dependent Melting of Ceramic Nanostructures via In Situ Electron Irradiation
Advanced Materials Interfaces (2020)