Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors


Over the past several years, the inherent scaling limitations of silicon (Si) electron devices have fuelled the exploration of alternative semiconductors, with high carrier mobility, to further enhance device performance1,2,3,4,5,6,7,8. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied7,9,10: such devices combine the high mobility of III–V semiconductors and the well established, low-cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored9,11,12,13—but besides complexity, high defect densities and junction leakage currents present limitations in this approach. Motivated by this challenge, here we use an epitaxial transfer method for the integration of ultrathin layers of single-crystal InAs on Si/SiO2 substrates. As a parallel with silicon-on-insulator (SOI) technology14, we use ‘XOI’ to represent our compound semiconductor-on-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high-quality InAs/dielectric interface is obtained by the use of a novel thermally grown interfacial InAsO x layer (~1 nm thick). The fabricated field-effect transistors exhibit a peak transconductance of ~1.6 mS µm−1 at a drain–source voltage of 0.5 V, with an on/off current ratio of greater than 10,000.

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Figure 1: Fabrication scheme for ultrathin InAs XOI, and AFM images.
Figure 2: Cross-sectional TEM analysis of InAs XOI substrates.
Figure 3: Back-gated, long-channel InAs XOI FETs.
Figure 4: Top-gated InAs XOI FETs.


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This work was funded by the MARCO/MSD Focus Center, Intel Corporation and BSAC. The materials characterization part of this work was partially supported by an LDRD from Lawrence Berkeley National Laboratory. A.J. acknowledges a Sloan research fellowship, an NSF CAREER award, and support from the World Class University programme at Sunchon National University. R.K. and M.M. acknowledge respectively an NSF graduate fellowship and a postdoctoral fellowship from the Danish Research Council for Technology and Production Sciences. S.K. acknowledges support from AFOSR contract FA9550-10-1-0113. Y.-L.C. acknowledges support from the National Science Council, Taiwan, through grant no. NSC 98-2112-M-007-025-MY3.

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H.K., K.T. and A.J. designed the experiments. H.K., K.T., S.C., H.F., E.P., H.S.K., M.M. and A.C.F. carried out the experiments. R.K. and P.W.L. performed device simulations. K.G. and S.S. performed mobility calculations. S.-Y.C. and Y.-L.C. performed TEM imaging. H.K., K.T., R.K., P.W.L., K.G., S.K., S.S. and A.J. contributed to analysing the data. H.K., K.T., R.K. and A.J. wrote the paper while all authors provided feedback.

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Correspondence to Ali Javey.

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Ko, H., Takei, K., Kapadia, R. et al. Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors. Nature 468, 286–289 (2010). https://doi.org/10.1038/nature09541

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