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Ballistic two-dimensional InSe transistors

Nature volume 616, pages 470–475 (2023)Cite this article

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Abstract

The International Roadmap for Devices and Systems (IRDS) forecasts that, for silicon-based metal–oxide–semiconductor (MOS) field-effect transistors (FETs), the scaling of the gate length will stop at 12 nm and the ultimate supply voltage will not decrease to less than 0.6 V (ref. 1). This defines the final integration density and power consumption at the end of the scaling process for silicon-based chips. In recent years, two-dimensional (2D) layered semiconductors with atom-scale thicknesses have been explored as potential channel materials to support further miniaturization and integrated electronics. However, so far, no 2D semiconductor-based FETs have exhibited performances that can surpass state-of-the-art silicon FETs. Here we report a FET with 2D indium selenide (InSe) with high thermal velocity as channel material that operates at 0.5 V and achieves record high transconductance of 6 mS μm−1 and a room-temperature ballistic ratio in the saturation region of 83%, surpassing those of any reported silicon FETs. An yttrium-doping-induced phase-transition method is developed for making ohmic contacts with InSe and the InSe FET is scaled down to 10 nm in channel length. Our InSe FETs can effectively suppress short-channel effects with a low subthreshold swing (SS) of 75 mV per decade and drain-induced barrier lowering (DIBL) of 22 mV V−1. Furthermore, low contact resistance of 62 Ω μm is reliably extracted in 10-nm ballistic InSe FETs, leading to a smaller intrinsic delay and much lower energy-delay product (EDP) than the predicted silicon limit.

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Fig. 1: Structural and electronic characteristics of ballistic InSe FETs.
Fig. 2: Electronic characteristics and total resistance of InSe FETs.
Fig. 3: Benchmarking InSe, silicon and InGaAs FETs.
Fig. 4: Short-channel effect comparison of InSe FETs and silicon FinFETs.

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The data that support the findings of this study are available from the corresponding author on reasonable request.

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Acknowledgements

Funding for this work was provided by the National Key Research & Development Program of China (grant no. 2021YFA0717400) and the National Science Foundation of China (grant nos. 61888102, 61971009 and 62122006). We thank L.G. and F.M. (Institute of Physics, Chinese Academy of Sciences) for focused ion beam and STEM technique support.

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  1. These authors contributed equally: Jianfeng Jiang, Lin Xu

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  1. Key Laboratory for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, School of Electronics, Peking University, Beijing, China

    Jianfeng Jiang, Lin Xu, Chenguang Qiu & Lian-Mao Peng

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  1. Jianfeng Jiang
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Contributions

C.Q. and L.-M.P. proposed and supervised the project. J.J., C.Q. and L.-M.P. conceived the idea and designed the experiment. J.J. performed InSe material characterization, device fabrication and device characterization. L.X. provided the calculations and simulations based on DFT theory, TCAD models and compact models. J.J., C.Q., L.X. and L.-M.P. analysed the experimental and modelling results. J.J., C.Q., L.-M.P. and L.X. cowrote the manuscript. All authors commented on and discussed this work.

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Correspondence to Chenguang Qiu or Lian-Mao Peng.

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Extended data figures and tables

Extended Data Fig. 1 Structure characterization and schematic process flow of ballistic InSe FETs.

a, STEM image showing a top view of the atomic structure of few-layer InSe and corresponding selected electron diffraction pattern taken from the same InSe region. Scale bar, 2 nm. Inset, atomic structures of 2D InSe. Our InSe sample has an excellent crystal structure and an expected hexagonal lattice spacing of 3.4 Å without visible defects. b, Top-view SEM images of ballistic InSe FETs. Scale bar, 400 nm. c, Schematic process flow and structure of ballistic InSe FETs.

Extended Data Fig. 2 Benchmarking ID versus ns and TLM.

a, Benchmarking ID versus ns at VDS = 0.5 V (refs. 29,71,72,73,74,75). The numbers in parentheses is the channel length (nm). b, SEM image of a set of devices for TLM. c, Total resistance versus channel length, leading to a minimum value of 83 Ω μm. The fluctuation of resistances between different electrodes in the long channels leads to some inaccuracy in the extracted 2RC.

Extended Data Fig. 3 Comparison of transfer characteristics at various temperatures and Landauer formula.

a, Transfer characteristics of a ballistic non-optimal Schottky-barrier 2D InSe FET at various temperatures ranging from 300 to 100 K. b, Transfer characteristics of a ballistic ohmic-contact 2D InSe FET at various temperatures ranging from 300 to 100 K. c, Comparison of transfer characteristics of a ballistic ohmic-contact InSe FET and a ballistic non-optimal Schottky-barrier InSe FET at VDS = 0.3 V at 100 K. In a ballistic unoptimized Schottky-barrier InSe FET, the transfer curve exhibits two slopes below the threshold at low temperature. The lower part is exclusively thermionic emission (TE) current corresponding to carriers over the potential barrier, which is dominated by the channel. The upper part consists of thermionic emission and tunnelling current, also called thermal field emission (TFE). With an incremental change in VGS, the thermionic emission component changes only slightly owing to the Schottky-barrier effect. Also, the main increase in current is because of the tunnelling enhancement through squeezing the source Schottky barrier width and therefore exhibits a poor SS62,63. d, Experimental and theoretical total resistances in ballistic InSe transistors. The red stars are the experimental total resistance from typical output characteristics (Fig. 1j) and the black line is the calculated total resistance of the quantum limit by Landauer’s approach (related to the number of modes)76,77.

Extended Data Fig. 4 Capacitance–voltage characteristics and CQ simulation.

a,b, Optical and SEM images of our metal–insulator–metal (MIM) structure for capacitance–voltage (C–V) characteristics. c, Schematic diagram of the MIM structure. d, Typical as-measured back-gate multifrequency C–V curves; 19 frequency curves are measured between 10 kHz and 1 MHz. e, Typical back-gate C–V hysteresis curve at a frequency of 1 MHz. f, The back-gate capacitance versus f (10 kHz to 1 MHz) for VGS = 0.1, 0.3, 0.5 and 0.7 V. g, Thirty MIM curves of back-gate capacitance versus f (10 kHz to 1 MHz) at VGS = 0.5 V. h, Typical as-measured top-gate multifrequency C–V curves; 19 frequency curves are measured between 10 kHz and 1 MHz. i, Typical top-gate C–V hysteresis curve at a frequency of 1 MHz. j, The top-gate capacitance versus f (10 kHz to 1 MHz) for VGS = 0.1, 0.3, 0.5 and 0.7 V. k, Thirty MIM curves of top-gate capacitance versus f (10 kHz to 1 MHz) at VGS = 0.5 V. l, Simulated CQ versus VGS − VT, for a 10-nm InSe FET at VDS = 0 V and 0.5 V.

Extended Data Fig. 5 Transconductances of ballistic InSe FETs.

a, Transfer characteristics for ten typical ballistic InSe FETs at VDS = 0.5 V. The dashed line is the theoretically calculated transfer curve39. b, Corresponding transconductance of ten typical ballistic InSe FETs at VDS = 0.5 V. The best transconductance is 6 mS μm−1. Six FETs have transconductances exceeding 4 mS μm−1. The dashed line is the theoretically calculated transconductance39. c,d, Transfer curve and output of a typical ballistic InSe FET (with a transconductance of 6 mS μm−1). e, Transfer characteristics of a typical ballistic 2D InSe FET with 20-nm channel length at VDS = 0.1, 0.3, 0.5 and 0.7 V. f, Transfer characteristics comparison of ballistic 2D InSe FET at VDS = 0.5 and 0.7 V (coloured dots), 10-nm-node silicon FinFET (Intel, solid black line) and 20-nm-LG InGaAs FinFET normalized by state-of-the-art Fin Pitch = 34 nm (IBM, dashed black line). Note that all currents are normalized with the same rule. g, Transconductances comparison of typical ballistic 2D InSe FETs, a 10-nm-node silicon FinFET (Intel, solid black line) and an InGaAs FinFET (IBM, dashed black line). h, Transconductances comparison of ballistic 2D InSe FET at VDS = 0.5 and 0.7 V and other 2D FETs with sub-50-nm LG at VDD = 1 V. It shows that the transconductance of our InSe FETs at VDS = 0.7 V reaches 7 mS µm−1, which is larger than that of silicon FETs at the same bias voltage of VDS = 0.7 V but with slight degraded off-leakage current and subthreshold slope. The large transconductances of our 2D-InSe FETs benefit from several features of our FETs, including the ballistic channel with hardly any scatterings, higher thermal velocity, better source and drain contacts with negligible Schottky barriers and 2.6-nm-thick HfO2 double-gate structure.

Extended Data Fig. 6 Virtual Source Model fitting of output characteristics of InSe FETs.

Comparison of the Virtual Source Model fitting (hollow circles) and measured data (lines) for output characteristics of InSe FETs with LG = 10 nm (a) and LG = 20 nm (b). These results correspond to the red stars in Fig. 3e. To obtain an accurate Virtual Source Model fitting to extract the values of ballistic ratios, here a small gate voltage step of 0.1 V is used during output measurements.

Extended Data Fig. 7 Inner spacer structure and TCAD simulation.

a, Schematic diagram of a proposed process to achieve self-aligned (overlap-free) double-gate structure with low-k inner spacer and the process is compatible with the Y-doping ohmic contact. b,c, TCAD simulation of electron density distribution on the extension surfaces between the gate and the source/drain in ballistic InSe FETs with different k of the spacer. d, Schematic diagram of the ballistic InSe FETs with and without overlap from TCAD. e, The TCAD simulations of transfer curves of ballistic InSe FETs with (red) and without (black) overlap. f, On-state current density versus doping concentration of the ungated region below the spacer.

Extended Data Fig. 8 Transfer characteristics of typical ballistic InSe FETs and InSe thickness dependence of FET characteristics.

a, Transfer characteristics of five typical ballistic InSe FETs with LG = 10 nm, including SS and DIBL. b, Transfer characteristics of five typical ballistic InSe FETs with LG = 20 nm, including SS and DIBL. c, Typical AFM height profile of InSe samples, corresponding to 1, 3, 6, 13 and 22 layers. d, Dependence of the transfer characteristics of FETs on InSe channel thicknesses as in c. The reason for choosing the three-layer InSe channel material is that the monolayer InSe channel material has several basic limitations. (1) Monolayer InSe is more sensitive to the external environment and processing process than the three-layer InSe, so the on-state current and SS of the fabricated monolayer InSe FETs are degraded to some extent (Extended Data Fig. 8d). (2) The intrinsic electrical properties (thermal velocity etc.) of monolayer InSe are lower than those of the three-layer InSe channel (Fig. 1a) and, in addition, quantum-transport simulations also show that the transistors based on few-layer 2D semiconductors have higher on-state currents than those of monolayer 2D counterparts40,78.

Extended Data Fig. 9 Ballistic InSe FETs with single-top-gate, single-back-gate and dual-gate structures.

a,b, TCAD simulations of single-top-gate, single-back-gate and double-gate structures with 2.4-nm-thickness InSe channel and 10-nm gate length. The green transfer curve is the single-top-gate InSe FET, the blue transfer curve is the single-back-gate InSe FET and the red transfer curve is the dual-gate InSe FET. c, The experiment of the single-top-gate, the single-back-gate and the double-gate structures with 2.4-nm-thickness InSe channel and 20-nm channel length. The green transfer curve is the single-top-gate InSe FET, the blue transfer curve is the single-back-gate InSe FET and the red transfer curve is the dual-gate InSe FET. d, Top-view SEM images of ballistic InSe FETs with the single back gate (before top-gate fabrication) and the dual gate (after top-gate fabrication). e,f, The transfer characteristics of the typical ballistic 10-nm-channel-length InSe FETs with the single back gate (before top-gate fabrication, blue curves) and the dual gate (red curves). g,h, The transfer characteristics of the typical ballistic 20-nm-channel-length InSe FETs with the single back gate (before top-gate fabrication, blue curves) and the dual gate (red curves).

Extended Data Fig. 10 Electrical stability of ballistic 2D InSe FETs.

a, Transfer characteristics of a ballistic back-gate InSe FET without encapsulation in ambient conditions. b, Transfer characteristics of a ballistic double-gate InSe FET with top-gate encapsulation in ambient conditions. c, Transfer characteristics of a ballistic double-gate InSe FET before and after annealing at 250 °C for 1 h. LCH = 10 nm and VDS = 0.5 V. d, Output characteristics of the ballistic double-gate InSe FET before and after annealing at 250 °C for 1 h. LCH = 10 nm. Atomic thin InSe semiconductor is sensitive to moisture in the air and will suffer from a certain degree of degradation51,52,53. However, in previous reports, passivated InSe FETs encapsulated with hexagonal boron nitride45, a high-quality dry oxide51, high-k dielectric layer52 or PMMA53 show high stability and can be maintained for a long time. Here we adopt the double-gate structure, including HfO2/Ti/Au top-gate stacks. The high-k dielectric and top-gate metal covered on the InSe surface act as a passivation layer, which can effectively isolate moisture and oxygen in the air and improve the FETs’ stability.

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Jiang, J., Xu, L., Qiu, C. et al. Ballistic two-dimensional InSe transistors. Nature 616, 470–475 (2023). https://doi.org/10.1038/s41586-023-05819-w

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