Two-dimensional semiconductors for transistors

Abstract

In the quest for higher performance, the dimensions of field-effect transistors (FETs) continue to decrease. However, the reduction in size of FETs comprising 3D semiconductors is limited by the rate at which heat, generated from static power, is dissipated. The increase in static power and the leakage of current between the source and drain electrodes that causes this increase, are referred to as short-channel effects. In FETs with channels made from 2D semiconductors, leakage current is almost eliminated because all electrons are confined in atomically thin channels and, hence, are uniformly influenced by the gate voltage. In this Review, we provide a mathematical framework to evaluate the performance of FETs and describe the challenges for improving the performances of short-channel FETs in relation to the properties of 2D materials, including graphene, transition metal dichalcogenides, phosphorene and silicene. We also describe tunnelling FETs that possess extremely low-power switching behaviour and explain how they can be realized using heterostructures of 2D semiconductors.

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Figure 1: Advantages of 2D materials compared with 3D materials for FETs.
Figure 2: Operating principles of a FET with 2D semiconducting materials forming the channels.
Figure 3: Calculated FET characteristics and spin–valley locking in the valence band of 2D TMDs.
Figure 4: Energy band alignments and device properties of 2D materials.
Figure 5: 2D phosphorene for FETs.
Figure 6: 2D silicene FETs.
Figure 7: Future FET technologies.
Figure 8: Operating mechanism of tunnelling FETs.

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Acknowledgements

M.C. acknowledges financial support from US National Science Foundation ECCS 1128335. D.J. would like to acknowledge financial support from the STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA, and by the Office of Naval Research (ONR), the Air Force Office of Scientific Research (AFOSR), and the National Science Foundation (NSF).

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Correspondence to Manish Chhowalla or Debdeep Jena.

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Quantitative description of FET (PDF 326 kb)

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Flowchart for assessing performance of FETs (PDF 170 kb)

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Chhowalla, M., Jena, D. & Zhang, H. Two-dimensional semiconductors for transistors. Nat Rev Mater 1, 16052 (2016). https://doi.org/10.1038/natrevmats.2016.52

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