Introduction

Emerging reconfigurable technologies based on two-dimensional (2D) materials are expected to empower next-generation electronic devices with lower power consumption and higher expressive capability1,2,3,4,5. Different from conventional complementary metal-oxide semiconductor (CMOS) technologies, 2D-materials-based transistors show the dopant-free polarity control that the conduction mechanism reversibly switches between n-type and p-type operation modes under gate-voltage sweeps6,7,8. These transistors are regarded as Schottky junction field-effect transistors (SJFETs), in which the carrier injection is determined by the Schottky barrier (SB) formed at the metal/semiconductor interfaces (MSIs)9,10. However, this ambipolar behavior renders the SJFET hard to be switched off properly11. Especially in downscaling of 2D SJFET, the strong electrostatic control can shrink the off-state SB, resulting in a larger leakage current and a smaller current on/off ratio, which hampers its application towards the large-scale integration and low static power consumption12,13.

Contact engineering as an effective modulation method has been proposed to suppress ambipolarity under gate-voltage sweeps and achieve an ultra-low off-state current in the SJFET14,15,16,17. The ambipolar-to-unipolar conversion of transport polarity control in 2D SJFET has been realized by introducing dual gates under the source and drain, respectively, where the injection and conduction of carriers can be individually modulated4,18. But the multi-gate layout in integrated circuits impeded device scaling due to gate-length limitations. The insertion of an atomically thin insulator layer such as hexagonal boron nitride or the air gap in MSI was also effective in improving the interface quality and suppressing the drain leakage19,20. The tunneling conduction mechanism, however, inevitably decreases the on-state current density. An easier method to build unipolar SJFET with an uncompromised on-/off-state current ratio is to use asymmetric source/drain electrodes with different work functions21,22. However, the strong Fermi-level pinning induced by the metal-induced gap states (MIGs) and trap-induced gap states between deposited metal/2D semiconductor interfaces usually generates an unpredictable SB height and brings the uncertainty to control the unipolarity of SJFETs21.

Emerging layered semimetals/metals provide a state-of-the-art approach for building the MSI to achieve ambipolar-to-unipolar conversion in van der Waals (vdWs) layered SJFETs. The bond-free integration is unaffected by lattice mismatch, or defects induced in metal deposition process to avoid trap states in the MSI7, making the SB height more controllable. Furthermore, semimetals with a near-zero density of states at the Fermi level have been verified to avoid MIGs and achieve the ideal MSIs23. Graphene as a typical Dirac semimetal, whose Fermi energy can be effectively tuned by electrostatic gating has the potential to build the reconfigurable barrier transistor24. Beyond graphene, the family of transition metal dichalcogenide (TMD) also furnishes a rich variety of semimetals, e.g., 1T′-MoTe225,26, 1T′-WTe227,28, 1T′-PtSe229, and 2H-NbSe230. These semimetals possess a broad range of work functions and are expected to create predictable and high-quality all vdWs Schottky junctions31,32.

Here, we reported on a runtime reconfigurable WSe2 SJFET with epitaxially-grown WTe2 and mechanically exfoliated multi-layer graphene (MGr) contacts, in which the WTe2 contact effectively suppressed the carrier injection to realize the ambipolar-to-unipolar polarity conversion controlled by the single bottom gate. Because carrier injection only allowed tunneling from the MGr contact, the WSe2 SJFET shows an alternative carrier polarity between n-type and p-type, by applying positive and negative source-drain voltage Vds, respectively. The SJFET under both p-type and n-type unipolarity conditions suppressed the leakage currents to 2 × 10−10 μA/μm, while the controllable Ids on/off ratios with a maximum of 106 retained. The static power consumption induced by the leakage off-state Ids current was suppressed to 10−5 nW. The SJFET also worked as an electrically gate-tunable Schottky rectifier with a near-unity ideality factor of ~1.0 and a high rectifying ratio of 3×106. The asymmetrically contacted SJFET showed a reconfigurable photovoltaic performance with the open-circuit voltage Voc substantially tuned from 0.29 V to −0.47 V and the self-powered photoresponsivity markedly tuned from 61.7 to −12.7 mA/W. Both the negatively and positively gate-biased asymmetric photodiodes showed high filling factors with a maximum of 0.68, indicating larger shunt resistance and smaller leakage. As a facile design method, the WTe2/MGr contact strategy is also applicable to other 2D materials such as WTe2/MoS2 gate-tunable n-type Schottky diode, to boost 2D reconfigurable SJFETs in applications towards low- static-power-consumption and run-time reversible photovoltaic electronics.

Results and discusssion

The conversion from ambipolarity to reconfigurable unipolarity

The ambipolarity of the SJFET is attributed to the energy level alignments and evolution at both the source and drain Schottky contacts. Figure 1a shows the schematic of the SJFET with intrinsic ambipolar transport polarity, with its band alignment evolution and the corresponding ambipolar transfer curves schematically shown in Fig. 1b. According to the general theory of the Schottky barrier based on 2D semiconductors9, there are two main types of carrier injection mechanisms: (1) thermionic emission (TE) when the gate voltage Vg is smaller than flat band voltage VFB, which is given by Eqs. (1) and (2):

$${I}_{{{{{\rm{thermal}}}}}}\,\approx \,A{T}^{2}{{\exp }}\left(\frac{q{{{{{{\rm{\varphi }}}}}}}_{{{\rm{B}}}}}{{k}_{{{\rm{B}}}}T}\right)={{AT}}^{2}\exp \left(\frac{q\left({{{{{{\rm{\varphi }}}}}}}_{{{{{{\rm{SB}}}}}}-{{{{{\rm{n}}}}}}}+{{{{{{\rm{\psi }}}}}}}_{{{{{{\rm{S}}}}}}}\right)}{{k}_{{{{{{\rm{B}}}}}}}T}\right)$$
(1)
$${q{\psi}}_{{{{{\rm{S}}}}}}\,\approx \,\left | \frac{{V}_{{{{{\rm{g}}}}}}-{V}_{{{{{\rm{FB}}}}}}}{{\gamma}}\right | ,\,{\gamma}\,\approx \,1+\frac{{C}_{{{{{\rm{s}}}}}}+{C}_{{{{{\rm{it}}}}}}}{{C}_{{{{{\rm{ox}}}}}}}$$
(2)

where is the φB barrier height, ψs is the surface potential, γ is the inverse band movement factor and calculated by the semiconductor capacitance CS, the interface trap capacitance Cit, and the oxide capacitance Cox. (2) thermally assisted Fowler–Nordheim tunneling (FNT) and direct tunneling (DT) when the Vg exceeds the VFB, which is given by Eqs. (3) and (4):

$${I}_{{{{{\rm{tunnel}}}}}}=\frac{2{{{{\rm{h}}}}}}{q}{\int }_{q{{\varphi}}_{{{{{\rm{s}}}}}}}^{{{\varphi}}_{{{{{\rm{SB}}}}}-{{{{\rm{n}}}}}}}f(E){M}_{2{{{{\rm{D}}}}}}(E){T}_{{{{{\rm{WBK}}}}}}(E){{{{\rm{d}}}}}E$$
(3)
$${T}_{{{{{\rm{WBK}}}}}}(E)=\exp \left(-\frac{8{\pi}}{3{{{{\rm{h}}}}}}\sqrt{2{m}^{*}{({{\varphi}}_{{{{{\rm{SB}}}}}-{{{{\rm{n}}}}}}-E)}^{3}}\frac{{{{\lambda }}}_{{{{{\rm{SB}}}}}}}{q{{\psi}}_{{{{{\rm{S}}}}}}}\right)$$
(4)

where is the f (E) is the Fermi–Dirac distribution of the contact metal, M2D(E) is the number of 2D conduction modes in the semiconducting channel, and the TWKB (E) is the SB transmission probability, and the λSB is the characteristic length. As shown in Fig. 1b, when a positive Vg > VFB is applied, the ψs increases and the energy-band diagram is bent upwards to enable an electron tunneling current Itunnel from source to drain, which significantly contributes to the on-state current Ion on the n-branch. Reversely, when a negative Vg < VFB is applied, the ψs decreases, and the downward-bent band induced hole injection from the drain through direct tunneling, which contributes to the Ion on the p-branch. By setting Vg at zero, the DT current is suppressed, and only the lower TE current contributes to the off-state current due to the larger width of the contact barrier. Hence, when Vg exceeds the VFB, both n- and p-Ion are dominated by the Itunnel through the narrowed barrier width.

Fig. 1: The transition from ambipolarity to unipolarity behavior of the Schottky junction field-effect transistor (SJFET).
figure 1

a Schematic of global gated SJFET with symmetric drain (D) and source (S) contacts. b Schematic of ambipolar transport behavior and corresponding band structure diagram. Both n- and p-branch on-state currents are attributed to the tunneling current due to the barrier reduction and thinning. TE represents thermionic emission. DT represents directing tunneling. c Offset contact geometry enabling p-type and n-type transport behavior and the corresponding band structure diagram. d Suppression of leakage currents by utilizing WTe2 bottom contacts. The red and blue circles represent the hole and electron, respectively. The arrows represent the carrier injection. Vg and Vds are the gate voltage and drain–source voltage, respectively. Ids is the drain–source current. Vt is the threshold voltage.

Full size image

To achieve the ambipolar-to-unipolar transition, we proposed an offset contact strategy to suppress the carrier injection from the source by utilizing the shielding effect of the bottom electrode to avoid electrostatically ψs shifting (Fig. 1c). Firstly, we designed an SJFET with the MGr offset contacts, as shown in Supplementary Fig. 1a, in which the source and drain were contacted at the bottom and the top surfaces of the WSe2 channel, respectively. Supplementary Fig. 1b–c show the transfer curves of the WSe2 FET at various Vds with the offset contacts. When Vds < 0, the WSe2 transistor showed a p-type transport polarity with an on-state Ids of 0.18 μA/μm. Reversely, the WSe2 transistor showed an n-type polarity when Vds > 0. The output curves at negative and positive Vg also indicated that the back-to-back junctions were asymmetrically modulated, as shown in Supplementary Fig. 1d. However, the carrier injection from the source side was only suppressed slightly, as shown in Supplementary Fig. 1e–g, which induced a higher off-state Ids of 0.4 × 10−2 μA/μm and a lower on/off ratio (~10) for the MGr-contacted WSe2 SJFET. This weak ambipolar-to-unipolar transition was hard to be simply explained by the air-gap-induced barrier widening20. The contact interaction between the WSe2 and the bottom contact also played an important role to repress the leakage current, which will be discussed in Part III. According to our previous report based on the MGr/MoS2/WTe2 vertical junction33, WTe2 possessing an appropriate work function and weak interlayer interaction with WSe2 is expected to enlarge the tunneling width of SB at WTe2/WSe2 interface. Therefore, we can optimize the bottom contact material by utilizing WTe2 to suppress the leakage currents and fulfill the ambipolar-to-unipolar transition by only allowing carrier injection from the top contact side, as shown in Fig. 1d.

Preparation and electrical characterization of WTe2 contacts

To obtain a high-quality WTe2 bottom electrode, we proposed a one-step epitaxial growth method to prepare large-size WTe2. Figure 2a shows the photograph of epitaxially-grown WTe2 in which thicker MoTe2 flakes were synthesized first and worked as growth seeds to provide nucleation sites and reduce the nucleation energy barrier of WTe2. Compared to direct WTe2 growth, the epitaxial growth of WTe2 showed a large-size and high-quality surface and clear W(Mo)Te2 interface, advantageously reducing the unexpected Fermi level pinning and controlling the contact barrier precisely. More information about the sample growth and characterization is in the Methods section and Supplementary Note 1. Figure 2b–d show the Raman intensity mapping indicating the heterostructure properties and excellent uniformity of MoTe2 and epitaxial WTe2. The surface quality of the WTe2 was probed by atomic force microscope (AFM), as shown in Fig. 2e. Both the thin WTe2 at the edge and the thick MoTe2 possessed smooth surfaces, which were expected to work as the vdWs Schottky contact with a clean and desired interface.

Fig. 2: Growth and characterization of WTe2 bottom electrode.
figure 2

a Optical image of the epitaxially grown WTe2. Scale bar: 20 μm. b–d Raman intensity mapping images with the characteristic peaks corresponding to A17, A19 modes of WTe2, and Bg, Ag mode of MoTe2. Scale bar: 20 μm. e Morphology of epitaxially-grown WTe2 measured by AFM. Scale bar: 4 μm. f Potential image of epitaxially-grown WTe2 measured by Kelvin probe force microscopy. Scale bar: 4 μm. g Potential image of Au and CVD-grown WTe2. Scale bar: 2 μm. h I–V curves of W(Mo)Te2 with various thicknesses measured by the 2-terminal method. i I–V curves of W(Mo)Te2 with various thicknesses measured by the 4-terminal method. j 2-terminal resistance (R2T) and 4-terminal resistance (R4T) of W(Mo)Te2 with different thicknesses. The standard deviations were used as error bars. The inset shows the contact resistance 2Rcontact = R2T–R4T versus the thicknesses of W(Mo)Te2.

Full size image

As a promising candidate to build the semimetal-semiconductor junction, the potential and resistance of epitaxially-grown WTe2 were further investigated. Figure 2f shows the surface-potential image of WTe2 measured by Kelvin probe force microscopy (KPFM). The edge WTe2 possessed a higher surface potential compared to the thick MoTe2 region and the difference in potential between MoTe2 and WTe2 was 79 meV. The work function (WF) of WTe2 was ~5.17 eV by using Au film (WFAu = 5.1 eV) as the reference (Fig. 2g). Figure 2h and i show the Id–Vd curves of W(Mo)Te2 with various thicknesses characterized by 2-terminal and 4-terminal methods, respectively. The measurements are detailed in Supplementary Fig. 5. Since the 4-terminal resistance (R4T) eliminated the contact resistance, it was used to assess the intrinsic electrical resistance of the WTe2 (The details were discussed in Supplementary Note 2). The WTe2 with a thickness t of ~5 nm showed the highest resistance of about R4T = 9.41 kΩ. For the sample with thickness between t = 5–20 nm, the resistance decreased to 1.95 kΩ and the bulk sample (t > 20 nm) possessed the lowest conductivity of 0.58 kΩ (Fig. 2i). Compared to the R4T, the 2-terminal resistance (R2T) showed a more pronounced change with thickness, indicating the contact resistance 2Rcontact = R2T–R4T between the transferred Au film and W(Mo)Te2 increased with the decreased thickness, as shown in the inset of Fig. 2j.

Further, the current density (Vds = 0.1 V) of WTe2 devices at different temperatures was measured by the 2-terminal method (Supplementary Figs. 6–7). The current density of WTe2 with a small thickness of ~5 nm was positively correlated with the temperature. As the thickness increased, the WTe2 exhibited a weak temperature dependence. However, the WTe2 with a thickness larger than 20 nm showed a negative temperature coefficient of current density, as shown in Supplementary Fig. 7b–d. This metal-semiconductor transition was consistent with exfoliated W(Mo)Te2 flakes in previous reports34, which may be attributed to contact resistance and the surface absorption of the hydroxyl group in ambient conditions. The transfer curves of WTe2 with varied thicknesses also support this transition (Supplementary Fig. 7e–g). The bulk sample exhibited a constant source-drain current Ids when the gate-voltage Vg swept, but the Ids measured in the thin WTe2 were modulated by gate-voltage steadily, showing a weak p-type characteristic, especially in the low-temperature range.

Carrier injection capability comparison between MGr and WTe2

To compare the carrier injection capability of different contact materials and geometries, we built the WSe2-SJFET using symmetric top and bottom contacts with the exfoliated MGr and epitaxially grown WTe2. All devices were fabricated by the dry-transfer method to avoid the formation of defect-induced states. Figure 3a, b show the schematics and transfer curves of the top-contacted device at various Vds. Compared to the FET with top WTe2 contacts, the FET with MGr top electrodes showed symmetric transfer characteristics with higher currents, indicating the MGr possessed higher carrier injection efficiency for both electrons and holes, which was the reason why the MGr used as the top contact. We also measured the transfer curves of the FET with other bulk or layered metal contacts, but most of these contacts showed an asymmetric carrier injection efficiency and resulted in a stronger p-branch in the Ids–Vg curves, as shown in Supplementary Fig. 8. Figure 3c, d show the transfer curves of the bottom-contacted FET at varied Vds. The FET with MGr bottom contacts still showed a high and symmetric on-state Ids. Reversely, Ion of the WTe2-contacted WSe2 device was only ~10−9 μA/μm at Vds = 1 V, which was six orders of magnitude lower than that of the MGr-contacted FET, the same behavior as shown in the output characteristics (Supplementary Fig. 9b, c). The results suggested that the WTe2 bottom contacts exhibited a lower carrier injection efficiency due to the self-shielding effect of bottom contact14, weak interfacial interaction, and vdWs-gap-induced tunneling barrier at the WTe2/WSe2 interface.

Fig. 3: Carrier injection capability of the bottom MGr and WTe2 contacts.
figure 3

a Schematic and the transfer curves of MGr top-contacted FET. b Schematic and the transfer curves of WTe2 top-contacted FET. c Schematic of and the transfer curves MGr bottom-contacted FET. d Schematic and the transfer curves of WTe2 bottom-contacted FET. e, f Schematic of bottom-contacted WTe2-WSe2 and the network of contact resistances, and the corresponding schematic of the energy-band diagram. Ec, Ev, and Es represent the energies of the conduction band, valence band and Fermi level in 2D semiconductor, respectively. Em is the work function of the contact metal. SB represents the Schottky barrier. g, h Schematic of top-contacted WTe2-WSe2 and network of contact resistances, and the corresponding schematic of the energy-band diagram. i, j Schematic of MGr-WSe2 and network of contact resistances, and the corresponding schematic of energy-band diagram. The dashed line in the energy-band diagram indicates the band evolution induced by Vg. Brown spheres: selenium atoms. Rose red spheres: tellurium atoms. Green and purple spheres: tungsten atoms. Gray spheres: carbon atoms. Regions A-D represent the metal contact, the interface gap, the contacted semiconductor, and the channel semiconductor region, respectively. ρsc is the sheet resistance of the semiconductor overlapped with the contact, rc and re are the specific resistivities of the contact gap and edge, respectively, LC is the contact length.

Full size image

To explain the contact-geometry-induced suppression of carrier injection, we show the schematic of the current flow pathways in a typical MS surface contact geometry in Fig. 3e−i, where the current flow from metal (A) to channel (D) passes through two regions including the vdWs gap at MS interface (B) and the WSe2 overlapped with metal (C). We further reduce the surface contact region of WSe2 FETs into a resistor network under the diffusive approximation, and the contact RC is expressed in the transmission line model35:

$${R}_{{{{{\rm{c}}}}}}=\sqrt{{{\rho}}_{{{{{\rm{sc}}}}}}{r}_{{{{{\rm{c}}}}}}}\coth ({L}_{{{{{\rm{c}}}}}}/\sqrt{{{\rho}}_{{{{{\rm{sc}}}}}}{r}_{{{{{\rm{c}}}}}}})$$
(5)

where ρSC is the sheet resistance of the 2D semiconductor beneath the contact, rc is the specific resistivity of the MS interface, Lc is the contact length, respectively. For the top contact geometry, modulated by the global bottom-gate, ρSC was decreased as the amplitude of Vg increased, which reduced the RC and improved the on-state currents. However, for the bottom contact geometry, ρSC was hardly tuned by the bottom gate due to the shielding effect of the electrode, resulting in a large contact resistance and a poor on-state current density. The shielding effect of the bottom electrode was also verified by simulation using the COMSOL Multiphysics package, as shown in Supplementary Fig. 10, in which both the electric field and carrier density of the WSe2 atop the bottom contact were hardly to be modulated by Vg. Besides, the vdWs gap between the channel and the vertical side wall of the bottom contact (Supplementary Fig. 10b–o also led to the large and nonadjustable contact resistance due to the large interface resistance rc36, which was discussed in the previous report20. The same tendency could be derived from the schematic energy-band diagrams of the MS structures. As shown in Fig. 3h, the width of the n-type (p-type) Schottky barrier was narrowed as the Vg increased (decreased) in the WTe2 top contact geometry. In contrast, it is difficult to be modulated in the WTe2 bottom contact geometry (Fig. 3f).

Apart from the contact geometry, the contact materials were also important. Supplementary Fig. 11 shows the potential difference at the WSe2/WTe2, and WSe2/MGr interfaces measured by KPFM. Compared to the potential difference between WSe2 and MGr, there existed a smaller potential difference of 37 meV between WTe2 and WSe2, indicating that their WFs were horizontally aligned; therefore, WTe2 had a small charge transfer doping to the WSe2 and avoided the ψs shift of the contacted WSe2. Meanwhile, for the MGr bottom contact, the electrical contact was dominated by the edge interface of the MGr electrode (Fig. 3j), which was thinner than that of WTe2 contacts and difficult to suppress the tunneling injecting current. To verify that, the flat-band barrier heights (SHB) of the MGr bottom contact are calculated by 2D thermionic emission mode, as shown in Eq. (6)9:

$${I}_{{{{{\rm{ds}}}}}}=\left[A{A}^{*}{{{{{\rm{T}}}}}}^{1.5}\exp \left(-\frac{q{{\Phi}}_{{{{{\rm{B}}}}}}}{{k}_{{{{{\rm{B}}}}}}T}\right)\right]\left[\exp \left(\frac{q{V}_{{{{{\rm{ds}}}}}}}{{k}_{{{{{\rm{B}}}}}}T}-1\right)\right]$$
(6)

where A is the junction area and A* is the effective Richardson–Boltzmann constant. The obtained ΦB as a function of Vg is shown in Supplementary Fig. 9, which indicated that the Ion of both p- and n-branch was based on the tunneling mechanism due to the gate-thinned barrier.

The few-layered WTe2 also showed a weak interfacial interaction with the orbital overlapping to WSe2, compared to the Au film which possessed a similar WF to WTe2. We measured the potential difference of WSe2 on Au and WTe2 substrate using the WSe2 on SiO2 wafer as the reference (Supplementary Fig. 12). The results showed a positive potential difference (~300 meV) between WSe2 on Au film and the WSe2 on WTe2 flake, indicating an unexpectedly strong doping effect of Au film due to the interfacial state, such as metal-induced gap states (MIGS), defect states, and the interface dipoles37. Meanwhile, we also compared the intensity and shape-variation of the Raman characteristic peaks of WSe2 on Au and WTe2 flake (Supplementary Fig. 13). For out-of-plane vibrational A1g mode affected by the electrostatic environment change, its full width at half maximum (FWHM) was enlarged as WSe2 overlapped on Au film compared that of WSe2 overlapped on WTe2 (Supplementary Fig. 13c–f), indicating the strong charger transfer doping effect on Au film38,39. The detailed comparison is discussed in Supplementary Note 3.

Reconfigurable unipolar WSe2 SJFET with asymmetric contact

To suppress the ambipolar behavior while the high on-state performance retained, we fabricated a WSe2 SJFET with bottom-contacted WTe2 and top-contacted MGr electrode, as the drain and source contacts, respectively, as shown in Fig. 4a. The optical images of the devices are shown in Supplementary Fig. 9a and the thicknesses of the MGr, WSe2, and WTe2 were 13.2 nm, 6.2 nm, and 11 nm, respectively. The transistor characteristics were dominated by both source-drain polarity and control. When Vds was positively biased, as shown in Fig. 4b, the WSe2 SJFET showed an n-type characteristic, and the on-state current (Ion) increased to 6 × 10−3 μA/μm as Vds increased to 1 V. Meanwhile, the off-state current was suppressed to ~10−10 μA/ μm at Vds = 1 V and Vg = −60 V, hence, a maximum on/off ratio higher than 106 was achieved.

Fig. 4: Reconfigurable WSe2 SJFET with asymmetric MGr/WTe2 contacts.
figure 4

a Schematic of asymmetrically contacted WSe2 SJFET. b Pseudo-color transfer plots of the device at Vds > 0 showed the n-type polarity. c Pseudo-color transfer plots of the device at Vds < 0 showed the p-type polarity. The red dash lines indicated the threshold voltage Vt. d Vds-dependent effective field-effect mobility and the Ids on/off ratios. All field-effect mobilities were extracted from the linear regimes. e, f Barrier heights of the device at Vds = 1 V and Vds = −1 V. The Schottky barrier height is extracted under a flat-band gate voltage (VFB) condition, which was responsible for the start of deviations from the linear behavior. g Output characteristics of the device at varied gate voltages. h Gate-dependent rectifying ratios of the device. The gray-green dashed line represents the mean value of the ideality factors. i Comparison of ideality factor n and off-state current of MoS27,21,41,42,43,44,45 and WSe214,46,47,48,49,50 SJFET in previous reports.

Full size image

When Vds was negatively biased shown in Fig. 4c, the WSe2 FET displayed a p-type characteristic with Ion of 1.1 × 10−2 μA/μm at Vds = −1V. Similar to the n-type one, Vt increased as the amplitude of Vds  decreased, but the leakage current still remained to be below 1.9 × 10−9 μA/μm at Vds = 1 V and Vg = −50 V. Note that the threshold voltage (Vt) shifted with increasing amplitude of Vds, because the strong drain electric field penetrated into the channel region and thinned the barrier, resulting in compromised gate-control capability, which was named by the drain-induced barrier lowing (DIBL) effect40. The source-drain current Ids on/off ratio at different Vds was summarized in Fig. 4d, showing that the on/off ratio of p-type SJFET was tuned continuously more than 106 and all off-state currents were suppressed at 2.6 × 10−8 μA/μm. Meanwhile the on-state Ids of SJFET in the offset geometry were not decreased in comparison with that of WSe2 FET with the symmetric top contact geometry, as shown in Supplementary Fig. 14.

The off-state leakage power consumption was calculated by Pstatic = Vds × Ids. When Vds = 1 V, the Pstatic of the n-type FET was 1.8 × 10−5 nW at Vg = −50 V with a high on/off ratio, although the p-type FET shows a higher Pstatic of 2.7 × 10−4 nW at Vg = 50 V. To verify the necessity of the offset contact geometry, we also measured the asymmetric FET in the top contact and bottom geometries, both of which could not simultaneously achieve the ambipolarity to unipolarity conversion (low leakage current) and a high Ids on/off ratio (Supplementary Fig. 15). Meanwhile, we also replaced the bottom electrode with the Au film, as shown in Supplementary Fig. 16. The bottom-Au-contacted FET showed poor reconfigurability, verifying the WTe2 indeed played an important role in the polarity control. In addition, the effective two-terminal field-effect mobility (μeff) for electron and hole on varied Vds were also calculated by Eq. (7):

$${\mu }_{{{{{\rm{eff}}}}}}=\left(\frac{{{{{\rm{d}}}}}{I}_{{{{{\rm{ds}}}}}}}{{{{{\rm{d}}}}}{V}_{{{{{\rm{g}}}}}}}\right)\left(\frac{L}{W{C}_{{{{{\rm{i}}}}}}{V}_{{{{{\rm{ds}}}}}}}\right)$$
(7)

where Vg is the applied back gate voltage and Ci is the capacitance of the SiO2 dielectric layer (~11.5 nF/cm2). Figure 4d shows that the μeff of electron for the WSe2 FET was almost twice the μeff of hole for the device with the MGr contacts. Both μeff of electron and hole were strongly influenced by Vds since the calculated effective μFET were limited by the contact barrier. To qualify the Vds-induced switching of transport polarity, we measured the barrier heights of the asymmetric SJFET at variable temperatures (Supplementary Fig. 17). The ΦB-n and ΦB-p of top-MGr contact were obtained from the slope of a linear fit to ln (Ids/T1.5) as a function of 1/kBT, by employing the 2D thermionic emission Eq. (6). Figure 4e, f show that the ΦB-n at Vds = 1 V was extracted at VFB = 17 V to be 79 meV and the ΦB-p at Vds = −1V was extracted at VFB = −3V to be 142 meV, although the p-branch Ion was slightly higher than the n-branch Ion. The calculated results indicated that both p- and n-Ion were mainly attributed to the tunneling currents, hence the barrier width instead of height determined the on-state current density.

Figure 4g shows the reconfigurable rectifying behavior of the SJFET with different Vg in which the rectifying direction was switched by Vg. The maximum rectifying ratio reached 3×106 in the positive rectifying direction and 2.5 × 105 in the negative rectifying direction, whereas the rectifying ratio of the all-MGr-contacted WSe2 Schottky diode was only about 10 at Vds = ±1 V. To further evaluate the rectifying performance of the gate-tunable WSe2 Schottky junction diode, an ideality factor (n) was estimated at a small forward bias (here is 0.02–0.35 V) by fitting to Schottky diode Eq. (8).

$${I}_{{{{{\rm{ds}}}}}}={I}_{{{{{\rm{s}}}}}}\left[\exp \left(\frac{{V}_{{{{{\rm{ds}}}}}}}{n{V}_{{{{{\rm{T}}}}}}}-1\right)\right]$$
(8)

where Ids, Is, Vds, and VT denote the drain current, reverse leakage current, drain voltage, and thermal voltage, respectively. As the gate voltage swept from positive to negative in Fig. 4h, the ideality factor n derived from the parameters of the fitting equation was nearly fixed on 1 with negligible variation, indicating a near-ideal diode attribute in the reconfiguration process. Figure 4i summarizes the reported ideality factors and off-state current of the 2D SJFET, indicating the high quality of the asymmetric contacted SJFET and the application potential towards lower static power dissipation.

The reconfigurable rectifying operation was based on unpinned energy level at the MGr/WSe2 interface and the strong carrier-injection suppression capability of WTe2. As shown in Supplementary Fig. 18, when Vg > 0 at Vds > 0, the gate-electric field induced strong electron accumulation and reduced the ψs of the MGr-contacted WSe2. Hence the SB width was thinned to promote the electron injection from MGr through the DT (Supplementary Fig. 18b). In contrast, when Vg < 0, the width of barrier at WTe2/WSe2 interface remained constant due to the shielding effect, which reduced the off-state hole current leakage (Supplementary Fig. 18c). Reversed carrier injection process happened at Vds < 0 (Supplementary Fig. 18d–f), only holes were allowed to be injected from the MGr side when Vg < 0. The WTe2 contacting strategy can also be applied to fabricate the reconfigurable MoS2 SJFET (Supplementary Fig. 19). The SJFET with Au/WTe2 contacts showed a gate-tunable rectifying characteristic with rectification ratios ranging from 1 to 105. Compared to similar transport curves of Au/MGr contacted SJFET at Vds = ±1 V (Supplementary Fig. 19d and e), the transport behavior of Au/WTe2 contacted device was determined by the sign of Vds, because the electron injection from WTe2 was inhibited, as shown in Supplementary Fig. 19c.

Gate-tunable photo-response of the SJFET

Because the SJFET is regarded as equivalent to two back-to-back Schottky junctions at the asymmetric contact interfaces, the photo-response was tuned by both the Vds and the Vg. We used two devices to investigate the photo-response and the optical image are shown in Supplementary Fig. 10a, b. The data in Fig. 5a–c were derived from sample 2#. We first investigated the photocurrent Ip and photoresponsivity at positive and negative Ids when Vg = 0 (Supplementary Fig. 20), which showed a nearly linear increase with the laser power intensity. More details of power-dependent photo-response are shown in Supplementary Note 4. More importantly, the SJFET also showed a potential as a self-powered photodetector due to its tunable photovoltaic performance. Supplementary Fig. 20c shows the power-dependent temporal short-circuit current Isc at Vg = 0. The Isc was slightly lower than the photocurrents at the same power density, but the photovoltaic response had a smaller dark current and a lower power consumption since Vds was not required.

Fig. 5: The photovoltaic performance of asymmetric contacted SJFET.
figure 5

a, b Gate-dependent output curves of the device under illumination (635 nm). Dashed lines were measured in the dark. c Gate modulation of the responsivity (Rsc) at Vds = 0 V and open-circuit voltage Voc, respectively. d, e Output electrical powers at Vg > 0 and Vg < 0 as a function of drain-source voltage, respectively. Pin is the incident-light intensity. The dashed line indicates the increasing trend of Voc with Pin. f Output electrical power at Vg > 0 and Vg < 0 as a function of incident-light density. The inset shows Voc vs incident power density. the incident power density. ηPV is the power conversion efficiency. The standard deviations were used as error bars. g, h Fill factor (FF) at Vg > 0 and Vg < 0 as a function of the incident power density. The FF increased with the increasing amplitude of Vg. i Logic inverter based on the gate switchable photovoltaic performance. The white light power intensity was ranged from 0.1 mW/cm2 to 30 mW/cm2.

Full size image

The photovoltaic responses of the WSe2 FET were further tuned by Vg. Figure 5a, b shows the output curves on varying positive and negative Vg under the same laser power series (Pin = 3.5 mW/cm2, and a wavelength of 635 nm). With Vg positively increasing, Isc and open-circuit Voc gradually entered the saturated region. The negative Vg modulated behavior was similar. The gate-tunable Voc and Isc were summarized in Fig. 5c, showing that the Voc was tuned from 0.29 V to −0.47 V and the self-powered responsivity Rsc was tuned from −12.7 mA/W to 61.7 mA/W. Figure 5d, e shows that regardless of the positive and negative gate bias, Isc and output electrical power density showed an exponential increase with light power intensity, and Voc also monotonically increased (Fig. 5f). Hence the power conversion efficiency ηPV calculated by ηPV = Pout/Pphoto was almost fixed at 0.37% at Vg = 60 V and 0.15% at Vg = −60 V, respectively, although the incident power increased by two orders of magnitude. Although the output electrical power density and Voc were effectively modulated through the gate control under varying laser power density, Isc showed a weak gate-tunable capability, in which the corresponding self-powered responsivity reached 30 mA/W at Vg > 10 V and 1 mA/W at Vg < −10 V, respectively. The filling factor (FF) qualifies how closely a photovoltaic device acts as an ideal source. Figure 5g, h show the gate-modulated FF of the SJFET at varying incident power density due to the change of Voc. As the amplitude of Vg increased, the SJFET yielded an increased FF, reaching 0.60 at Vg = −60 V and 0.68 at Vg = 60 V. Supplementary Table 1 shows a photovoltaic performance comparison among the asymmetric contacted WSe2 SJFET and the previously reported photovoltaic devices, which implies the high photovoltaic performance of WSe2 SJFET at both positive and negative Vg. The reversible photovoltaic performance rendered the asymmetric SJFET to work as the self-powered logic inverter at an ambient light level, as shown in Fig. 5i and Supplementary Fig. 20d, with Vg as the input signal and Voc as the output signal. Even at low illuminance level (Pin = 0.1 mW/cm2), the logic inverter still showed the obvious Voc switch from −0.2 V to 0.28 V, which further decreased the static power dissipation in integrated circuits due to null Vds applied on the SJFET.

Conclusions

In conclusion, we proposed a contact-engineered SJFET with the reconfigurable polarity and low leakage current, achieved by employing the asymmetrically vdWs semimetal contacts in which the carriers were only injected from the MGr contact and the injection was suppressed at the epitaxially-grown WTe2 bottom contact. The asymmetrically contacted WSe2 SJFET in the offset geometry showed the conversion between ambipolarity and unipolarity and the alternative carrier polarity was determined by the drain bias. Meanwhile, the leakage currents were effectively suppressed to 2 × 10−9 μA/μm and the device showed a controllable Ids on/off ratio with a maximum of 106. The off-state leakage power consumption was reduced to 10−5 nW (n-type) and 10−4 nW (p-type) at Vds = ± 1 V. Also, the WSe2 SJFET also exhibited a reversible rectifying behavior with a maximum rectifying ratio of 3 × 106 and an ideality factor of 1. Advantageously from the electrically gate-tuned contact barrier, the drain-engineered SJFET exhibited a runtime reversible photovoltaic performance in which the sign of the photo-responsivity was substantially tuned and the Voc was switched markedly between the −0.47 V and 0.29 V. Furthermore, based on the photovoltage-reversible properties of the photodiode, a logic optoelectronic device was designed to realize the switch between positive situation to negative situation by manipulating the gate voltage. This contact engineering strategy is generally applicable to other 2D materials such as the electrically gate-tunable n-type MoS2 Schottky diode. The modulation of carrier injection in 2D materials also provides an alternative route to reduce the logic-circuit complexity and promises innovation for the future applications of computational sensors and optical communications.

Note: during revision of this manuscript, we became aware of a related work20.

Methods

One-step epitaxial growth of WTe2. The molten-salt-assisted thermal chemical vapor deposition (CVD) method was used to synthesize WTe2. A mixture of 20 mg hydrate (NH4)6Mo7O24·4H2O, (NH4)10W12O41·xH2O (Sigma-Aldrich) and sodium cholate (Sigma-Aldrich) in a mass ratio of 5:5:1 and the SiO2 substrate was placed in the middle of the heating zone, with a Te lump placed 1 cm away from the substrate. Throughout the growth process, a carrier gas mixture of H2/Ar at a flow rate of 10/100 sccm was utilized. The temperature of the heating zone gradually increased to 760–860 °C and held for 3–5 min. By using these two mixed hydrates as the precursor, the MoTe2/WTe2 semimetal heterostructures were epitaxially synthesized in a one-step method in which the thicker MoTe2 flakes were synthesized firstly, then the WTe2 epitaxially were grown along the edges of MoTe2. As the reaction time increased, the interspaces of MoTe2 frameworks were covered with the polycrystalline WTe2 to form a continuous MoTe2/WTe2 film, as shown in Supplementary Fig. 2e. More information about the sample growth is detailed in Supplementary Note 1.

Material characterization. AFM (Bruker, Dimension Icon) in the tapping mode TUNA mode were employed to measure the thickness of device, while the contact potentials of the different areas were measured via the Kelvin probe force microscopy. Micro-Raman investigation was performed using HORIBA LabRAM HR Evolution system with 532 nm laser excitation (the laser spot was ∼1 μm). The morphology and chemical composition distribution of WTe2/MoTe2 were analyzed by SEM, and XPS (Thermo Fisher Scientific, K-Alpha+). The crystal structure of 2D flakes was characterized by the TEM (FEI Tecnai F200 systems) operated at 80 kV. The TEM sample was prepared using PMMA-supported wet-transfer method.

Electrical characterization. The SJFET devices were tested in a Cascade probe station under high vacuum conditions. The electrical measurement was performed through the Keithley 4200 semiconductor characterization system. Electrical conductivity measurements were taken from 340 K to 80 K with a cooling rate of 2 K/min. The dwell time at each test temperature was 10 min. The 635 nm lasers were used for light illumination and controlled by the Thorlabs ITC 4001. The power density was 30 mW/cm2. During the measurements, the devices were positioned at the center of the light spot.