A general-purpose framework and continuous miniaturization have been key to the success of CMOS technology. However, the recent explosion in compute requirements across a growing variety of architectures and applications is happening at a time when CMOS technology faces unprecedented scaling and cost challenges. This requires reimagining of the existing paradigm.
This is a preview of subscription content, access via your institution
Access options
Subscribe to this journal
Receive 12 digital issues and online access to articles
$119.00 per year
only $9.92 per issue
Buy this article
- Purchase on Springer Link
- Instant access to full article PDF
Prices may be subject to local taxes which are calculated during checkout
References
Kenyon, C. & Capano, C. Apple silicon performance in scientific computing. 2022 IEEE High Performance Extreme Computing Conference, HPEC 2022 https://doi.org/10.1109/HPEC55821.2022.9926315 (2022).
Lie, S. Cerebras architecture deep dive: first look inside the hardware/software co-design for deep learning. IEEE Micro 43, 18–30 (2023).
Choquette, J. NVIDIA Hopper H100 GPU: scaling performance. IEEE Micro 43, 9–17 (2023).
Hooker, S. The hardware lottery. Preprint at https://doi.org/10.48550/arXiv.2009.06489 (2020).
Acknowledgements
The authors thank Imec’s STCO and DTCO teams for fruitful discussions, and L. Aerts for help in editing this article.
Author information
Authors and Affiliations
Corresponding authors
Ethics declarations
Competing interests
The authors declare no competing interests.
Rights and permissions
About this article
Cite this article
Ryckaert, J., Samavedam, S.B. The CMOS 2.0 revolution. Nat Rev Electr Eng 1, 139–140 (2024). https://doi.org/10.1038/s44287-023-00016-3
Published:
Issue Date:
DOI: https://doi.org/10.1038/s44287-023-00016-3
