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Gallium nitride-based complementary logic integrated circuits

Abstract

Owing to its energy efficiency, silicon complementary metal–oxide–semiconductor (CMOS) technology is the current driving force of the integrated circuit industry. Silicon’s narrow bandgap has led to the advancement of wide-bandgap semiconductor materials, such as gallium nitride (GaN), being favoured in power electronics, radiofrequency power amplifiers and harsh environment applications. However, the development of GaN CMOS logic circuits has proved challenging because of the lack of a suitable strategy for integrating n-channel and p-channel field-effect transistors on a single substrate. Here we report the monolithic integration of enhancement-mode n-channel and p-channel GaN field-effect transistors and the fabrication of GaN-based complementary logic integrated circuits. We construct a family of elementary logic gates—including NOT, NAND, NOR and transmission gates—and show that the inverters exhibit rail-to-rail operation, suppressed static power dissipation, high thermal stability and large noise margins. We also demonstrate latch cells and ring oscillators comprising cascading logic inverters.

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Fig. 1: Monolithically integrated GaN CL inverter.
Fig. 2: Quasi-static electrical characteristics of discrete n-FET and p-FET.
Fig. 3: Characteristics of GaN CL inverters.
Fig. 4: Demonstration of single-stage GaN monolithically integrated CL gates.
Fig. 5: Demonstration of a latch cell with two cross-coupled inverters.
Fig. 6: Demonstration of ring oscillators composed of cascading CL inverters.

Data availability

The data that support the plots within this paper and other findings of this study are available from the corresponding authors upon reasonable request.

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Acknowledgements

This work was supported in part by the Hong Kong Research Impact Fund under grant R6008-18. We acknowledge the support by the Nanosystem Fabrication Facility (NFF), HKUST, for device fabrication. We are grateful to N. Li from the Department of ECE, HKUST, for his assistance in the SEM characterization, and Y. Cai from the Material Characterization and Preparation Facility (MCPF), HKUST, for her assistance in FIB sample preparation and TEM characterization. We also thank M. Hua from the Southern University of Science and Technology and X. Zhang from the Department of ECE, HKUST, for valuable technical discussions.

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Contributions

K.J.C., J.W. and Z.Z. conceived the idea and proposed the technical approach. K.J.C. supervised the project. Z.Z., J.W. and L.Z. designed the layout. Z.Z. and L.Z. designed the process flow with the help of W.S. and J.W. W.S. developed the OPT technique, and developed another critical process technique with Z.Z. and L.Z. Z.Z. and L.Z. conducted the fabrication with the help of W.S., S.Y. and T.C. Z.Z. and L.Z. performed the device characterizations. Z.Z., H.X. and J.S. performed the circuit characterizations. L.Z. and S.F. conducted the material characterizations. Z.Z., W.S. and S.F. processed and analysed the data. T.C. and Z.Z. conducted the technology computer-aided design (TCAD) simulations. Z.Z. and K.J.C. wrote the manuscript. All the authors reviewed and commented on the manuscript.

Corresponding authors

Correspondence to Zheyang Zheng or Kevin J. Chen.

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The authors declare no competing interests.

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Peer review information Nature Electronics thanks Andrei Vescan, Luca Nela and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Extended data

Extended Data Fig. 1 Transistor manufacture.

al, Fabrication process flow of the n-FET/p-FET monolithic integration.

Supplementary information

Supplementary Information

Supplementary Figs. 1–11 and Sections 1–8.

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Zheng, Z., Zhang, L., Song, W. et al. Gallium nitride-based complementary logic integrated circuits. Nat Electron 4, 595–603 (2021). https://doi.org/10.1038/s41928-021-00611-y

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