Skip to main content

Thank you for visiting You are using a browser version with limited support for CSS. To obtain the best experience, we recommend you use a more up to date browser (or turn off compatibility mode in Internet Explorer). In the meantime, to ensure continued support, we are displaying the site without styles and JavaScript.

Gallium nitride-based complementary logic integrated circuits


Owing to its energy efficiency, silicon complementary metal–oxide–semiconductor (CMOS) technology is the current driving force of the integrated circuit industry. Silicon’s narrow bandgap has led to the advancement of wide-bandgap semiconductor materials, such as gallium nitride (GaN), being favoured in power electronics, radiofrequency power amplifiers and harsh environment applications. However, the development of GaN CMOS logic circuits has proved challenging because of the lack of a suitable strategy for integrating n-channel and p-channel field-effect transistors on a single substrate. Here we report the monolithic integration of enhancement-mode n-channel and p-channel GaN field-effect transistors and the fabrication of GaN-based complementary logic integrated circuits. We construct a family of elementary logic gates—including NOT, NAND, NOR and transmission gates—and show that the inverters exhibit rail-to-rail operation, suppressed static power dissipation, high thermal stability and large noise margins. We also demonstrate latch cells and ring oscillators comprising cascading logic inverters.

This is a preview of subscription content

Access options

Buy article

Get time limited or full article access on ReadCube.


All prices are NET prices.

Fig. 1: Monolithically integrated GaN CL inverter.
Fig. 2: Quasi-static electrical characteristics of discrete n-FET and p-FET.
Fig. 3: Characteristics of GaN CL inverters.
Fig. 4: Demonstration of single-stage GaN monolithically integrated CL gates.
Fig. 5: Demonstration of a latch cell with two cross-coupled inverters.
Fig. 6: Demonstration of ring oscillators composed of cascading CL inverters.

Data availability

The data that support the plots within this paper and other findings of this study are available from the corresponding authors upon reasonable request.


  1. Khanna, S. M., Webb, J., Tang, H., Houdayer, A. J. & Carlone, C. 2 MeV proton radiation damage studies of gallium nitride films through low temperature photoluminescence spectroscopy measurements. IEEE Trans. Nucl. Sci. 47, 2322–2328 (2000).

    Article  Google Scholar 

  2. Asif Khan, M., Bhattarai, A., Kuznia, J. N. & Olson, D. T. High electron mobility transistor based on a GaN-AlxGa1–xN heterojunction. Appl. Phys. Lett. 63, 1214 (1993).

    Article  Google Scholar 

  3. Ambacher, O. et al. Two-dimensional electron gases induced by spontaneous and piezoelectric polarization charges in N- and Ga-face AlGaN/GaN heterostructures. J. Appl. Phys. 85, 3222 (1999).

    Article  Google Scholar 

  4. Smorchkova, I. P. et al. Polarization-induced charge and electron mobility in AlGaN/GaN heterostructures grown by plasma-assisted molecular-beam epitaxy. J. Appl. Phys. 86, 4520 (1999).

    Article  Google Scholar 

  5. Mishra, U. K., Shen, L., Kazior, T. E. & Wu, Y. F. GaN-based RF power devices and amplifiers. Proc. IEEE 96, 287–305 (2008).

    Article  Google Scholar 

  6. Chen, K. J. et al. GaN-on-Si power technology: devices and applications. IEEE Trans. Electron Devices 64, 779–795 (2017).

    Article  Google Scholar 

  7. Amano, H. et al. The 2018 GaN power electronics roadmap. J. Phys. D: Appl. Phys. 51, 163001 (2018).

    Article  Google Scholar 

  8. Zhang, N.-Q. et al. High breakdown GaN HEMT with overlapping gate structure. IEEE Electron Device Lett. 21, 421–423 (2000).

    Article  Google Scholar 

  9. Chu, R. et al. 1200-V normally off GaN-on-Si field-effect transistors with low dynamic on-resistance. IEEE Electron Device Lett. 32, 632–634 (2011).

    Article  Google Scholar 

  10. Cai, Y., Zhou, Y., Chen, K. J. & Lau, K. M. High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment. IEEE Electron Device Lett. 26, 435–437 (2005).

    Article  Google Scholar 

  11. Uemoto, Y. et al. Gate injection transistor (GIT)—a normally-off AlGaN/GaN power transistor using conductivity modulation. IEEE Trans. Electron Devices 54, 3393–3399 (2007).

    Article  Google Scholar 

  12. Wu, Y.-F. et al. Performance and robustness of first generation 600-V GaN-on-Si power transistors. In The 1st IEEE Workshop on Wide Bandgap Power Devices and Applications 6–10 (IEEE, 2013).

  13. Kashiwagi, J. et al. Recessed-gate enhancement-mode GaN MOSFETs with a double-insulator gate providing 10-MHz switching operation. IEEE Electron Device Lett. 34, 1109–1111 (2013).

    Article  Google Scholar 

  14. Huang, S., Jiang, Q., Yang, S., Zhou, C. & Chen, K. J. Effective passivation of AlGaN/GaN HEMTs by ALD-grown AlN thin film. IEEE Electron Device Lett. 33, 516–518 (2012).

    Article  Google Scholar 

  15. Yang, S. et al. High-quality interface in Al2O3/GaN/AlGaN/GaN MIS structures with in situ pre-gate plasma nitridation. IEEE Electron Device Lett. 34, 1497–1499 (2013).

    Article  Google Scholar 

  16. Hua, M. et al. Integration of LPCVD-SiNx gate dielectric with recessed-gate E-mode GaN MIS-FETs: toward high performance, high stability and long TDDB lifetime. In 2016 IEEE International Electron Devices Meeting (IEDM) 10.4.1–10.4.4 (IEEE, 2016).

  17. Wong, K.-Y., Chen, W. & Chen, K. J. Wide bandgap GaN smart power chip technology. In Proc. CS MANTECH 1–4 (CSMANTECH, 2009).

  18. Wong, K.-Y., Chen, W. & Chen, K. J. Integrated voltage reference and comparator circuits for GaN smart power chip technology. In 2009 IEEE 21st International Symposium on Power Semiconductor Devices & IC’s (ISPSD) 57–60 (IEEE, 2009).

  19. Tsai, C. et al. Smart GaN platform: performance & challenges. In 2017 IEEE International Electron Devices Meeting (IEDM) 33.1.1–33.1.4 (IEEE, 2017).

  20. Chen, K. J. et al. Planar GaN power integration—the world is flat. In 2020 IEEE International Electron Devices Meeting (IEDM) 27.1.1–27.1.4 (IEEE, 2020).

  21. Kaufmann, M., Lueders, M., Kaya, C. & Wicht, B. 18.2 A monolithic e-mode GaN 15W 400V offline self-supplied hysteretic buck converter with 95.6% efficiency. In 2020 IEEE International Solid-State Circuits Conference (ISSCC) 288–290 (IEEE, 2020).

  22. Kinzer, D. Monolithic GaN power IC technology drives wide bandgap adoption. In 2020 IEEE International Electron Devices Meeting (IEDM) 27.5.1–27.5.4 (IEEE, 2020).

  23. Tang, G. et al. High-speed, high-reliability GaN power device with integrated gate driver. In 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) 76–79 (IEEE, 2018).

  24. Xu, H., Tang, G., Wei, J. & Chen, K. J. Integrated high-speed over-current protection circuit for GaN power transistors. In 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) 275–278 (IEEE, 2019).

  25. Li, X. et al. GaN-on-SOI: monolithically integrated all-GaN ICs for power conversion. In 2019 IEEE International Electron Devices Meeting (IEDM) 4.4.1–4.4.4 (IEEE, 2019).

  26. Rabaey, J. M., Chandrakasan, A. & Nikolic, B. Digital Integrated Circuits: A Design Perspective (Prentice Hall, 2003).

  27. Razavi, B. Design of Analog CMOS Integrated Circuits (Tata McGraw-Hill Education, 2002).

  28. Bader, S. J. et al. Prospects for wide bandgap and ultrawide bandgap CMOS devices. IEEE Trans. Electron Devices 67, 4010–4020 (2020).

    Article  Google Scholar 

  29. Zheng, Z. et al. High ION and ION/IOFF ratio enhancement-mode buried p-channel GaN MOSFETs on p-GaN gate power HEMT platform. IEEE Electron Device Lett. 41, 26–29 (2020).

    Article  Google Scholar 

  30. Zheng, Z. et al. Enhancement-mode GaN p-channel MOSFETs for power integration. In 2020 IEEE 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD) 525–528 (IEEE, 2020).

  31. Ibbetson, J. P. et al. Polarization effects, surface states, and the source of electrons in AlGaN/GaN heterostructure field effect transistors. Appl. Phys. Lett. 77, 250 (2000).

    Article  Google Scholar 

  32. Hwang, I. et al. 1.6kV, 2.9 mΩ cm2 normally-off p-GaN HEMT device. In 2012 IEEE 24th International Symposium on Power Semiconductor Devices and ICs (ISPSD) 41–44 (IEEE, 2012).

  33. Hwang, I. et al. p-GaN gate HEMTs with tungsten gate metal for high threshold voltage and low gate current. IEEE Electron Device Lett. 34, 202–204 (2013).

    Article  Google Scholar 

  34. Zimmermann, T. et al. P-channel InGaN-HFET structure based on polarization doping. IEEE Electron Device Lett. 25, 450–452 (2004).

    Article  Google Scholar 

  35. Hahn, H. et al. p-channel enhancement and depletion mode GaN-based HFETs with quaternary backbarriers. IEEE Trans. Electron Devices 60, 3005–3011 (2013).

    Article  Google Scholar 

  36. Li, G. et al. Polarization-induced GaN-on-insulator E/D mode p-channel heterostructure FETs. IEEE Electron Device Lett. 34, 852–854 (2013).

    Article  Google Scholar 

  37. Reuters, B. et al. Fabrication of p-channel heterostructure field effect transistors with polarization-induced two-dimensional hole gases at metal–polar GaN/AlInGaN interfaces. J. Phys. D: Appl. Phys. 47, 175103 (2014).

    Article  Google Scholar 

  38. Nakajima, A. et al. One-chip operation of GaN-based P-channel and N-channel heterojunction field effect transistors. In 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC’s (ISPSD) 241–244 (IEEE, 2014).

  39. Chu, R., Cao, Y., Chen, M., Li, R. & Zehnder, D. An experimental demonstration of GaN CMOS technology. IEEE Electron Device Lett. 37, 269–271 (2016).

    Article  Google Scholar 

  40. Bader, S. J. et al. Gate-recessed e-mode p-channel HFET with high on-current based on GaN/AlN 2D hole gas. IEEE Electron Device Lett. 39, 1848–1851 (2018).

    Article  Google Scholar 

  41. Chowdhury, N. et al. p-channel GaN transistor based on p-GaN/AlGaN/GaN on Si. IEEE Electron Device Lett. 40, 1036–1039 (2019).

    Article  Google Scholar 

  42. Bader, S. J. et al. Wurtzite phonons and the mobility of a GaN/AlN 2D hole gas. Appl. Phys. Lett. 114, 253501 (2019).

    Article  Google Scholar 

  43. Nainani, A., Bennett, B. R., Brad Boos, J., Ancona, M. G. & Saraswat, K. C. Enhancing hole mobility in III-V semiconductors. J. Appl. Phys. 111, 103706 (2012).

    Article  Google Scholar 

  44. Poncé, S., Jena, D. & Giustino, F. Hole mobility of strained GaN from first principles. Phys. Rev. B 100, 085204 (2019).

    Article  Google Scholar 

  45. Zheng, Z. et al. Monolithically integrated GaN ring oscillator based on high-performance complementary logic inverters. IEEE Electron Device Lett. 42, 26–29 (2021).

    Article  Google Scholar 

  46. Wright, A. F. Substitutional and interstitial oxygen in wurtzite GaN. J. Appl. Phys. 98, 103531 (2005).

    Article  Google Scholar 

  47. Xu, H. et al. Incorporating the dynamic threshold voltage into the SPICE model of Schottky-type p-GaN gate power HEMTs. IEEE Trans. Power Electron. 36, 5904–5914 (2021).

    Article  Google Scholar 

  48. Zhang, L. et al. p-GaN gate HEMT with surface reinforcement for enhanced gate reliability. IEEE Electron Device Lett. 42, 22–25 (2021).

    Article  Google Scholar 

  49. Francis, P., Terao, A., Gentinne, B., Flandre, D. & Colinge, J.-P. SOI technology for high-temperature applications. In 1992 International Technical Digest on Electron Devices Meeting 353–356 (IEEE, 1992).

  50. Grella, K., Dreiner, S., Vogt, H. & Paschen, U. Reliability of CMOS on silicon-on-insulator for use at 250 °C. IEEE Trans. Device Mater. Rel. 14, 21–29 (2014).

    Article  Google Scholar 

  51. Amor, S. et al. Reliable characteristics and stabilization of on-membrane SOI MOSFET-based components heated up to 335 °C. Semicond. Sci. Technol. 32, 014001 (2017).

    Article  Google Scholar 

  52. Rahman, A. et al. High-temperature SiC CMOS comparator and op-amp for protection circuits in voltage regulators and switch-mode converters. IEEE Trans. Emerg. Sel. Topics Power Electron. 4, 935–945 (2016).

    Article  Google Scholar 

  53. Albrecht, M., Erlbacher, T., Bauer, A. & Frey, L. Improving 5V digital 4H-SiC CMOS ICs for operating at 400 °C using PMOS channel implantation. Mater. Sci. Forum 963, 827–831 (2019).

    Article  Google Scholar 

  54. Murphree, R. C. et al. A SiC CMOS linear voltage regulator for high-temperature applications. IEEE Trans. Power Electron. 35, 913–923 (2020).

    Article  Google Scholar 

  55. Tang, G. et al. Digital integrated circuits on an e-mode GaN power HEMT platform. IEEE Electron Device Lett. 38, 1282–1285 (2017).

    Article  Google Scholar 

Download references


This work was supported in part by the Hong Kong Research Impact Fund under grant R6008-18. We acknowledge the support by the Nanosystem Fabrication Facility (NFF), HKUST, for device fabrication. We are grateful to N. Li from the Department of ECE, HKUST, for his assistance in the SEM characterization, and Y. Cai from the Material Characterization and Preparation Facility (MCPF), HKUST, for her assistance in FIB sample preparation and TEM characterization. We also thank M. Hua from the Southern University of Science and Technology and X. Zhang from the Department of ECE, HKUST, for valuable technical discussions.

Author information

Authors and Affiliations



K.J.C., J.W. and Z.Z. conceived the idea and proposed the technical approach. K.J.C. supervised the project. Z.Z., J.W. and L.Z. designed the layout. Z.Z. and L.Z. designed the process flow with the help of W.S. and J.W. W.S. developed the OPT technique, and developed another critical process technique with Z.Z. and L.Z. Z.Z. and L.Z. conducted the fabrication with the help of W.S., S.Y. and T.C. Z.Z. and L.Z. performed the device characterizations. Z.Z., H.X. and J.S. performed the circuit characterizations. L.Z. and S.F. conducted the material characterizations. Z.Z., W.S. and S.F. processed and analysed the data. T.C. and Z.Z. conducted the technology computer-aided design (TCAD) simulations. Z.Z. and K.J.C. wrote the manuscript. All the authors reviewed and commented on the manuscript.

Corresponding authors

Correspondence to Zheyang Zheng or Kevin J. Chen.

Ethics declarations

Competing interests

The authors declare no competing interests.

Additional information

Peer review information Nature Electronics thanks Andrei Vescan, Luca Nela and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Extended data

Extended Data Fig. 1 Transistor manufacture.

al, Fabrication process flow of the n-FET/p-FET monolithic integration.

Supplementary information

Supplementary Information

Supplementary Figs. 1–11 and Sections 1–8.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Zheng, Z., Zhang, L., Song, W. et al. Gallium nitride-based complementary logic integrated circuits. Nat Electron 4, 595–603 (2021).

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI:


Quick links

Nature Briefing

Sign up for the Nature Briefing newsletter — what matters in science, free to your inbox daily.

Get the most important science stories of the day, free in your inbox. Sign up for Nature Briefing