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Power-efficient combinatorial optimization using intrinsic noise in memristor Hopfield neural networks

Abstract

To tackle important combinatorial optimization problems, a variety of annealing-inspired computing accelerators, based on several different technology platforms, have been proposed, including quantum-, optical- and electronics-based approaches. However, to be of use in industrial applications, further improvements in speed and energy efficiency are necessary. Here, we report a memristor-based annealing system that uses an energy-efficient neuromorphic architecture based on a Hopfield neural network. Our analogue–digital computing approach creates an optimization solver in which massively parallel operations are performed in a dense crossbar array that can inject the needed computational noise through the analogue array and device errors, amplified or dampened by using a novel feedback algorithm. We experimentally show that the approach can solve non-deterministic polynomial-time (NP)-hard max-cut problems by harnessing the intrinsic hardware noise. We also use experimentally grounded simulations to explore scalability with problem size, which suggest that our memristor-based approach can offer a solution throughput over four orders of magnitude higher per power consumption relative to current quantum, optical and fully digital approaches.

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Fig. 1: Overview of the mem-HNN, experimental noise measurements and the max-cut problem.
Fig. 2: Utility of noise in HNNs to obtain better solutions, illustrated for 60-node instances of dense max-cut problems.
Fig. 3: Experimental implementation of the mem-HNN.
Fig. 4: Experimental data from the mem-HNN.
Fig. 5: Circuit and array simulations of the mem-HNN.
Fig. 6: Simulations of the mem-HNN solving dense instances of the max-cut problem with varying graph sizes.

Data availability

The data supporting plots within this paper and other findings of this study are available from the corresponding author upon reasonable request.

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Acknowledgements

We are grateful to S. Mandrà for performing the CPU simulations used in Table 1 and early review of the article. We acknowledge discussions with H. Katzgraber, P. L. McMahon, E. Rothberg, K. Roenigk, C. Santos, R. Slusher and J. Weinschenk. This research was based upon work supported by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), via contract number 2017-17013000002.

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F.C., S.K., T.V.V., C.L. and J.P.S. performed the simulations. T.V.V., S.K., R.L., Z.L., M.F. and J.P.S. contributed to performance benchmarking. S.K. and J.P.S. performed the experiments. X.S., C.L., Q.X., J.J.Y. and J.P.S. contributed to the chip fabrication and experimental system development. All authors supported analysis of the results and commented on the article.

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Correspondence to John Paul Strachan.

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Supplementary Figs. 1–15, Supplementary Discussion sections 1–10

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Cai, F., Kumar, S., Van Vaerenbergh, T. et al. Power-efficient combinatorial optimization using intrinsic noise in memristor Hopfield neural networks. Nat Electron 3, 409–418 (2020). https://doi.org/10.1038/s41928-020-0436-6

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