A hybrid memristor–CMOS chip for AI

An integrated co-processor chip based on a memristor crossbar array and complementary metal–oxide–semiconductor (CMOS) control circuitry can be used to implement neuromorphic and machine learning algorithms.

Access optionsAccess options

Rent or Buy article

Get time limited or full article access on ReadCube.


All prices are NET prices.

Fig. 1: PIEM and its applications.


  1. 1.

    Yakopcic, C., Alom, M. Z. & Taha, T. M. In 2016 Int. Joint Conf. Neural Networks (IJCNN) 963–970 (IEEE, 2016).

  2. 2.

    Li, C. et al. Nat. Mach. Intell. 1, 49–57 (2019).

  3. 3.

    Rathi, N., Panda, P. & Roy, K. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 38, 668–677 (2019).

  4. 4.

    Krestinskaya, O., Dolzhikova, I. & James, A. P. IEEE Trans. Emerg. Top. Comput. Intell. 2, 380–395 (2018).

  5. 5.

    Buchanan, B., Zheng, L. & Strachan, J. P. Multiply-accumulate circuits. US patent 15/282,021 (2018).

  6. 6.

    Wang, F. Z., Li, L., Shi, L., Wu, H. & Chua, L. O. J. Appl. Phys. 125, 054504 (2019).

  7. 7.

    Cai, F. et al. Nat. Electron. (2019).

Download references

Author information

Correspondence to Alex Pappachen James.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark