An integrated co-processor chip based on a memristor crossbar array and complementary metal–oxide–semiconductor (CMOS) control circuitry can be used to implement neuromorphic and machine learning algorithms.
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References
Yakopcic, C., Alom, M. Z. & Taha, T. M. In 2016 Int. Joint Conf. Neural Networks (IJCNN) 963–970 (IEEE, 2016).
Li, C. et al. Nat. Mach. Intell. 1, 49–57 (2019).
Rathi, N., Panda, P. & Roy, K. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 38, 668–677 (2019).
Krestinskaya, O., Dolzhikova, I. & James, A. P. IEEE Trans. Emerg. Top. Comput. Intell. 2, 380–395 (2018).
Buchanan, B., Zheng, L. & Strachan, J. P. Multiply-accumulate circuits. US patent 15/282,021 (2018).
Wang, F. Z., Li, L., Shi, L., Wu, H. & Chua, L. O. J. Appl. Phys. 125, 054504 (2019).
Cai, F. et al. Nat. Electron. https://doi.org/10.1038/s41928-019-0270-x (2019).
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James, A.P. A hybrid memristor–CMOS chip for AI. Nat Electron 2, 268–269 (2019). https://doi.org/10.1038/s41928-019-0274-6
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DOI: https://doi.org/10.1038/s41928-019-0274-6
