The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated.
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The data that support the plots within this paper and other findings of this study are available from the corresponding author on reasonable request.
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This work was supported by the Samsung Research Funding & Incubation Center of Samsung Electronics under project number SRFC-TA1703-07 and by the U-K Brand Research Fund (1.180037.01) of UNIST (Ulsan National Institute of Science & Technology). The authors are grateful to foundry support for 130-nm and 90-nm CMOS technology processes.
The authors declare no competing interests.
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Jeong, J.W., Choi, YE., Kim, WS. et al. Tunnelling-based ternary metal–oxide–semiconductor technology. Nat Electron 2, 307–312 (2019). https://doi.org/10.1038/s41928-019-0272-8
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