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Metrology for the next generation of semiconductor devices

A Publisher Correction to this article was published on 09 November 2018

This article has been updated


The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate sizes and functionality of these new devices will be affected by fundamental and engineering limits such as heat dissipation, carrier mobility and fault tolerance thresholds. At present, it is unclear which are the best measurement methods needed to evaluate the nanometre-scale features of such devices and how the fundamental limits will affect the required metrology. Here, we review state-of-the-art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches. We describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements. We also discuss potentially powerful emerging technologies and highlight measurement problems that at present have no obvious solution.

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Fig. 1: Proposed advanced integrated circuit devices.
Fig. 2: Advanced CD-SEM imaging.
Fig. 3: CD-SAXS operations and feature shape models.
Fig. 4: Principles of optical scatterometry with future challenges.
Fig. 5: Combined TEM and AFM measurements.

Change history

  • 09 November 2018

    In the version of this Review Article originally published, the labelling of the reflected beam in Fig. 4a was incorrect. This has now been corrected in the Review Article.


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We thank W. Thompson, T. Vorburger and R. Silver for discussions and comments. We thank M.-A. Henn for assistance with Fig. 4d.

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All authors contributed to project planning, discussions and manuscript writing at all stages.

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Correspondence to N. G. Orji.

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Orji, N.G., Badaroglu, M., Barnes, B.M. et al. Metrology for the next generation of semiconductor devices. Nat Electron 1, 532–547 (2018).

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