Introduction

Brain-inspired spiking neural networks (SNNs) have emerged as a promising platform for neuromorphic hardware due to their remarkable energy efficiency1,2,3. In SNNs, numerous spiking neurons act as the basic information processing unit of SNNs and transfer signals between synapses. Therefore, spiking neurons with highly compact and energy efficiency are crucial to implement SNNs in hardware. In addition, to enhance the performance of SNNs, several spike-based coding techniques and architectures have implemented biomimetic functions at the neuron level. Inhibition can prevent overfitting of neural networks by suppressing the firing rates of highly activated neurons. This helps the network generalize better to new inputs4,5,6. Another essential function, namely the tunable threshold, can induce sparse activity in SNNs by emulating the brain stimulus activation. This enables dynamic modulation of neural coding precision, potentially saving significant energy by selectively increasing firing rates only at specific times and locations as required7,8,9. In addition, this function provides robust immunity against artificial neurons with threshold deviations, ensuring the homeostasis10,11,12.

The complex neuronal behavior has been emulated through CMOS-based circuits, which typically consist of numerous transistors and capacitors, requiring a large footprint area and power consumptions13,14,15,16. To overcome these problems, spiking neurons with simple structures have been reported by applying various silicon17,18,19,20,21,22,23,24,25 and non-silicon devices26,27,28,29. PD-SOI MOSFET based neurons provided a means of incorporating integration and threshold triggering operation using the floating body effect without a capacitor19,20,21,22. However, these neurons require external circuit for signal conversion and reset process, which results in large power consumption30. Recently, the single MOSFET neuron devices have been reported that can realize neuronal behavior without both capacitors and external circuitry. However, these single-device neurons consume large power and have small internal capacitance, limiting their ability to integrate large amounts of synaptic signals23,24,25. Non-silicon devices such as memristors and ferroelectric field effect transistor (FeFET) neurons have also been reported due to their steep switching characteristics and scalable structures. However, these neurons have difficulties in controlling their properties consistently in large-area fabrication. Moreover, the resistance change according to the constant voltage pattern is non-linear, which can make practical application difficult26,27,28,29. In conclusion, these reported spiking neurons still operate with large energy consumption for periodic neural oscillations incorporating biomimetic functions.

In this work, we proposed a novel spiking neuron using silicon–germanium (SiGe) based heterojunction bipolar transistors (HBTs) for low energy applications and implementation of biomimetic functions. Our simple spiking neuron consists of four components (2 HBTs, 1 resistor, and 1 capacitor) to realize the periodic integrate-and-fire (IF) behavior without external reset circuit. The latch-up voltage, voltage width and current gain were investigated according to germanium content of p-base region. The hetero-bandgap structure of HBT amplifies the positive feedback gain of hysteresis in the low voltage range through improved hole storage capability and impact-ionization coefficient. This hysteresis characteristic enables integration, threshold triggering, and self-reset processes to run entirely within a low voltage range, resulting in low spiking energy consumption. The hysteresis properties of HBT were utilized to analyze neuronal function for various synaptic inputs. The inhibition of multiple strengths was demonstrated though the control of firing latency achieved by modulation of inhibitory signals. Furthermore, the spiking frequency was tuned by controlling the voltage width of hysteresis of HBTs.

Methods

Device structure and simulation

Figure 1a shows a schematic of a silicon–germanium (SiGe) based heterojunction bipolar transistor (HBT) simulated using the Sentaurus TCAD tool31. The HBT features a laterally formed silicon nanowire structure with physical n+-p-n+ layers, where the gated p-layer is made of SiGe. The n+ anode and cathode were heavily doped with 1020 cm–3. The p-base was doped with 5 × 1017 cm–3, in consideration of impact ionization effect to ensure sufficient supply of holes. The channel length (Lch) was determined to be 100 nm considering the carrier recombination. A heterogeneous bandgap material, Si0.6Ge0.4 was utilized in the p-base to form hysteresis with high current margin in the low voltage range. The channel area (Wch2) was set to 40 × 40 nm2 considering the critical thickness to enable deposition without defects caused by lattice mismatch32,33,34,35.

Figure 1
figure 1

Schematic of (a) lateral nanowire-based heterojunction bipolar transistor (HBT) and (b) diagram of spiking neuron with dual HBTs. (c) Calibration results fitting on experimental data of the fabricated biristor.

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Figure 1b illustrates a simple configuration of a spiking neuron designed using TCAD mixed-mode simulations. A membrane capacitor (CMEM = 4.7 pF) was used for the integration of synaptic current signals (Isyn). Dual HBTs were connected in parallel with the membrane capacitor as a threshold trigger for spike firing and self-reset process. The output resistor (Rout = 20 kΩ) was employed in series with the HBT2 to generate the output voltage (Vout).

Figure 1c shows the calibration results of the electrical hysteresis between the simulated and measured data of the biristor to ensure the reliability of our simulation. The physics was adjusted using experimental data obtained from fabricated devices36,37. Fermi–Dirac distribution and drift–diffusion transport models were used, and the Philips unified mobility model is applied to account for carrier-impurity and carrier-carrier scattering. High-field saturation and doping-dependent mobility models were used, and the Oldslotboom bandgap narrowing model was used to describe the high silicon concentration region. An avalanche generation model was applied to calculate carriers generated by the impact-ionization effect. The doping-dependent Shockley–Read–Hall (SRH) and Auger recombination models were adopted to calculate the recombination rate at the junction surface. A Si-SiGe surface SRH recombination model was also added to consider defects at junctions and interfaces.

Device characteristics

Figure 2a shows the anode current–voltage (IA-VA) hysteresis characteristics of the HBT under quasi-static conditions when the gate voltage (VG) is grounded. This hysteresis curve can be seen forming in the low voltage region compared to the typical floating body memory device shown in Fig. 1c. One of the main reasons is that the narrow bandgap of the p-base increases the impact ionization coefficient and the valence band offset (ΔEv) suppresses the diffusion of stored holes. A detailed analysis of this will be illustrated in Fig. 2d following the description of the basic state transition mechanism in Fig. 2b,c. Figure 2b shows energy band of the HBT at the latch-up voltage of 0.59 V (VLU), where the latch-up phenomenon begins. Here, electrons from the cathode are injected into the p-base by the applied VA. These electrons cause impact ionization in the high electric field of the anode-base junction, resulting in the generation of electron–hole pairs. As a result, the potential barrier is lowered by the excess holes stored in the p-base. As the potential barrier is lowered, more electrons can be injected into the p-base. This series of processes activates positive feedback, which eventually results in abrupt switching of the HBT from the off-state to the on-state as shown in Fig. 2c. As VA decreases, the on-state is maintained until the latch-down voltage of 0.3 V (VLD), where the HBT rapidly transitions back to the off-state. This is because when VA is above VLD, the impact ionization rate is large enough to maintain a positive feedback loop. Therefore, a counterclockwise hysteresis is formed with a voltage width (ΔVw = VLU-VLD) of 0.29 V.

Figure 2
figure 2

Heterojunction bipolar transistor (HBT) (a) IA-VA hysteresis at VG = 0 mV. (b) Energy band of HBT at VA = 0.59 V, where the latch-up phenomenon begins (c) Energy band of HBT at VA = 0.6 V, where the latch-up phenomenon completes (d) VLU and ΔVw as a function of the germanium content (x). (e) On-state current at VLD versus the x. (f) IA-VA hysteresis at VG = –100 mV, 0 mV and 100 mV.

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It is noteworthy that the hysteresis of the HBT exhibits a high current margin of ~ 16 μA at the low VLU of 0.59 V. This high current margin in the low voltage region is attributed to the heterogeneous bandgap structure of HBT. To investigate the effect of the low bandgap material in the p-base, the electrical characteristics in hysteresis curve were extracted according to germanium content (x in Si1-xGex) of the p-base (Fig. 2d,e). The analysis range of the x was set to within 0.4, which can form a dislocation-free layer, considering the Wch of HBT. The high current margin in the low voltage region can be explained by amplified IA through the increased multiplication factor (M) and current gain (β) values as follows37,38,39:

$$I_{A} = \frac{\beta \cdot M}{{1 - \beta \cdot (M - 1)}}I_{B}$$
(1)

The M is associated with the impact ionization coefficient that supplies excess holes. Additionally, the β is related to the storage capability of excess holes in the p-base. As shown on the left axis of Fig. 2d, as the x increases from 0.0 to 0.4, the VLU decreases from 0.74 to 0.59 V. This is attributed to the increased value of the M and β. As the x increases, the bandgap of the p-base narrows and M becomes larger. Furthermore, the increased ΔEv at the base-cathode junction suppresses the hole diffusion current and increases the value of β40. Despite the decrease in VLU, ΔVw increases from 0 to 0.29 V, as shown on the right axis of Fig. 2d. This is because our device operates in the low-voltage region, so the effect of β is larger than that of M, which is greatly amplified at large voltages. Specifically, an increase in the M and β both reduces the voltage range of hysteresis, but the difference is that the M contributes significantly to the reduction of VLU, while the β contributes substantially to the reduction of VLD. Therefore, the decrease in VLD is greater than that of VLU, resulting in an increase in the ΔVw.

Figure 2e shows the on-current in VLD as a function of the x. When the x increases, the on-current of the VLD is amplified to 10 μA, approximately four orders higher than the value of homogeneous bandgap bipolar transistor. This enhancement is due to the increased positive feedback gain, resulting from the improved value of M and β. The high current margin of the HBT is essential to reliably reset the proposed spiking neuron circuit. Because the self-reset process can be completed as the HBT switches rapidly back to the off-state from the on-state, the HBT in on-state must discharge the membrane capacitor faster than the charging current signal until the membrane voltage reaches VLD. Therefore, as can be seen from the simulation results in Fig. 2d, e, the hysteresis with high current margin in the HBT is formed in low voltage range. As a result, the HBT with this hysteresis ensures the energy-efficient IF operation without the need for external reset circuits.

Figure 2f shows the IA-VA hysteresis characteristics of the HBT when the VG is − 100 mV, 0 mV and 100 mV. The VLU decreases from 0.685 to 0.528 V as the VG increases from − 100 mV to 100 mV. A larger VG reduces the potential barrier, triggering positive feedback at lower voltage. On the other hands, after latch-up, the stored holes in the p-base minimize the effect of VG on the potential barrier, so VLD maintains nearly constant. This tunable VLU modulates the spiking characteristics by adjusting the threshold voltage (Vth) of membrane in IF operation.

Operation of HBT based spiking neuron

Figure 3a shows the flow diagram of the integrate-and-fire (IF) operation. One cycle of IF behavior consists of three steps: integrate, fire, and reset. The Isyn signal is input to the node where HBT1,2 and the membrane capacitor are connected in parallel. During the integrate-step, the Isyn signal charges the membrane capacitor, increasing the VMEM. This increase in VMEM corresponds to an excitatory post-synaptic potential (EPSP) in biological terms, which increases the firing probability for post-synaptic neurons. The fire-step occurs after the VMEM reaches the VLU, where HBT1,2 are converted from the off-state to the on-state. The reduced resistance of HBT2 leads to an increase in the voltage across the output resistor. This sharp increase in Vout indicates that the spike is firing. Simultaneously, Isyn flows through HBT1,2 without charging the membrane capacitor. The membrane capacitor discharges with the same flow as Isyn, reducing VMEM. The final reset step is the process where the spike is fully formed and the fire-state transitions back to the initial integrate-state. As the Vout increases, the potential difference (i.e. VMEM–Vout) across HBT2 decreases, which causes the HBT2 to switch to off-state. This causes Vout to drop to 0 V and ultimately resulting in the formation of the spike. To achieve periodic IF behavior, both HBT1 and HBT2 must be returned to the off-state, which corresponds to the initial integrate-state. HBT1 discharges the membrane capacitor, reducing VMEM to VLD, which leads to HBT1 converting itself to off-state.

Figure 3
figure 3

(a) Flowchart of integrate-and-fire (IF) operation consisting of three steps: integrate, fire, and reset. (b) Periodic IF behavior under excitatory condition (VG1 = VG2). (c) Anode current of HBT1,2 corresponding to Fig. 3b.

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Figure 3b shows the periodic IF behavior implemented in our spiking neuron from 20 to 30 μs. The Isyn pulse is 5 μA with the pulse duration (Tpulse) of 50 ns and the interval time (Tint) of 1 μs. When the time was 20 μs, the VMEM has reached to 0.68 V due to temporal charging of the membrane capacitor by Isyn pulses. At the VMEM of 0.68 V, the decrease in resistance of HBT2 causes Vout to rapidly increase to 0.245 V, namely firing of spike. After Vout reaches 0.245 V, it begins to decrease corresponding to the decrease of VMEM. The VMEM increases periodically from 0.29 V to 0.68 V when both HBT1,2 maintain off-state. As shown in Fig. 3c, in the process where Vout rises and then falls to 0 V (i.e., spike generation), HBT1 maintains on-state for 50 ns even after HBT2 transitions back to off-state. Thanks to the large positive feedback gain that can be induced even with small VLU, HBT1 ensures stable self-reset in the low voltage range. In addition, HBT1,2 remain on-state for a short period of time due to their steep-switching characteristics thereby reducing the duration for spike-generation. Accordingly, the hysteresis of the HBT allows our spiking neuron to realize high spiking frequency with low-power consumption.

Figure 4a shows the spike response for different Isyn values of 5 μA and 10 μA when Tpulse is 50 ns and Tint is 1 μs. As Isyn increases from 5 μA to 10 μA, the spiking frequency (fs) increases. This is because a larger Isyn can charge the membrane capacitor faster, which in turn reduces the time required for VMEM to reach the Vth. As shown in black line of Fig. 4b, fs increases linearly from 58.8 to 245.7 kHz with corresponding to an increment of Isyn values from 2 to 10 μA. In addition, the impact of Tint on fs is investigated. When Tint increases from 1 to 2 μs, fs decreases by half. The larger the Tint, the less frequently the membrane capacitor is charged by Isyn pulse, increasing the integration time.

Figure 4
figure 4

(a) Spike response in time domain for synaptic current (Isyn) of 5 μA and 10 μA. (b) Spiking frequency (fs) as a function of amplitude of synaptic current (Isyn) and interval time (Tint).

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Multi-strength neuronal inhibitory function can be implemented in the proposed spiking neuron. This function can be induced by applying consecutive inhibitory signals to the gate of HBT1. Figure 5a shows IA-VA hysteresis characteristics of HBT1 under inhibitory signal of VG1 = 0.5 V and 0.7 V. These inhibitory signals increase the off-current of HBT1, resulting in faster discharge of the membrane capacitor. Consequently, the VMEM decreases, corresponding to an inhibitory post-synaptic potential (IPSP) of biological neuron. Figure 5b,c depict the spiking responses resulting from the temporal accumulation of inhibitory and excitatory signals. As shown in Fig. 5b, when an inhibitory signal of 0.5 V is applied, the IPSP suppresses spike firing for 13.6 μs by delaying the VMEM from reaching its threshold. Figure 5c shows the intensive neuronal inhibition achieved by the strong inhibitory signal of 0.7 V. This inhibitory signal further accelerates the discharge of the membrane capacitor with a larger off-current of HBT1, delaying spike firing for 18.9 μs.

Figure 5
figure 5

(a) IA-VA hysteresis characteristics of HBT1 under inhibitory signal of VG1 = 0.5 V and 0.7 V. Neuronal inhibition according to the (b) weak inhibitory signals (c) strong inhibitory signals.

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Figure 6a shows the spike response for VG values of 0 mV and 100 mV. When the VG increases from 0 to 100 mV, the integration time shortens as Vth decreases from 0.665 to 0.56 V, increasing the number of spikes from 5 to 8 over 40 μs. Additionally, the reduction of Vth decreases the energy consumed when generating a spike. As shown in Fig. 6b, the fs increases from 95 to 192 kHz as VG increases from −100 to 100 mV. On the other hand, the energy consumed per spike decreases linearly from 1.37 pJ to 0.53 pJ. Therefore, the spiking properties such as fs and energy per spike can be modulated with respect to VG. These tunable characteristics enable spiking neurons to selectively respond to a specific range of inputs, enhancing the energy efficiency and sensitivity at the neuron level20.

Figure 6
figure 6

(a) Spike response modulated for VG values of 0 mV and 100 mV. (b) Spiking frequency (fs) and energy consumption per spike as a function of VG when an Isyn pulse of 5 μA is input.

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Table 1 compares our proposed spiking neuron with previously reported spiking neurons. The comparison focuses on core device, spiking frequency, energy consumption, input type, tunability and circuit components. PD-SOI MOSFET based spiking neurons integrate voltage synaptic signals without capacitor, but requires large energy consumption due to their large threshold (≤ 35 pJ/spike)19. JLFET and TBIMOS based neurons also have superior spiking frequency (1 ~ 180 MHz) with ~ 30 times less energy (≤ 1.14 pJ/spike) and ~ 100 times less energy (≤ 0.37 pJ/spike), respectively, compared to PD-SOI MOSFET based neuron21,22. PCMO RRAM neurons, another spiking neuron utilizing the capacitor-less integration method, consume low energy (less than 4.8 pJ/spike) to fire spikes26. However, in these spiking neurons, which operate the integration step without a capacitor, external reset circuits are essential for periodic IF operation and an I-V convertor using OP-AMP is also required to receive the current signal from the synaptic device array. In terms of entire spiking neuron circuit, the energy consumption can be significantly increased due to the operation of external circuits that require additional voltage supply30. FBFET and FeFET neurons can emulate neuronal behavior without peripheral circuitry but they need a large number of the components (typically 10 and 8) including two capacitors and have high power consumption (≤ 18.8 pJ/spike and ≤ 369 pJ/spike)18,29. The integration of both excitatory and inhibitory signals, tunable threshold triggering, and reset operations are fully implemented with a single SOI-MOSFET, however, this neuron device consumes a lot of energy consumption (≤ 45 pJ/spike) and oscillates at low frequency (~ 20 Hz)23. Single germanium MOSFET neuron can reduce its threshold voltage, resulting in lower energy consumption (8 pJ/spike) and have a higher spiking frequency (~ 100 Hz) than a single MOSFET neuron25. Among these neurons, our proposed simple spiking neuron is particularly capable of achieving periodic neuronal oscillations with a good spiking frequency (~ 245 kHz) and low energy consumption (≤ 1.37 pJ/spike) without external circuit components, while also implementing biomimetic functions such as inhibition and tunable threshold.

Table 1 Benchmark comparison of the proposed spiking neuron and various reported spiking neurons.
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Conclusions

We have successfully developed a highly biomimetic spiking neuron composed of four components. The heterogeneous bandgap structure of HBT results in the formation of hysteresis with high current margin in the low voltage region. By taking advantage of these hysteresis characteristics, the periodic IF behavior can be operated reliably at high frequency (~ 245 kHz) with low energy consumption (≤ 1.37 pJ/spike). Through modulation of inhibitory signals, inhibition is implemented in multiple strengths, thereby effectively regulating excessive firing. Additionally, the threshold can be adjusted to modulate the spiking frequency by controlling the gate bias of HBTs. These features play an important role in the sparse activity and homeostasis of neural networks. Consequently, our developed neuron can be a strong candidate for realizing fast and energy-efficient neuromorphic systems.