Abstract
Twodimensional (2D) material based FETs are being considered for future technology nodes and high performance logic applications. However, a comprehensive assessment of 2D material based FETs has been lacking for high performance logic applications considering appropriate system level figureofmerits (FOMs) e.g. delay, and energydelay product. In this paper, we present guidelines for 2D material based FETs to meet sub10 nm high performance logic requirements focusing on material requirement, device design, energydelay optimization for the first time. We show the need for 2D materials with smaller effective mass in the transport direction and anisotropicity to meet the performance requirement for future technology nodes. We present novel device designs with one such 2D material (monolayer blackphosphorus) to keep Moore’s alive for the HP logic in sub5 nm gate length regime. With these device proposals we show that below 5 nm gate lengths 2D electrostatistics arising from gate stack design becomes more of a challenge than direct sourcetodrain tunneling for 2D materialbased FETs. Therefore, it is challenging to meet both delay and energydelay requirement in sub5 nm gate length regime without scaling both supply voltage (V _{ DD }) and effectiveoxidethickness (EOT) below 0.5 V and 0.5 nm respectively.
Introduction
To keep Moore’s law alive, silicon based trigate FinFETs are being used for high performance logic at current technology nodes. With each technology generation, these devices achieve 15% boost in ON current, 50% reduction in energydelay product, and 0.5x area scaling^{1, 2}. To further continue this trend, alternative channel materials e.g. SiGe, Ge, IIIV, and novel device architectures e.g. gateallaround nanowire (NW) FETs are being explored for future technology nodes. IIIV materials due to its lower effective mass and electronphonon scattering promise higher mobilities, thus higher ON currents for logic applications. But, the lower effective mass also poses challenges such as losing control on electrostatistics with the scaling of channel length, and lower charge concentrations owing to limited densityofstates (DOS)^{3}. Device architectures such as gateallaround (GAA) FETs promise to achieve better electrostatistics at scaled gate lengths.
Alternatively, 2D materials are considered for high performance logic roadmap due to their atomic thickness, which offer better scalability in comparison to Si and III–V channel FETs^{4}. Within the 2D materials family, monolayer black phosphorus based FET has recently gained popularity as a promising highperformance (HP) logic device option at the end of the semiconductor roadmap due to its superior transport properties^{5}. Monolayer (ML) BP shows anisotropic properties such as lower effective mass in armchair direction and 8x higher effective mass in zigzag direction. By aligning the ML BP channel length in armchair direction and channel width in zigzag direction we can achieve higher carrier velocity (mobility) and higher densityofstates (i.e. inversion charge density) respectively, which can effectively result in higher onstate currents. With fullband dissipative simulations, currents in monolayer black phosphorus (ML BP) FETs are reported to be significantly higher than other ML TMD based FETs^{6, 7}. The dissipative current in ML BP FET is shown to be around 90% of the ballistic current for 10 nm gate length. Having said that, the lower effective mass in the transport direction pose challenges in maintaining good subthreshold slope below 10 nm gate lengths in ML BP FET in comparison to other TMD based FETs. Moreover, the efforts to have the stable BP under ambient condition are ongoing^{8, 9}. Nevertheless, to evaluate real potential of such materials for high performance logic in sub10 nm technology nodes, we need to cooptimize material and different device designs to achieve the required circuitlevel metrics such as delay, and energydelay product.
In this paper, using quantum transport simulations of monolayer 2D materialsbasedFETs, we analyze the cause of such performance degradation in sub10 nm gate length regime due to both material and device parameters. We propose device structures with ML BP to enable scaling of gate length in sub5 nm regime. Further, for a given technology node, we show the selection of supply voltage (V _{ DD }) to achieve the required delay and an optimum energydelay product (EDP).
Results and Discussion
CircuitLevel Requirements
In order to benchmark the 2D FETs at the circuit level and understand the energydelay tradeoff, we choose delay and energy per operation as circuit level figureofmerits (FOMs). We estimate these circuit level metrics for a simplified version of critical path in CMOS logic, with a CMOS inverter chain and balanced 2D FETs for both p and ntype transistors. The firstorder equations for delay and energy per operation can be written as ref. 10:
where τ _{ CP } is the delay of the critical path with a logic depth L _{ D } and the total capacitance of each node C _{ node }. Total energy (E _{ tot }) per operation can be written as sum of dynamic and leakage energy. Here, α, and C _{ tot } denote the activity factor and the total capacitance of the logic design respectively.
Further, we normalize the total energy and delay by the capacitance of the chip, which is reasonable for the sub10 nm technology nodes, when the total capacitance is dominated by interconnect capacitances instead of intrinsic device capacitance, given as:
here Nτ _{ CP }, and NE _{ tot } denote the normalized delay and total energy per operation respectively, while the energydelay product (NEτ) signifies that energy and speed are equally weighed for an optimized logic design.
As shown in Fig. 1, we extend the circuitlevel high performance logic roadmap for sub5 nm technology nodes by extrapolating scaling of normalized delay and energydelay product from Intel 22 nm^{1} to Intel 14 nm technology nodes^{2} with reported 15% boost in ON current (for same supply voltage) and required 50% reduction in the energydelay product. Thus, the scaling of normalized delay by 0.87x and normalized energydelay product by 0.78x results in total capacitance scaling of around 0.8x with each technology node. Figure 1 shows that extended Intel HP requirements seems most reasonable in comparison to ITRS HP requirements while IIIV ITRS HP requirements are quite ambitious.
Technology Requirements
To achieve area scaling of 0.5x with each technology node, the technology parameters such as contacted gate pitch (C _{ GP }) and metal pitch (MP) are scaled by 0.7x with each technology generation. To scale C _{ GP }, gate length (L _{ G }) scaling has been the primary driver for past technology generations. But, due to process constraints, scaling of C _{ GP } below 25 nm is not forseen^{11}. Therefore, for future technology nodes it is imperative to scale gate lengths in sub10 nm to relax constraints on spacer thickness and contact openings. Alternatively, technology options such as monolithic 3D integration are sought to further scale the area per function^{12}. The technology parameters listed in Table 1 (till N2) are taken from IIIV ITRS HP roadmap^{13}.
DeviceLevel FigureofMerits
We consider a doublegate monolayer 2D material based FET as shown in Fig. 2a. The electrical characteristics of 2D material based FETs are calculated using the framework described in methods section. The effect of different transport effective mass and channel lengths on ON current (I _{ ON }) is shown in Fig. 2b. We can clearly see that a smaller effective mass 2D material is the preferred choice for high performance logic. Smaller transport mass 2D materials with anisotropic properties can offer higher carrier injection velocity and higher inversion charge density, resulting in higher onstate current provided we can maintain good electrostatistics with gate length scaling. To get physical insights in electrostatics of shorter gate length devices, we study the effect of transport effective mass on subthreshold slope (S.S.) behavior for different gate lengths as shown in Fig. 2c. We breakdown Fig. 2c into two regions: 1) At lower effective masses S.S. degrades due to direct S/D tunneling (due to material property); 2) At higher effective masses where the increase in S.S. with downscaling of gate lengths is attributed to 2D electrostatistics.
CircuitLevel FigureofMerits
Figure 3 shows the combined effect of subthreshold and superthreshold behavior on delay and energydelay product for a given I _{ OFF } of 100 nA/μm. We observe that till N3, 2D materials with smaller transport effective mass outperform the 2D materials with higher ones. It can be also seen that monolayer BP (\({m}_{x}^{\ast }\) = 0.15 m _{0}, \({m}_{y}^{\ast }\) = 1.2 m _{0}) FET can meet both extended Intel HP and IIIV ITRS 2013 HP delay and energydelay requirements for N7, and N5.
Proposed Device Structures
To further enable the HP logic roadmap with ML BP FETs, we need to improve electrostatistics for sub10 nm channel lengths with novel device designs. We propose device designs which address improving both 2D electrostatistics and direct sourcetodrain (S/D) tunneling.
Improving 2D Electrostatistics
We introduce a lowk interfacial layer (IL) between ML BP and Highk dielectric to reduce fringing fields due to the gate stack at shorter gate lengths^{14}. As shown in Fig. 4a, by reducing fringing fields we improve both the gate control (i.e. slope of gate capacitance with gate voltage) and effective gate capacitance in ON state. Further, Fig. 4b shows that the performance of ML BP FETs at L _{ G } = 7.4 nm improves by more than 50% for the same effectiveoxidethickness (EOT) and physical thickness of the gate oxide (T _{ OX }). For effectiveoxidethicknesses above 0.5 nm, we consider lowκ IL (SiO _{2}) to be between 0.4–0.6 nm and Highκ dielectric (HfO _{2}, ZrO _{2}, La _{2} O _{3}) to be 1–1.5 nm thick. To meet both extended Intel HP and IIIV ITRS 2013 HP delay requirement with the device structure having lowk IL, we can relax EOT requirements of the N3 technology node. Further, to see prospects of such gate stack with gate length scaling, we consider equivalent direct S/D tunneling probability i.e. ~exp (−L _{ G } · \({\sqrt{m}}_{x}^{\ast }\)) as shown in Fig. 4c. It shows that to achieve reasonable 2D electrostatistics below 4.5 nm gate length, we require EOT scaling below 0.5 nm irrespective of the direct S/D tunneling.
Reducing Direct SourcetoDrain Tunneling
We consider different device concepts (as shown in Fig. 5a) which employ depletion at the source/drain extensiontochannel junction in OFF state, resulting in larger tunneling lengths by modifying the potential profile at the junctions. Although, underlap (UL) and junctionless (JL) 2D material based FETs have been shown to improve direct sourcetodrain tunneling at scaled gate lengths^{15}, such designs alone can’t provide required performance below 5 nm gate lengths as shown in Fig. 5b. To achieve the required performance for sub5 nm gate lengths, we propose extended backgate device architecture in conjunction with UL/JL FET, which makes it possible to meet the performance requirements till N0.7 (L _{ G } = 2.7 nm) for a fixed V _{ DD }, and EOT. It is important to note that due to backgate overlap in the extended backgate architecture, an extra parasitic capacitance component as gate overlap capacitance comes in picture which may affect the total capacitance scaling, thus delay and energydelay scaling. Nevertheless, Fig. 5c shows the need to scale V _{ DD } to meet energydelay requirement although the performance (delay) requirement is met till N0.7 for a fixed V _{ DD }.
EnergyDelay Optimization
As shown in Fig. 6a, it is very challenging to meet both energydelay and delay requirement even for smaller supply voltages for N1.5 and beyond. On the other hand, we see that the EOT requirement for N1.5 can be relaxed as shown in Fig. 6b, while Fig. 6c shows that we need to scale EOT below 0.5 nm to meet N1 requirements which scales the supply voltage. As EOTs below 0.5 nm become challenging to achieve using Highk dielectric with IL layer; it requires the advent of twodimensional oxides with higher dielectric constant, and higher tunneling barrier with ML BP.
Effect of contact resistance and scattering
Lastly, to understand the limit on different contact resistances and different ballitsic ratios, we first optimize the device structure consisting of Highκ with IL and extended backgate with underlap for technology node N3. The device parameters are taken from Table 1 and the optimized L _{ UN } comes out to be 1 nm. As shown in Fig. 7a, both I _{ ON } and Nτ _{ CP } degrades by increasing contact resistance (R _{ C }). We notice the upper limit of contact resistance to be 125 Ωμm considering no scattering in the channel. Further, Fig. 7b,c show that for R _{ C }, ranging between 60 to 100 Ωμm, we need to have ballisticity in the channel material between 85% to 60% respectively.
Conclusions
In this paper, we show that monolayer black phosphorus based FETs with different device designs can fulfill the highperformance logic energydelay requirements till sub5 nm gate lengths. Although the monolayer black phosphorus is reported to be unstable under ambient conditions and efforts to have the stable BP are ongoing, we infer that lower transport effective mass 2D material such as monolayer BP (with proposed device designs) perform better than higher effective mass 2D materials. To boost the performance of 2D material FET for advanced technology nodes, we propose device structures consisting of Highκ with IL (to increase the effective device gate capacitance), and extended backgate with underlap (to curb direct sourcetodrain tunneling). To meet the HP logic requirements, Table 2 lists the choice of device structure, and technology/device/circuit level parameters such as EOT/I _{ ON }/V _{ DD }. We see that for N1 and beyond, scaling of V _{ DD } below 0.5 V becomes increasingly hard in order to meet both delay and energydelay requirements, due to 60 mV/dec subthreshold slope limit of FETs. It instigates the requirement of sleep subthreshold slope transistors with effective ON currents ~2000 μA/μm.
Methods
The electrical characteristics of 2D material based FETs in the ballistic limit are calculated using a twoband tight binding (TB) Hamiltonian with a quantum transport simulation framework based on selfconsistent solution of Poisson and Schrödinger equation with nonequilibrium Green’s function within the NanoTCAD ViDES suite^{16}. The twoband Hamiltonian for an anisotropic effective mass twodimensional material with hexagonal lattice can be written as a 2 × 2 Hamiltonian matrix:
where E _{ cm }, and E _{ νm } denote the bottom of conduction band, and top of the valence band. Further, bandgap (E _{ G }) of the material can be expressed as: E _{ G } = E _{ cm } − E _{ νm }. Here, the f(k) function, due to nearest neighbors, can be written as:
Here, t _{1}, t _{2} represents hopping energies in x and y direction respectively, which are calculated using the effective masses in x and y directions and bandgap of 2D material. k _{ x }, and k _{ y } are wave vectors in x & y directions, while a denotes the lattice constant of the twodimensional hexagonal lattice. Further, using secular equation, we obtain the dispersion relation for the twoband model given as:
In order to calculate t _{1} and t _{2} for given effective masses in x and y direction, we use the parabolic effective mass approximation with the twoband model as:
where \({m}_{x}^{\ast }\) and \({m}_{y}^{\ast }\) denotes the reduced effective mass in x and y direction. Using Eqs 4–6, and by taking limit of the second derivative at the minimum energy kpoint, we can calculate t _{1} and t _{2} for a given \({m}_{x}^{\ast }\), \({m}_{y}^{\ast }\), and E _{ G } as:
Further, to calculate practical currents from ballistic currents, first we calibrate our results with fullband dissipative simulations of ML BP FETs at 10.5 nm gate length using monolayer BP material parameters, which results in ballistic ratio of around 0.9 as mentioned in ref. 6. Moreover, the effect of source/drain contact resistances are included according to ITRS guidelines (i.e. linear degradation in the intrinsic ON current from 33% (in 2011) to 40% (in 2026)) to benchmark the performance of intrinsic 2D material based FETs with IIIV ITRS HP roadmap^{13}. Effectively, degradation of around 44% is considered in the ballistic currents due to scattering and contact resistance for Table 2.
References
 1.
Jan, C.H. et al. A 22 nm SoC platform technology featuring 3D trigate and highk/metal gate, optimized for ultra low power, high performance and high density SoC applications. In Electron Devices Meeting (IEDM), 2012 IEEE International, 3–1 (IEEE, 2012).
 2.
Natarajan, S. et al. A 14 nm logic technology featuring 2ndgeneration FinFET, airgapped interconnects, selfaligned double patterning and a 0.0588 mm^{2} SRAM cell size. In 2014 IEEE International Electron Devices Meeting, 3–7 (IEEE, 2014).
 3.
Del Alamo, J. A. Nanometrescale electronics with IIIV compound semiconductors. Nature 479, 317–323 (2011).
 4.
Liu, L., Kumar, S. B., Ouyang, Y. & Guo, J. Performance Limits of Monolayer Transition Metal Dichalcogenide Transistors. IEEE Transactions on Electron Devices 58, 3042–3047 (2011).
 5.
Li, L. et al. Black phosphorus fieldeffect transistors. Nature nanotechnology 9, 372–377 (2014).
 6.
Szabo, A., Rhyner, R., CarrilloNunez, H. & Luisier, M. Phononlimited performance of singlelayer, singlegate black phosphorus nand ptype fieldeffect transistors. In 2015 IEEE International Electron Devices Meeting (IEDM), 12–1 (IEEE, 2015).
 7.
Luisier, M. et al. Firstprinciples simulations of 2D semiconductor devices: Mobility, IV characteristics, and contact resistance. In Electron Devices Meeting (IEDM), 2016 IEEE International, 5–4 (IEEE, 2016).
 8.
Pei, J. et al. Producing airstable monolayers of phosphorene and their defect engineering. Nature communications 7 (2016).
 9.
Illarionov, Y. Y. et al. Longterm stability and reliability of black phosphorus fieldeffect transistors. ACS nano 10, 9543–9549 (2016).
 10.
Agarwal, T. et al. Effect of material parameters on twodimensional materials based TFETs: An energydelay perspective. In 2016 46th European SolidState Device Research Conference (ESSDERC), 47–50 (2016).
 11.
Badaroglu, M. ITRS 2.0  More Moore update. In Focus Team Presentations http://www.itrs2.net/itrsreports.html (2015).
 12.
Batude, P. et al. 3D Sequential Integration: A Key Enabling Technology for Heterogeneous CoIntegration of New Function With CMOS. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2, 714–722 (2012).
 13.
Table PIDS 4, ITRS updates online http://www.itrs2.net/2013itrs.html (2013).
 14.
SalmaniJelodar, M. et al. Optimum Highk Oxide for the Best Performance of UltraScaled DoubleGate MOSFETs. IEEE Transactions on Nanotechnology 15, 904–910 (2016).
 15.
Cao, W., Kang, J., Sarkar, D., Liu, W. & Banerjee, K. 2D semiconductor FETs—Projections and design for sub10 nm VLSI. IEEE Transactions on Electron Devices 62, 3459–3469 (2015).
 16.
Fiori, G. & Iannaccone, G. NanoTCAD ViDES http://vides.nanotcad.com (2008).
Acknowledgements
The authors acknowledge support through the imec’s industrial affiliation programs on core CMOS. G.F. and G.I. gratefully acknowledge European Commission under Contract No. 696656 (Project GRAPHENE FLAGSHIP Core 1).
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T.K.A. performed the device simulations with contributions from G.F. in the definition of the anisotropic 2D material and benchmarked the devices with proposed figureofmerits with contributions from W.D. B.S., I.R., P.R., G.I. and M.H. helped interpreting the simulation results. T.K.A. wrote the manuscript with contributions from all authors.
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Agarwal, T.k., Soree, B., Radu, I. et al. MaterialDeviceCircuit Cooptimization of 2D Material based FETs for UltraScaled Technology Nodes. Sci Rep 7, 5016 (2017). https://doi.org/10.1038/s41598017040553
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