Current-driven magnetic domain-wall logic

Abstract

Spin-based logic architectures provide nonvolatile data retention, near-zero leakage, and scalability, extending the technology roadmap beyond complementary metal–oxide–semiconductor logic1,2,3,4,5,6,7,8,9,10,11,12,13. Architectures based on magnetic domain walls take advantage of the fast motion, high density, non-volatility and flexible design of domain walls to process and store information1,3,14,15,16. Such schemes, however, rely on domain-wall manipulation and clocking using an external magnetic field, which limits their implementation in dense, large-scale chips. Here we demonstrate a method for performing all-electric logic operations and cascading using domain-wall racetracks. We exploit the chiral coupling between neighbouring magnetic domains induced by the interfacial Dzyaloshinskii–Moriya interaction17,18,19,20, which promotes non-collinear spin alignment, to realize a domain-wall inverter, the essential basic building block in all implementations of Boolean logic. We then fabricate reconfigurable NAND and NOR logic gates, and perform operations with current-induced domain-wall motion. Finally, we cascade several NAND gates to build XOR and full adder gates, demonstrating electrical control of magnetic data and device interconnection in logic circuits. Our work provides a viable platform for scalable all-electric magnetic logic, paving the way for memory-in-logic applications.

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Fig. 1: Chiral coupling between adjacent nanomagnets and current-driven DW inversion.
Fig. 2: Current-driven DW inverter.
Fig. 3: Reconfigurable NAND/NOR logic gates.
Fig. 4: Electrical control of data flow and cascaded DW logic circuits.

Data availability

All data used in this paper have been deposited in the Zenodo database, at https://doi.org/10.5281/zenodo.3557288.

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Acknowledgements

We thank A. Weber, V. Guzenko and X. Wang for technical support with sample fabrication and measurements. This work was supported by the Swiss National Science Foundation through grant number 200020-172775. S.M. acknowledges funding from the Swiss National Science Foundation under grant agreement number 200021-172517. A.H. was funded by the European Union’s Horizon 2020 research and innovation programme through Marie Skłodowska-Curie grant agreement number 794207 (ASIQS). J.F. was partially supported by a fellowship from the Chinese Scholarship Council. Part of this work was performed at the PolLux (X07DA) endstation of the Swiss Light Source, Paul Scherrer Institut, Villigen, Switzerland. The PolLux endstation was financed by the German Bundesministerium für Bildung und Forschung under grant agreements 05KS4WE1/6 and 05KS7WE1. Part of this work was performed at the Scanning Probe Microscopy Laboratory, Laboratory for Micro and Nanotechnology, Paul Scherrer Institut, Villigen, Switzerland.

Author information

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Authors

Contributions

Z.L., L.J.H. and P.G. conceived the work and designed the experiments; Z.L. fabricated the samples and performed the MFM and MOKE measurements with the support of A.H., T.P.D. and J.F.; Z.L. analysed and interpreted the data from the MOKE measurements with the help of A.H., T.P.D. and P.G.; Z.L., A.H., G.S., S.F., T.P.D., J.F., S.M. and J.R. performed the STXM measurements and interpreted the data; A.H. performed the micromagnetic simulations; Z.L., P.G. and L.J.H. worked on the manuscript together. All authors contributed to the discussion of the results and the manuscript revision.

Corresponding authors

Correspondence to Zhaochu Luo or Pietro Gambardella or Laura J. Heyderman.

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Competing interests

Z.L., A.H., T.P.D., P.G. and L.J.H. have filed a European patent application (EPO) covering the logic architectures based on current-driven domain-wall motion.

Additional information

Peer review information Nature thanks See-Hun Yang and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Extended data figures and tables

Extended Data Fig. 1 Device fabrication and magnetic characterization.

a, Schematics of main nanofabrication processes for magnetic DW logic circuits. (i) Ion milling of magnetic Pt/Co/Al multilayer to create magnetic strips, (ii) ion milling to produce magnetic racetracks and logic gates, and (iii) oxidization of the Al layer in the OOP regions. The inset shows an SEM image of the 50-nm-wide PMMA mask used to protect the IP region of the NAND gate shown in Fig. 3a during oxygen plasma treatment. The scale bar is 100 nm. b, Polar MOKE measurement of the IP and OOP regions on application of an OOP magnetic field. c, Anomalous Hall measurement of the OOP region on application of an IP magnetic field.

Extended Data Fig. 2 DW inversion in a DW inverter with a straight IP region.

a, STXM image sequence of DW inversion for an incident | DW performed in a DW inverter with a straight IP region. Each XMCD image is captured after the application of two current pulses. The edges of the magnetic racetracks are indicated with red dashed lines and the positions of the inverters are indicated with solid white lines. The bright and dark regions in the XMCD images correspond to and magnetization, respectively. The current density and duration of the pulses are 1.1 × 1012 A m−2 and 1 ns, correspondingly. b, STXM images of the nucleation of reversed magnetic domains in the same DW inverter for four different operations. c, DW velocity in inverters with V-shaped and straight IP regions as a function of current density, determined from the experimental MOKE measurements. Error bars and shading represent the standard deviation of the DW velocity for 5 measurements. All the scale bars are 500 nm.

Extended Data Fig. 3 Further experimental demonstration of the DW inverter.

a, b, MOKE image sequences of DW inversion for incident | (a) and | (b) DWs performed in the same device used for Fig. 2c. The edges of the magnetic racetracks are indicated by red dashed lines and the positions of the inverters are indicated by white lines. The bright and dark regions in the magnetic racetracks in the MOKE images correspond to and magnetization, respectively. The current density and pulse length of the applied current pulses are 7.5 × 1011 A m−2 and 50 ns, correspondingly. The number of applied current pulses is indicated. The entire image sequences are shown in Supplementary Videos 1, 4. c, STXM image sequence of DW inversion for an incident | DW and corresponding micromagnetic simulation. Each XMCD image is captured after the application of one current pulse with a current density of 1.1 × 1012 A m−2 and a pulse length of 1 ns. The bright and dark regions in the XMCD images correspond to and magnetization, respectively. For the simulated images, the IP directions of the magnetizations are given by the colour wheel, and the white and black regions correspond to and magnetization, respectively. The scale bars in the MOKE images are 3 µm and those in the XMCD images with simulations are 500 nm.

Extended Data Fig. 4 Electrical control of DW motion through a cross structure.

The directions of the current J and the DW motion are the same and are indicated for each image (current density 9 × 1011 A m−2, pulse length 30 ns). The edges of the cross structures are indicated with red dashed lines. The bright and dark regions in the cross structure in the MOKE images correspond to and magnetization, respectively. All the scale bars are 1 µm.

Extended Data Fig. 5 Various cascaded DW logic circuits.

a, AND gate fabricated by cascading one NAND gate and one NOT gate. b, Cascaded DW logic circuit with a NAND gate and a NOR gate. Green and purple in the schematic correspond to and magnetization, respectively. There is an inverter placed in the bias reservoir of the NOR gate highlighted with the green box, giving a bias of ‘1’, as shown in inset, whereas the bias for the NAND gate is ‘0’. c, Two-bit multiplexer constructed by cascading three NAND gates and one NOT gate. d, Half-subtractor constructed by cascading four NAND gates and one NOT gate. e, Extensive cascaded DW logic circuits including 10 NAND gates and 11 NOT gates. The bright and dark areas in the device regions in the MFM images correspond to and magnetization, respectively. The MFM images are captured after saturation with an OOP magnetic field to set the initial magnetization direction to in all of the reservoirs, followed by current pulses to obtain the final states. All the scale bars are 500 nm.

Extended Data Fig. 6 Magnetic DW logic elements.

Red and blue shaded regions indicate regions that have OOP and IP anisotropy, respectively. The direction of the current flow is indicated by black arrows. The dimensions of the magnetic DW logic elements used in the experiments are indicated.

Extended Data Fig. 7 DW velocity in a uniform OOP region of a racetrack and effective DW velocity in a NOT gate as a function of current density.

Error bars represent the standard deviation of the DW velocity measured in 5 different devices.

Extended Data Fig. 8 Time sequence of MOKE images of the NAND gate during operation and corresponding schematics.

The NAND gate contains two inverters in each of the DW reservoirs and a bias set to ‘0’. The boundaries of the NAND gate are indicated by red dashed lines. The two V-shaped inverters in the DW reservoirs are associated with small reversed domains in the initial state (purple triangles) resulting from the chiral coupling. A sequence of MOKE images is captured and each image is taken following two current pulses with a current density of 7.5 × 1011 A m−2 and a pulse length of 30 ns. The bright and dark regions in the gate structure in the MOKE images correspond to and magnetization, respectively. In the schematics, green and purple correspond to and magnetization, respectively. The two DW reservoirs and the bias are set to logical value ‘0’ by applying an OOP magnetic field of 1 kOe. All the scale bars are 1 µm.

Extended Data Fig. 9 Propagation delay time for DW logic.

a, Schematic showing the use of the propagation delay time to improve the operational reliability of logic operation in a NAND gate. Green and purple correspond to and magnetization, respectively. b, MFM images of NAND gates with different input racetrack lengths (top, la = lb; middle, la > lb; bottom, la < lb; where la and lb represent the racetrack lengths of input a and b, respectively). The bright and dark regions correspond to and magnetization, respectively. The MFM images are captured after saturation with an OOP magnetic field to set the initial magnetization direction to in all of the reservoirs, followed by application of current pulses to obtain the final states. The direction of the current flow is indicated. c, Schematic showing the dependence of the probability of giving a correct output as a function of propagation delay time. All the scale bars in the MFM images are 500 nm.

Extended Data Fig. 10 Hall measurement of logic operation in a NAND gate.

a, Schematic and optical microscope image of the device. Red, yellow and purple colours in the image represent the regions with electrodes, the Pt cross and the NAND gate, respectively. b, Hall resistance as a function of pulse number and corresponding MOKE images. Left, typical evolution of the Hall resistance with increasing number of pulses. Right, the first 30 and last 30 of the 1,172 repeated measurements. The Hall resistance levels for and output magnetizations are indicated by the red dashed lines. An OOP magnetic field is applied to set the initial state at the beginning of each measurement, indicated with the red arrow. The bright and dark regions in the gate structure in the MOKE images correspond to and magnetization, respectively. The boundaries of the NAND gate are indicated by red dashed lines. The current density and pulse length of the applied current pulses are 7.5 × 1011 A m−2 and 30 ns, respectively. c, Operational reliability as a function of the number of current pulses. All the scale bars are 2 µm.

Supplementary information

Supplementary Information

This file contains Supplementary Figures 1–5 and Supplementary Tables 1 and 2.

Supplementary Video 1

MOKE movie of DW inversion for a DW incident from the left with an | configuration. The edges of the magnetic nanowires are indicated by red dashed lines and the positions of the inverters are indicated by white lines. The bright and dark regions in the racetracks in the MOKE images correspond to and magnetization, respectively. Each frame is captured after the application of one current pulse (current density 7.5×1011 A/m2 and pulse length 50 ns). Some of the frames are shown in Fig. 2c and Extended Data Fig. 3a. The scale bar is 3 µm.

Supplementary Video 2

STXM XMCD movie of DW inversion for incident DWs with | (left) and | (right) configurations. The bright and dark regions in the XMCD images correspond to and magnetization, respectively. Each frame is captured after the application of one current pulse (current density 1.1×1012 A/m2 and pulse length 1 ns). Some of the frames are shown in Fig. 2d and Extended Data Fig. 3c. The scale bars are 500 nm.

Supplementary Video 3

MOKE movie demonstrating the inversion of a domain driven across the IP region with current pulses. The edges of the magnetic nanowires are indicated by red dashed lines and the positions of the inverters are indicated by white lines. The bright and dark regions in the racetracks in the MOKE images correspond to and magnetization, respectively. Each frame is captured after the application of one current pulse (current density 7.5×1011 A/m2 and pulse length 50 ns). Some of the frames are shown in Fig. 2e. The scale bar is 3 µm.

Supplementary Video 4

MOKE movie of DW inversion for DW incident from the left with a | configuration. The edges of the magnetic nanowires are indicated by red dashed lines and the positions of the inverters are indicated by white lines. The bright and dark regions in the racetracks in the MOKE images correspond to and magnetization, respectively. Each frame is captured after the application of one current pulse (current density 7.5×1011 A/m2 and pulse length 50 ns). Some of the frames are shown in Extended Data Fig. 3b. The scale bar is 3 µm.

Supplementary Video 5

MOKE movie demonstrating logic operation in a single NAND gate with a sequence of logic inputs. The boundaries of the logic gate are indicated by red dashed lines and the positions of the inverters are indicated by white lines. The bright and dark areas in the device regions in the MOKE images correspond to and magnetization, respectively. Each frame is captured after the application of one current pulse (current density 7.5×1011 A/m2 and pulse length 30 ns). Some of the frames are shown in Fig. 3f. The scale bar is 1 µm.

Supplementary Video 6

MOKE movie illustrating electrical control of magnetic DW passing through a cross structure. The edges of the magnetic nanowires are indicated by red dashed lines. The bright and dark regions in the cross structure in the MOKE images correspond to and magnetization, respectively. Each frame is captured after the application of one current pulse (current density 9×1011 A/m2 and pulse length 30 ns). Some of the frames are shown in Fig. 4b. The scale bar is 1 µm.

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Luo, Z., Hrabec, A., Dao, T.P. et al. Current-driven magnetic domain-wall logic. Nature 579, 214–218 (2020). https://doi.org/10.1038/s41586-020-2061-y

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