Electronics is approaching a major paradigm shift because silicon transistor scaling no longer yields historical energy-efficiency benefits, spurring research towards beyond-silicon nanotechnologies. In particular, carbon nanotube field-effect transistor (CNFET)-based digital circuits promise substantial energy-efficiency benefits, but the inability to perfectly control intrinsic nanoscale defects and variability in carbon nanotubes has precluded the realization of very-large-scale integrated systems. Here we overcome these challenges to demonstrate a beyond-silicon microprocessor built entirely from CNFETs. This 16-bit microprocessor is based on the RISC-V instruction set, runs standard 32-bit instructions on 16-bit data and addresses, comprises more than 14,000 complementary metal–oxide–semiconductor CNFETs and is designed and fabricated using industry-standard design flows and processes. We propose a manufacturing methodology for carbon nanotubes, a set of combined processing and design techniques for overcoming nanoscale imperfections at macroscopic scales across full wafer substrates. This work experimentally validates a promising path towards practical beyond-silicon electronic systems.
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We acknowledge Analog Devices, Inc. (ADI), the Defence Advanced Research Projects Agency (DARPA) Three-Dimensional System-on-Chip (3DSoC) program, the National Science Foundation and the Air Force Research Laboratory for support. We thank S. Feindt, A. Olney, T. O’Dwyer, S. Gupta and S. Knepper (all at ADI), and Dimitri Antoniadis and Utsav Banerjee (both at MIT) for collaborations.
A.C. is a board member at Analog Devices, Inc., and this work was sponsored in part by Analog Devices, Inc.
Publisher’s note: Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Peer review information Nature thanks Marko Radosavljevic and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.
Extended data figures and tables
The fabrication process is a 5-metal-layer (M1 to M5) process and involves >100 individual process steps. s-CNT, semiconducting CNT; S/D, source/drain.
The processor core is in the middle of the die, with test circuitry surrounding the perimeter (when the RV16X-NANO is diced for packaging, these test structures are removed). The test structures include test structures for monitoring fabrication, as well as for measuring and characterizing all of the 63 standard cells in our standard cell library.
List of all of the standard cells comprising our standard cell library, along with a microscopy image of each fabricated standard cell, the schematic of each cell, and a typical measured waveform from each fabricated cell. As expected for static CMOS logic stages, the CNFET logic stages exhibit output voltage swing exceeding 99% of VDD, and achieve gain of >15. Experimental waveforms are not shown for cells whose functionality is not demonstrated by output voltage as a function of either input voltage or time; for example, for cells without outputs (for example, fill cells: cell names that start with ‘fill_’ or decap cells: cell names that start with ‘decap_’), for cells whose output is constant (tied high/low: cell names that start with ‘tie_’), or for transmission gates (cell names that start with ‘tg_’).
Each wafer includes 32 dies (single die shown in Extended Data Fig. 2).
a, CNT density is the same pre- versus post-RINSE. b, CNFET ID–VGS exhibit minimal change for sets of CNFETs fabricated with and without RINSE (VDS = −1.8 V for all measurements shown). Both samples came from the same wafer, which was diced after the CNT deposition but before the RINSE process. One sample underwent RINSE while the other sample did not. c, CNFETs can still be doped NMOS after the RINSE process, leveraging our MIXED process (VDS = −1.2 V for all measurements shown).
a, Definitions of key metrics for characterizing logic gates, including SNM, gain and swing. VOH, VIH, VIL and VIL (labelled on the VTCs in a, where (VIL, VOH) and (VIH, VOL) are the points on the VTC where ΔVOUT/ΔVIN = −1) are used to extract the noise margin: SNM = min(SNMH, SNML). b, Key metrics extracted for the 10,400 CNFET CMOS nor2 logic gates measured in Fig. 5 (metrics defined in a). This is the largest CNT CMOS demonstration to date, to our knowledge. VDD is 1.2 V. c, SNM is extracted based on the distributions from b. We analyse >100 million logic gate pairs based on these experimental results. d, Spatial dependence of VIH (as an example parameter to compute SNM). Each pixel represents the VIH of the nor2 at that location in the die. Importantly, VIH increases across the die (from top to bottom). The change in VIH corresponds with slight changes in CNFET threshold voltage. The fact that the threshold voltage variations are not independently and identically distributed (i.i.d.), but rather have spatial dependence, illustrates that a portion of the threshold voltage variations (and therefore variation in SNM) is due to wafer-level processing-related variations (CNT deposition is more uniform across the 150-mm wafer). Future work should optimize processing steps, for example, increasing the uniformity of the atomic-layer-deposition oxide deposition used for electrostatic doping to further improve SNM for realizing VLSI circuits. e, Wafer-scale CNFET CMOS characterization. Measurements from 4 dies across 150-mm wafer (1,000 CNFET CMOS nor2 logic gates are sampled randomly from the 10,400 such logic gates in each die). No outliers are excluded. Yield and performance variations are negligible across the wafer, illustrated by the distribution of the output voltage swing.
a, Reduction in CNFET EDP benefits versus pS (metallic CNTs increase IOFF, degrading EDP). pS ≈ 99.999%, sufficient to minimize EDP cost due to metallic CNTs to ≤5%. b, pNMS versus pS (metallic CNTs degrade SNM), (shown for SNMR = VDD/5, and for a circuit of one million logic gates). Although 99.999% pS is sufficient to limit EDP degradation to ≤5%, panel b shows that SNM imposes far stricter requirements on purity: pS ≈ 99.999999% (that is, number of 9s is 8) to achieve pNMS ≥ 99% (number of 9s is 2). Results in panels a and b are simulated for VLSI circuit modules from a 7-nm node processor core (see Supplementary Information and Methods for additional details).
a, Experimentally measured ID versus VGS for all 1,000 NMOS (VDS = 1.8 V) and 1,000 PMOS CNFETs (VDS = −1.8 V), with no CNFETs omitted. Metallic CNTs (m-CNTs) present in some CNFETs result in high off-state leakage current (IOFF = ID at VGS = 0 V). b, VTC and SNM parameter definitions, for example, for (nand2, nor2). DR is the driving logic stage; LD is the loading logic stage. SNM = min(SNMH, SNML), where SNMH = VOH(DR) – VIH(LD) and SNML = VIL(LD) – VOL(DR). c–e, Methodology to solve VTCs (for example, for nand2) using experimentally measured CNFET I–V curves. c, Example ID versus VDS for NMOS and PMOS CNFETs (VGS is swept from −1.8 V to 1.8 V in 0.1-V increments). d, Schematic. To solve a VTC (for example, VOUT versus VA with VB = VDD): for each VA, find V1 and VOUT such that iPA + iPB = iNA = iNB (DC, direct current, convergence). e, Current in the pull-up network (iPU, where iPU = iPA + iPB, and iPA and iPB are the labelled drain currents of the PMOS FETs gated by A and B, respectively) and current in the pull-down network (iPD, where iPD = iNA = iNB, and iNA and iNB are the labelled drain currents of the NMOS FETs gated by A and B, respectively) versus VOUT and VA. The VTC is seen where these currents intersect. CNFETs are fabricated at a ~1 µm technology node, and the CNFET width is 19 µm in panel a.
a, Standard cell layouts (derived using the ‘asap7sc7p5t’ standard cell library37), illustrating the importance of CNT correlation: because the length of CNTs (which can be of the order of hundreds of micrometres) is typically much longer compared with the CNFET contacted gate pitch (CGP, for example about 42–54 nm for a 7-nm node37), the number of s-CNTs and m-CNTs in CNFETs can be uncorrelated or highly correlated depending on the relative physical placement of CNFET active regions38. For many CMOS standard cell libraries at sub-10-nm nodes (for example refs 37,39), the active regions of FETs are highly aligned, resulting in highly correlated number of m-CNTs among CNFETs in library cells, further degrading VTCs (because one m-CNT can affect multiple CNFETs simultaneously). b–f, Generating a variation-aware CNFET SNM model, shown for a D-flip-flop (dff) derived from the asap7sc7p5t standard cell library37. b, Layout used to extract netlists for each logic stage. c, Schematic: CNFETs are grouped by logic stage (with nodes arbitrarily labelled ‘D’, ‘MH’, ‘MS’, ‘SH’, ‘SS’, ‘CLK’, ‘clkn’, ‘clkb’ and ‘QN’ for ease of reference). d, For each extracted netlist, there can be multiple VTCs: for each logic stage output, a logic stage input is sensitized if the output state (0 or 1) depends on the state of that input (given the states of all the other inputs). For example, for a logic stage with Boolean function: Y = !(A*B+C), C is sensitized when (A, B) = (0, 0), (0, 1) or (1, 0). We simulate all possible VTCs (over all logic stage outputs and sensitized inputs), and also in the presence of m-CNTs. For example, panel d shows a subset of the VTCs for the logic stage in panel b with output node ‘MH’ (labelled in panel c), and sensitized input ‘D’ (with labelled nodes (‘clkb’, ‘clkn’, ‘MS’) = (0, 1, 0)). The dashed line indicates VTC with no m-CNTs, and the solid lines are example VTCs in the presence of m-CNTs (including the effect of CNT correlation). In each case, we model VOH, VIH, VIL and VOL as affine functions of the number of m-CNTs (Mi) in each of r regions (M1, ..., Mr), with calibration parameters in the static noise margin (SNM) model matrix T (shown in panel f). e, Example calibration of the SNM model matrix T for the VTC parameters extracted in panel d; the symbols are VTC parameters extracted from circuit simulations (using Cadence Spectre), and solid lines are the calibrated model. f, Affine model form. g–j, VLSI design and analysis methodology. g, Industry-practice physical design flow to optimize energy and delay of CNFET digital VLSI circuits, including: (1) library power/timing characterization (using Cadence Liberate) across multiple VDD and using parasitics extracted from standard cell layouts (derived from the asap7sc7p5t standard cell library), in conjunction with a CNFET compact model8. (2) Synthesis (using Cadence Genus), place-and-route (using Cadence Innovus) with back-end-of-line (BEOL) wire parasitics from the ASAP7 process design kit (PDK). (3) Circuit EDP optimization: we sweep both VDD and target clock frequency (during synthesis/place-and-route) to create multiple physical designs. The one with best EDP is used to compare design options (for example, DREAM versus baseline). h, Subset of logic gates in an example circuit module, showing the effect of CNT correlation at the circuit level (for example, the m-CNT counts of CNFETs P3,1 and P5,1 are both equal to M1 + M2 + M3)40. i, Distribution of SNM over all connected logic stage pairs, for a single sample of the circuit m-CNT counts. The minimum SNM for each trial limits the probability that all noise margin constraints in the circuit are satisfied (pNMS). j, Cumulative distribution of minimum SNM over 10,000 Monte Carlo trials, shown for multiple target pS values, where pS is the probability that a given CNT is a semiconducting CNT. These results are used to find pNMS versus pS for a target SNM requirement (SNMR), where pNMS is the fraction of trials that meet the SNM requirement for all logic stage pairs. We note that pNMS can then be exponentiated to adjust for various circuit sizes based on the number of logic gates. k, CNFET compact model parameters (for example, 7-nm node).
Supplementary Text, Data, Tables and References.
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