Electronic and photonic technologies have transformed our lives—from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions1,2. This goal is hindered by the fact that most silicon nanotechnologies—which enable our processors, computer memory, communications chips and image sensors—rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal–oxide–semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing3,4. By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions5, but with the performance, complexity and scalability of ‘systems on a chip’1,6,7,8. As transistors smaller than ten nanometres across become commercially available9, and as new nanotechnologies emerge10,11, this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.
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Sun, C. et al. Single-chip microprocessor that communicates directly using light. Nature 528, 534–538 (2015).
Khilo, A. et al. Photonic ADC: overcoming the bottleneck of electronic jitter. Opt. Express 20, 4454–4469 (2012).
Rumley, S. et al. Silicon photonics for exascale systems. J. Lightwave Technol. 33, 547–562 (2015).
Miller, D. A. Rationale and challenges for optical interconnects to electronic chips. Proc. IEEE 88, 728–749 (2000).
Boeuf, F. et al. A multi-wavelength 3D-compatible silicon photonics platform on 300 mm SOI wafers for 25 Gb/s applications. In Electron Devices Meeting (IEDM) 13–3 (IEEE, 2013).
Assefa, S. et al. Monolithic integration of silicon nanophotonics with CMOS. In Photonics Conference (IPC) 626–627 (IEEE, 2012).
Narasimha, A. et al. A 40-Gb/s QSFP optoelectronic transceiver in a 0.13 µm CMOS silicon-on-insulator technology. In Optical Fiber Communication Conference (OMK7) (Optical Society of America, 2008).
Awny, A. et al. A 40 Gb/s monolithically integrated linear photonic receiver in a 0.25 µm BiCMOS SiGe:C technology. IEEE Microw. Wirel. Compon. Lett. 25, 469–471 (2015).
Ieong, M., Doris, B., Kedzierski, J., Rim, K. & Yang, M. Silicon device scaling to the sub-10-nm regime. Science 306, 2057–2060 (2004).
del Alamo, J. A. Nanometre-scale electronics with III–V compound semiconductors. Nature 479, 317–323 (2011).
Desai, S. B. et al. MoS2 transistors with 1-nanometer gate lengths. Science 354, 99–102 (2016).
Ghelfi, P. et al. A fully photonics-based coherent radar system. Nature 507, 341–345 (2014).
Mudumba, S. et al. Photonic ring resonance is a versatile platform for performing multiplex immunoassays in real time. J. Immunol. Methods 448, 34–43 (2017).
Quail, M. A. et al. A tale of three next generation sequencing platforms: comparison of Ion Torrent, Pacific Biosciences and Illumina MiSeq sequencers. BMC Genomics 13, 341 (2012).
Zolfaghari, A., Chan, A. & Razavi, B. Stacked inductors and transformers in CMOS technology. IEEE J. Solid-State Circuits 36, 620–628 (2001).
Fossum, E. R. CMOS image sensors: electronic camera-on-a-chip. IEEE Trans. Electron Dev. 44, 1689–1698 (1997).
Magarshack, P., Flatresse, P. & Cesana, G. UTBB FD-SOI: A process/design symbiosis for breakthrough energy-efficiency. In Proc. Conf. Design, Automation and Test in Europe 952–957 (EDA Consortium, 2013).
Wörhoff, K., Heideman, R. G., Leinse, A. & Hoekman, M. TriPleX: a versatile dielectric photonic platform. Adv. Opt. Technol. 4, 189–207 (2015).
Selvaraja, S. K. et al. Low-loss amorphous silicon-on-insulator technology for photonic integrated circuitry. Opt. Commun. 282, 1767–1770 (2009).
Sun, C. et al. A monolithically-integrated chip-to-chip optical link in bulk CMOS. IEEE J. Solid-State Circ. 50, 828–844 (2015).
Preston, K., Manipatruni, S., Gondarenko, A., Poitras, C. B. & Lipson, M. Deposited silicon high-speed integrated electro-optic modulator. Opt. Express 17, 5118–5124 (2009).
Dangel, R. et al. Polymer-waveguide-based board-level optical interconnect technology for datacom applications. IEEE Trans. Adv. Packag. 31, 759–767 (2008).
Eggleton, B. J., Luther-Davies, B. & Richardson, K. Chalcogenide photonics. Nat. Photon. 5, 141–148 (2011).
Xu, Q., Schmidt, B., Pradhan, S. & Lipson, M. Micrometre-scale silicon electro-optic modulator. Nature 435, 325–327 (2005).
Shainline, J. M. et al. Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS. Opt. Lett. 38, 2657–2659 (2013).
Mehta, K. K. et al. Polycrystalline silicon ring resonator photodiodes in a bulk complementary metal-oxide-semiconductor process. Opt. Lett. 39, 1061–1064 (2014).
Atabaki, A. H., Meng, H., Alloatti, L., Mehta, K. K. & Ram, R. J. High-speed polysilicon CMOS photodetector for telecom and datacom. Appl. Phys. Lett. 109, 111106 (2016).
Nishi, Y. & Doering, R. Handbook of Semiconductor Manufacturing Technology (CRC Press, 2000).
Soref, R. & Bennett, B. Electrooptical effects in silicon. IEEE J. Quantum Electron. 23, 123–129 (1987).
Ackert, J. J. et al. 10 Gbps silicon waveguide-integrated infrared avalanche photodiode. Opt. Express 21, 19530–19537 (2013).
Settaluri, K. T. et al. Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform. In 41st European Solid-State Circuits Conf. (ESSCIRC) 156–159 (IEEE, 2015).
Sun, C. et al. A 45 nm CMOS-SOI monolithic photonics platform with bit-statistics-based resonant microring thermal tuning. IEEE J. Solid-State Circ. 51, 893–907 (2016).
Yang, S. et al. 10 nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling. In Symp. on VLSI Technology T70–T71 (IEEE, 2017).
Alloatti, L., Wade, M., Stojanovic, V., Popovic, M. & Ram, R. Photonics design tool for advanced CMOS nodes. IET Optoelectron. 9, 163–167 (2015).
Seto, J. Y. W. The electrical properties of polycrystalline silicon films. J. Appl. Phys. 46, 5247 (1975).
Notaros, J. et al. Ultra-efficient CMOS fiber-to-chip grating couplers. In Optical Fiber Communications Conf. Exhib. (OFC) 1–3 (IEEE, 2016).
We thank E. Timurdogan and M. Byrd for help with high-speed photonic measurements, and A. Nikiforov of the Boston University Photonics Center for assistance with sample imaging and analysis. This work was supported by DARPA POEM award HR0011-11-C-0100 and contract HR00111190009, led by J. Shah. We also acknowledge support from the Microsystems Technology Laboratories (MTL) at MIT, the Berkeley Wireless Research Center, the Center for Nanoscale Sciences and Engineering and the Packard Foundation. The views expressed are those of the authors and do not reflect the official policy or position of the DoD or the US Government.
C.S., M.T.W., R.J.R., M.A.P. and V.M.S. are involved in developing silicon photonic technologies at Ayar Labs.
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Extended data figures and tables
a, Waveguide propagation loss at 1,300 nm. Waveguide loss drops with wavelength because of a combination of lower absorption and scattering by polysilicon. b, Q-factor of a 15-µm-diameter microring resonator. c, Waveguide propagation loss at 1,550 nm. d, One resonance of a 17-µm-diameter microring near 1,540 nm with a Q-factor of 38,000.
a, Current–voltage curve of the microring photodiode under dark and illumination for an input optical power of 20 µW. Dynamic range is about 60 dB and about 10 dB at 0 V and 16 V, respectively. b, One microring photodetector resonance (top) and the corresponding photo-current (bottom) as the wavelength is swept across the resonance. The loaded Q-factor (Qloaded) of the microring is about 10,000. The fit is obtained through least-squares optimization of a model that includes a Lorentzian resonance for the microring and accounts for the reflections from the end facets of the chip to model the Fabry–Perot resonances observed in the transmission curve. c, Noise equivalent power (NEP, blue curve) of the photodiode estimated from the dark-current shot noise, which dominates the detector noise. Avalanche gain is 13 at 16 V bias, with an noise equivalent power of 0.27 pW Hz−1/2. The simulated signal-to-noise ratio (SNR) (red curve) at the output of the optical receiver, assuming an optical signal of 1 µW, and a receiver circuit input-referred noise spectral density of 1 pA Hz−1/2. d, The responsivity of the photodetector versus input optical power, showing minimal power dependency. The error bar is estimated based on a ±5% error in estimating the optical power in the waveguide before coupling into the detector. This error comes from variations in fibre to chip coupling efficiency owing to fibre-grating coupler misalignment. e, f, Eye diagrams at 12.5 Gb s−1 at 0 V and 14.5 V reverse bias.
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Atabaki, A.H., Moazeni, S., Pavanello, F. et al. Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip. Nature 556, 349–354 (2018). https://doi.org/10.1038/s41586-018-0028-z
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