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Scalable CMOS back-end-of-line-compatible AlScN/two-dimensional channel ferroelectric field-effect transistors

Nature Nanotechnology volume 18, pages 1044–1050 (2023)Cite this article

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Abstract

Three-dimensional monolithic integration of memory devices with logic transistors is a frontier challenge in computer hardware. This integration is essential for augmenting computational power concurrent with enhanced energy efficiency in big data applications such as artificial intelligence. Despite decades of efforts, there remains an urgent need for reliable, compact, fast, energy-efficient and scalable memory devices. Ferroelectric field-effect transistors (FE-FETs) are a promising candidate, but requisite scalability and performance in a back-end-of-line process have proven challenging. Here we present back-end-of-line-compatible FE-FETs using two-dimensional MoS2 channels and AlScN ferroelectric materials, all grown via wafer-scalable processes. A large array of FE-FETs with memory windows larger than 7.8 V, ON/OFF ratios greater than 107 and ON-current density greater than 250 μA um–1, all at ~80 nm channel length are demonstrated. The FE-FETs show stable retention up to 10 years by extension, and endurance greater than 104 cycles in addition to 4-bit pulse-programmable memory features, thereby opening a path towards the three-dimensional heterointegration of a two-dimensional semiconductor memory with silicon complementary metal–oxide–semiconductor logic.

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Fig. 1: AlScN/MoS2 FE-FET device structure and electrical characteristics and the FE property of AlScN.
Fig. 2: Array of scaled AlScN/MoS2 FE-FETs.
Fig. 3: Electrical characterization of voltage-pulse-induced FE switching in scaled FE-FETs.
Fig. 4: Multibit operation of scaled FE-FET devices.

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All data needed to evaluate the conclusions of this study are present in the Article and its Supplementary Information.

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Acknowledgements

This material is based on work supported by the Defense Advanced Research Projects Agency (DARPA) TUFEN program under agreement no. HR00112090046. The work was carried out in part at the Singh Center for Nanotechnology at the University of Pennsylvania, which is supported by the National Science Foundation (NSF) National Nanotechnology Coordinated Infrastructure Program (NSF grant NNCI-1542153). H.M.K., K.K. and D.J. acknowledge partial support from the Penn Center for Undergraduate Research and Fellowships. We gratefully acknowledge the use of the facilities and instrumentation supported by NSF through the University of Pennsylvania Materials Research Science and Engineering Center (MRSEC) (DMR-1720530). P.K., E.A.S. and D.J. also acknowledge partial support from the NSF DMR Electronic Photonic and Magnetic Materials (EPM) core program (grant no. DMR-1905853) as well as the University of Pennsylvania Laboratory for Research on the Structure of Matter, a Materials Research Science and Engineering Center (MRSEC) supported by the NSF (no. DMR-1720530). A.A., Y.W. and V.C.T. are indebted to the support from the King Abdullah University of Science and Technology (KAUST) Solar Center and Office of Sponsored Research (OSR) under award no. OSR-2018-CARF/CCF-3079. The MOCVD-grown MoS2 monolayer samples were provided by the 2D Crystal Consortium—Materials Innovation Platform (2DCC-MIP) facility at the Pennsylvania State University, which is funded by the NSF under cooperative agreement nos. DMR-1539916 and DMR-2039351. S.S. acknowledges support from the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (grant no. 2021R1A6A3A14038492). K.K. acknowledges support from the NSF Graduate Research Fellowship Program (GRFP), Fellow ID: 2022338725. N.T. acknowledges that this material is based upon work supported by the National Science Foundation Graduate Research Fellowship Program under Grant No. DGE1255832.

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Authors and Affiliations

  1. Department of Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, PA, USA

    Kwan-Ho Kim, Merrilyn Mercy Adzo Fiagbenu, Pariasadat Musavigharavi, Pawan Kumar, Hyong Min Kim, Keshava Katti, Seunguk Song, Gwangwoo Kim, Zichen Tang, Roy H. Olsson III & Deep Jariwala

  2. Division of Electrical Engineering, Hanyang University ERICA, Ansan, South Korea

    Seyong Oh

  3. Department of Materials Science and Engineering, University of Pennsylvania, Philadelphia, PA, USA

    Jeffrey Zheng, Pariasadat Musavigharavi & Eric A. Stach

  4. Department of Materials Science and Engineering, Pennsylvania State University, University Park, PA, USA

    Nicholas Trainor & Joan M. Redwing

  5. Department of Physics, King Abdulaziz University, Jeddah, Saudi Arabia

    Areej Aljarb

  6. Department of Physical Science and Engineering, King Abdullah University of Science and Technology, Thuwal, Saudi Arabia

    Yi Wan & Vincent Tung

  7. Department of Chemical System Engineering, University of Tokyo, Tokyo, Japan

    Jui-Han Fu, Mariam Hakami & Vincent Tung

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Contributions

D.J., R.H.O. and K-H.K. conceived the idea of using large-area 2D semiconductors with AlScN to make the CMOS BEOL-compatible FE-FETs at scale and with scaled dimensions. K.-H.K. designed the experiments and performed the device fabrication and characterization of the samples. K.-H.K. and D.J. wrote the manuscript. M.M.A.F. and K.-H.K. conducted the P–E loop and PUND measurements and R.H.O. supervised them. J.Z. and K.-H.K. performed sputtering to prepare the various AlScN substrates and R.H.O. supervised them. P.M. and P.K. performed the TEM and SEM characterizations, respectively. P.K. prepared the cross-sectional lamella for the subsequent TEM observation. E.A.S. supervised the microscopy efforts. N.T. prepared the two-inch wafer-scale MoS2 using MOCVD and J.M.R. supervised it. CVD-based two-inch wafer-scale MoS2 was prepared by A.A., Y.W., J.-H.F. and M.H., and V.T. supervised them. K.-H.K. and P.K. performed the wet transfer of MoS2 on AlScN and SiO2. S.O. and K.K. contributed to the MLP-based artificial neural network simulation and technology computer-aided design simulation. K.-H.K. and H.M.K. performed the electrical measurements of 130 FE-FET arrays. S.S. and G.K. performed the device fabrication for revision. Z.T. developed the recipe for electron-beam lithography. All the authors contributed to the discussion and analysis of the results.

Corresponding authors

Correspondence to Roy H. Olsson III or Deep Jariwala.

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Competing interests

D.J., R.H.O., K.-H.K. and E.A.S. are co-inventors on a patent (US Patent App. 17/354,256) based on this work. The other authors declare no competing interests.

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Nature Nanotechnology thanks Kah-Wee Ang and Weida Hu for their contribution to the peer review of this work.

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Kim, KH., Oh, S., Fiagbenu, M.M.A. et al. Scalable CMOS back-end-of-line-compatible AlScN/two-dimensional channel ferroelectric field-effect transistors. Nat. Nanotechnol. 18, 1044–1050 (2023). https://doi.org/10.1038/s41565-023-01399-y

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