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Highly reproducible van der Waals integration of two-dimensional electronics on the wafer scale

Nature Nanotechnology volume 18, pages 471–478 (2023)Cite this article

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Abstract

Two-dimensional (2D) semiconductors such as molybdenum disulfide (MoS2) have attracted tremendous interest for transistor applications. However, the fabrication of 2D transistors using traditional lithography or deposition processes often causes undesired damage and contamination to the atomically thin lattices, partially degrading the device performance and leading to large variation between devices. Here we demonstrate a highly reproducible van der Waals integration process for wafer-scale fabrication of high-performance transistors and logic circuits from monolayer MoS2 grown by chemical vapour deposition. By designing a quartz/polydimethylsiloxane semirigid stamp and adapting a standard photolithography mask-aligner for the van der Waals integration process, our strategy ensures a uniform mechanical force and a bubble-free wrinkle-free interface during the pickup/release process, which is crucial for robust van der Waals integration over a large area. Our scalable van der Waals integration process allows damage-free integration of high-quality contacts on monolayer MoS2 at the wafer scale and enables high-performance 2D transistors. The van-der-Waals-contacted devices display an atomically clean interface with much smaller threshold variation, higher on-current, smaller off-current, larger on/off ratio and smaller subthreshold swing than those fabricated with conventional lithography. The approach is further used to create various logic gates and circuits, including inverters with a voltage gain of up to 585, and logic OR gates, NAND gates, AND gates and half-adder circuits. This scalable van der Waals integration method may be useful for reliable integration of 2D semiconductors with mature industry technology, facilitating the technological transition of 2D semiconductor electronics.

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Fig. 1: Wafer-scale vdW integration.
Fig. 2: Alignment offset in large-scale vdW integration.
Fig. 3: Electronic properties of large-area vdW-integrated monolayer MoS2 FETs with Ag/Au contacts.
Fig. 4: Monolayer-MoS2-based inverter with vdW contacts.
Fig. 5: The vdW integration MoS2 logic gates and half-adder.

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Data availability

The data that support the findings of this study are available within the paper and the Supplementary Information. Other relevant data are available from the corresponding authors on reasonable request. Source data are provided with this paper.

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Acknowledgements

We at Hunan University acknowledge the support from the National Natural Science Foundation of China (grant nos. 51802090, 51872086, 51991341, 52102168, 61874041, 61925403), the Innovative Research Groups of Hunan Province (grant no. 2020JJ1001), the Hunan Key Laboratory of Two-Dimensional Materials (grant no. 2018TP1010) and the National Key R&D Program of China (grant no. 2021YFA1200503). The author at Ningbo University of Technology acknowledges the support from the Scientific Research Starting Foundation of Ningbo University of Technology (grant no. 2022KQ37).

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  1. These authors contributed equally: Xiangdong Yang, Jia Li.

Authors and Affiliations

  1. Hunan Key Laboratory of Two-Dimensional Materials, State Key Laboratory for Chemo/Biosensing and Chemometrics, College of Chemistry and Chemical Engineering, Hunan University, Changsha, China

    Xiangdong Yang, Jia Li, Rong Song, Bei Zhao, Jingmei Tang, Zhengwei Zhang & Xidong Duan

  2. Institute of Micro/Nano Materials and Devices, Ningbo University of Technology, Ningbo, China

    Xiangdong Yang

  3. School of Physics and Electronics, Hunan University, Changsha, China

    Lingan Kong, Hao Huang, Lei Liao & Yuan Liu

  4. School of Resources, Environments and Materials, Guangxi University, Nanning, China

    Hao Huang

  5. Department of Chemistry and Biochemistry, University of California, Los Angeles, Los Angeles, CA, USA

    Xiangfeng Duan

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Contributions

Xidong Duan and Y.L. conceived and supervised the project. X.Y. designed the experiments. J.L. and R.S. performed the growth of the 2 inch MoS2 wafers with help from B.Z. and Z.Z.; X.Y. fabricated and measured the devices with help from J.T., L.K., H.H., L.L. and Y.L.; X.Y., J.L., H.H., Y.L. Xidong Duan and Xiangfeng Duan contributed to the data analysis and discussions of the results. X.Y., J.L., Xidong Duan, Y.L. and Xiangfeng Duan cowrote the manuscript, and all authors commented on the manuscript.

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Correspondence to Yuan Liu or Xidong Duan.

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Nature Nanotechnology thanks Won Jong Yoo and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Supplementary figs. 1–9 and text.

Supplementary video 1. The formation process of the bubble-free and wrinkle-free PDMS/PMMA interface.

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Source Data Fig. 4

Statistical source data of Fig. 4.

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Statistical source data of Fig. 5.

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Yang, X., Li, J., Song, R. et al. Highly reproducible van der Waals integration of two-dimensional electronics on the wafer scale. Nat. Nanotechnol. 18, 471–478 (2023). https://doi.org/10.1038/s41565-023-01342-1

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