Article | Published:

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications


As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

Access optionsAccess options

Rent or Buy article

Get time limited or full article access on ReadCube.


All prices are NET prices.

Additional information

Publisher’s note: Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.


  1. 1.

    Seabaugh, A. C. & Zhang, Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98, 2095–2110 (2010).

  2. 2.

    Ionescu, A. M. & Riel, H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011).

  3. 3.

    Wang, P. F. et al. A semi-floating gate transistor for low-voltage ultrafast memory and sensing operation. Science 341, 640–643 (2013).

  4. 4.

    Makarov, A., Sverdlov, V. & Selberherr, S. Emerging memory technologies: trends, challenges, and modeling methods. Microelectron. Reliab. 52, 628–634 (2012).

  5. 5.

    Yang, J. J., Strukov, D. B. & Stewart, D. R. Memristive devices for computing. Nat. Nanotech. 8, 13–24 (2013).

  6. 6.

    International Technology Roadmap for Semiconductors 2.0 (ITRS, 2015);

  7. 7.

    Lembke, D. & Kis, A. Breakdown of high-performance monolayer MoS2 transistors. ACS Nano 6, 10070–10075 (2012).

  8. 8.

    Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V. & Kis, A. Single-layer MoS2 transistors. Nat. Nanotech. 6, 147–150 (2011).

  9. 9.

    Fang, H. & Chuang et al. High-performance single layered WSe2 p-FETs with chemically doped contacts. Nano Lett. 12, 3788–3792 (2012).

  10. 10.

    Deng, Y. et al. Black phosphorus-monolayer MoS2 van der Waals heterojunction p-n diode. ACS Nano 8, 8292–8299 (2014).

  11. 11.

    Roy, K. et al. Graphene-MoS2 hybrid structures for multifunctional photoresponsive memory devices. Nat. Nanotech. 8, 826–830 (2013).

  12. 12.

    Baugher, B. W., Churchill, H. O., Yang, Y. & Jarilloherrero, P. Optoelectronic devices based on electrically tunable p–n diodes in a monolayer dichalcogenide. Nat. Nanotech. 9, 262–267 (2014).

  13. 13.

    Yu, Z. et al. Analyzing the carrier mobility in transition metal dichalcogenide MoS2 field effect transistors. Adv. Funct. Mater. 27, 1604093 (2017).

  14. 14.

    Britnell, L. et al. Electron tunneling through ultrathin boron nitride crystalline barriers. Nano Lett. 12, 1707–1710 (2012).

  15. 15.

    Zhao, W. et al. Evolution of electronic structure in atomically thin sheets of WS2 and WSe2. ACS Nano 7, 791–797 (2012).

  16. 16.

    Zhang, Y. et al. Direct observation of the transition from indirect to direct bandgap in atomically thin epitaxial MoSe2. Nat. Nanotech. 9, 111–115 (2014).

  17. 17.

    Li, L. et al. Black phosphorus field-effect transistors. Nat. Nanotech. 9, 372–377 (2014).

  18. 18.

    Kang, K. et al. High-mobility three-atom-thick semiconducting films with wafer-scale homogeneity. Nature 520, 656–660 (2015).

  19. 19.

    Yu, W. J., Chae, S. H., Lee, S. Y., Duong, D. L. & Lee, Y. H. Ultra transparent, flexible single walled carbon nanotube non-volatile memory device with an oxygen decorated graphene electrode. Adv. Mater. 23, 1889–1893 (2011).

  20. 20.

    Lee, S. et al. Impact of gate work-function on memory characteristics in Al2O3/HfOx/Al2O3/graphene charge-trap memory devices. Appl. Phys. Lett. 100, 023109 (2012).

  21. 21.

    Kim, S. M. et al. Transparent and flexible graphene charge-trap memory. ACS Nano 6, 7879–7884 (2012).

  22. 22.

    Bertolazzi, S., Krasnozhon, D. & Kis, A. Nonvolatile memory cells based on MoS2/graphene heterostructures. ACS Nano 7, 3246–3252 (2013).

  23. 23.

    Choi, M. S. et al. Controlled charge trapping by molybdenum disulphide and graphene in ultrathin heterostructured memory devices. Nat. Commun. 4, 1624 (2013).

  24. 24.

    Zhang, E. et al. Tunable charge-trap memory based on few-layer MoS2. ACS Nano 9, 612–619 (2014).

  25. 25.

    Vu, Q. A. et al. Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio. Nat. Commun. 7, 12725 (2016).

  26. 26.

    He, G. et al. Thermally assisted nonvolatile memory in monolayer MoS2 transistors. Nano Lett. 16, 6445 (2016).

  27. 27.

    Lee, H. S. et al. MoS2 nanosheets for top gate nonvolatile memory transistor channel. Small 8, 3111–3115 (2012).

  28. 28.

    Lee, Y. T. et al. Nonvolatile ferroelectric memory circuit using black phosphorus nanosheet-based field-effect transistors with P(VDF-TrFE) polymer. ACS Nano 9, 10394–10401 (2015).

  29. 29.

    JEDEC Solid State Technology Association Standard JESD79-2b 65 (2005);

  30. 30.

    Wachter, S., Polyushkin, D. K., Bethge, O. & Mueller, T. A microprocessor based on a two-dimensional semiconductor. Nat. Commun. 8, 14948 (2017).

  31. 31.

    Yu, L. et al. Design, modeling and fabrication of CVD grown MoS2 circuits with E-mode FETs for large-area electronics. Nano Lett. 16, 6349–6356 (2016).

  32. 32.

    Yan, R. et al. Esaki diodes in van der Waals heterojunctions with broken-gap energy band alignment. Nano Lett. 15, 5791–5798 (2015).

  33. 33.

    Hong, X. et al. Ultrafast charge transfer in atomically thin MoS2/WS2 heterostructures. Nat. Nanotech. 9, 682–686 (2014).

  34. 34.

    Ji, Y. et al. Boron nitride as two dimensional dielectric: reliability and dielectric breakdown. Appl. Phys. Lett. 108, 012905 (2016).

  35. 35.

    Mak, K. F., Lee, C., Hone, J., Shan, J. & Heinz, T. F. Atomically thin MoS2: a new direct-gap semiconductor. Phys. Rev. Lett. 105, 474–479 (2010).

  36. 36.

    Zeng, H. et al. Optical signature of symmetry variations and spin-valley coupling in atomically thin tungsten dichalcogenides. Sci. Rep. 3, 1608 (2013).

  37. 37.

    Liu, W. et al. Role of metal contacts in designing high-performance monolayer n-type WSe2 field effect transistors. Nano Lett. 13, 1983–1990 (2013).

  38. 38.

    Gong, C., Zhang, H., Wang, W. & Colombo, L. Band alignment of two-dimensional transition metal dichalcogenides: application in tunnel field effect transistors. Appl. Phys. Lett. 103, 053513 (2013).

  39. 39.

    Sarkar, D. et al. A subthermionic tunnel field-effect transistor with an atomically thin channel. Nature 526, 91–95 (2015).

  40. 40.

    Das, S., Chen, H.-Y., Penumatcha, A. V. & Appenzeller, J. High performance multilayer MoS2 transistors with scandium contacts. Nano Lett. 13, 100–105 (2012).

  41. 41.

    Xu, K. et al. Ultrasensitive phototransistors based on few-layered HfS2. Adv. Mater. 27, 7881–7887 (2015).

  42. 42.

    Shi, H. et al. Exciton dynamics in suspended monolayer and few-layer MoS2 2D crystals. ACS Nano 7, 1072–1080 (2013).

  43. 43.

    Imam, S. A., Deshpande, T., Guermoune, A., Siaj, M. & Szkopek, T. Charge transfer hysteresis in graphene dual-dielectric memory cell structures. Appl. Phys. Lett. 99, 082109 (2011).

  44. 44.

    Wang, H., Wu, Y., Cong, C., Shang, J. & Yu, T. Hysteresis of electronic transport in graphene transistors. ACS Nano 4, 7221–7228 (2010).

  45. 45.

    Late, D. J., Liu, B., Matte, H. R., Dravid, V. P. & Rao, C. Hysteresis in single-layer MoS2 field effect transistors. ACS Nano 6, 5635–5641 (2012).

Download references


This work was supported by the National Natural Science Foundation of China (61622401, 61734003) and the National Key Research and Development Program 2017YFB0405600. P.Z. thanks D. Sandubashao's group for encouragement and help, and P.F. Wang, F. Xiu, Q. Sun and N. Yan for assistance during device fabrication and for fruitful discussions.

Author information

P.Z. conceived the idea and supervised the experiments. C.L. performed the device fabrication and carried out the electrical characteristics measurements. X.Y. and X.S. provided valuable input to the overall experiments. S.D. and D.W.Z. provided input on the experiment conditions. C.L., D.W.Z. and P.Z. wrote the paper with help from all authors.

Competing interests

The authors declare no competing interests.

Correspondence to David Wei Zhang or Peng Zhou.

Supplementary information

  1. Supplementary Information

    Supplementary Figures 1–11, Supplementary Table 1, Supplementary References.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Further reading

Fig. 1: van der Waals heterostructures and 2D SFG memory.
Fig. 2: Two key design solutions (p–n-junction switch and controlled channel) to achieve 2D SFG memory.
Fig. 3: Demonstration of the ultrahigh-speed writing function of the 2D SFG memory.
Fig. 4: Memory performance under different operation modes.
Fig. 5: The state-1 decay rule and the quasi-non-volatile characteristics of the 2D SFG memory.
Fig. 6: Schematic illustrations of the mechanisms of 2D SFG memory.