A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

Abstract

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

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Fig. 1: van der Waals heterostructures and 2D SFG memory.
Fig. 2: Two key design solutions (p–n-junction switch and controlled channel) to achieve 2D SFG memory.
Fig. 3: Demonstration of the ultrahigh-speed writing function of the 2D SFG memory.
Fig. 4: Memory performance under different operation modes.
Fig. 5: The state-1 decay rule and the quasi-non-volatile characteristics of the 2D SFG memory.
Fig. 6: Schematic illustrations of the mechanisms of 2D SFG memory.

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Acknowledgements

This work was supported by the National Natural Science Foundation of China (61622401, 61734003) and the National Key Research and Development Program 2017YFB0405600. P.Z. thanks D. Sandubashao's group for encouragement and help, and P.F. Wang, F. Xiu, Q. Sun and N. Yan for assistance during device fabrication and for fruitful discussions.

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P.Z. conceived the idea and supervised the experiments. C.L. performed the device fabrication and carried out the electrical characteristics measurements. X.Y. and X.S. provided valuable input to the overall experiments. S.D. and D.W.Z. provided input on the experiment conditions. C.L., D.W.Z. and P.Z. wrote the paper with help from all authors.

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Correspondence to David Wei Zhang or Peng Zhou.

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Supplementary Figures 1–11, Supplementary Table 1, Supplementary References.

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Liu, C., Yan, X., Song, X. et al. A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications. Nature Nanotech 13, 404–410 (2018). https://doi.org/10.1038/s41565-018-0102-6

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