Power consumption of integrated digital devices sets the ultimate limit to downscaling and Moore’s Law1. Reducing power consumption has been thwarted by fundamental limits on the operating voltage set by thermionic emission2. For an ideal thermionic device, the dependence of current I on voltage V is expressed through the subthreshold swing SS = [dlog10(I)/dV]−1 = (kBT/q)log(10) ≈60 mV/dec at room temperature, where kBT is the thermal energy and q is the elemental charge.

Two-dimensional (2D) van der Waals (vdW) materials3,4 have been proposed for various schemes to overcome the thermionic limit (SS = 60 mV/dec) of metal-oxide-semiconductor field-effect transistors (MOSFETs) in nonconventional transistors such as TFETs, NC-FETs, and DS-FETs5,6,7,8,9,10,11,12,13,14. In particular, DS-FETs use the linear energy dispersion relationship of graphene, producing a super-exponential change in the DOS with energy15. As a result, DS-FETs have achieved a smaller SS than that of a MOSFET, with a large drive current11,12,13,14.

Integration of heterogeneous electronic components on a single low-power-consumption platform is highly desirable to enable applications such as the Internet of Things (IoT). Schottky diodes are important electronic components with low operation voltage and high current16, and have many useful applications such as rectifiers, mixers, selectors, switches, photodetectors and solar cells16. Although there has been considerable development of low-power transistors, steep-slope diode (or triode) rectifiers that overcome the thermionic limit (η < 1) of conventional diodes have not been proposed yet, but will be necessary for device integration with low-power transistors. Herein, we propose a DS diode as an essential element for low-power circuits. The DS injects cold electrons without a long thermal tail above the potential barrier in the channel (Supplementary Figure 1). Our DS diode consists of a graphene/MoS2/graphite heterojunction, where graphene acts as a cold electron injector, whereas the graphite/MoS2 interface provides a Schottky barrier for rectification. The MoS2 channel was chosen because of its high-gate tunability and mobility17. The minimum and average values of η for the DS diode are 0.78 and less than 1 over more than four decades of current at room temperature (ηave_4dec < 1), respectively, with a high rectifying ratio (>108).


Characteristics of Dirac-source diode

The DS diode device (Fig. 1a, b) consists of four components: (i) an n-type monolayer MoS2 channel (Supplementary Fig. 3), (ii) a graphene DS neutral at a zero gate voltage, (iii) a graphite drain-contact to form a Schottky barrier between the graphite and monolayer MoS2 for electrical rectification with a bias voltage, and (iv) metal (back, top, and control) gate electrodes to tune the Fermi levels of 2D materials. Two-dimensional van der Waals epitaxy was performed inside an Ar-filled glovebox until the heterostructure was encapsulated by hexagonal boron nitride (hBN) to avoid any contamination through air exposure or chemicals (Supplementary Fig. 2). Unlike a metal contact, a graphite contact with the monolayer MoS2 forms a non-reactive clean interface18 (Supplementary Fig. 4). Cr/Au electrodes were placed only in the region where graphite or graphene encapsulated by hBN exists.

Fig. 1: Device structure, characteristic curve, and band diagram of DS diode.
figure 1

a Optical image of graphene/MoS2/graphite heterojunction diode. Grey, red, and black dashed lines indicate graphite, monolayer MoS2, and graphene, respectively. We used graphene as a source and graphite as a drain. The top-gate(TG) and control-gate(CG) were placed for gate modulation of the MoS2 channel and graphene/MoS2 overlapped region, respectively. Scale bar, 5 um. b Schematic image of graphene/MoS2/graphite heterojunction diode. c Characteristic drain current(ID)-bias voltage(Vbias) curve in our device, which exhibits ideality factor(η) = 0.78 in 1 decade of current and an average η < 1 in more than four decades of current, i.e., ηave_4dec < 1. The rectifying ratio of our device is larger than 108. d Band diagram of DS Schottky diode, which explains the working principle of cold electron injection from graphene. EDirac, DOS, EFS, and EFD indicate Energy at the Dirac point, the density of states, Fermi level at the source side, and Fermi level at the drain side, respectively. Blue dashed line and green arrows indicate MoS2 energy window level and expression of rapid increment of current flow.

The diode has a local top-gate, control-gate and a global back-gate. The top gate only modulates the channel of the monolayer MoS2 band while the control-gate tunes the regions of the monolayer MoS2 channel and part of graphene overlapped with MoS2, respectively. The global back-gate affects the graphene/MoS2/graphite heterostructure. The gate-dependent electrical measurements (Supplementary Fig. 5) indicate that the Dirac point of hBN-encapsulated graphene is located at VBG=+1.9 V.

Figure 1c presents the characteristic drain current (ID) versus bias voltage (Vbias) curve for the DS diode at VBG = −6 V, VCG = 0 V and VTG = −0.7 V. At VBG = −6 V, graphene is p-type. When a bias voltage is applied to the graphene, electrons are injected from the p-type graphene source into the graphite drain. Note the electrons in the graphene source contributing to the current injection should have energy above the green dotted line (Fig. 1d) which is determined by the top of the MoS2 conduction band edge while not all the electrons above EF in graphene contribute to the current. The injected current density from graphene is given by:

$$J\left(E\right)\propto {M}_{0}\left|E-{E}_{D}\right|f(E-{E}_{{FS}})$$

Where \({E}_{D}\) is the Dirac point and \({E}_{{FS}}\) is the Fermi level of graphene. So, as the channel barrier gets lower than the Dirac point, availible density of states from graphene around E = Etop (Etop is the top of channel barrier) increases due to \({M}_{0}\left|E-{E}_{D}\right|\). So, injected current increased super-exponentially and the device works as a DS-FET. The electrical measurements reveal a nearly Ohmic graphene/MoS2 contact and a Schottky barrier of the graphite/MoS2 contact (Supplementary Fig. 6). When a negative back-gate voltage is applied, the Schottky barrier height increases and the device current is mainly modulated by the Schottky barrier at the interface between the graphite and monolayer MoS2. Although the Ohmic contact behaviour between graphene and monolayer MoS2 was observed in electrical measurements, to fully understand the band diagram at the graphene/monolayer MoS2 interface and its gate dependence, further studies are needed.

The performance of a Schottky diode is mainly characterised by two figures of merit. One is the rectifying ratio, which refers to the ratio between the on and off currents \(({{{{{\rm{R}}}}}}=\frac{{I}_{{on}}}{{I}_{{off}}})\), whereas the other is η, which is the slope representing the change in drain current with a bias voltage and can be obtained from the following Schottky diode equation:

$${I}_{{{{{{\rm{D}}}}}}}={I}_{{{{{{\rm{S}}}}}}}\left(1-{e}^{q{V}_{{{{{{\rm{bias}}}}}}}/\eta {k}_{{{{{{\rm{B}}}}}}}T}\right),$$

where q is the elementary charge, Vbias is the applied bias voltage, η is the ideality factor, kB is the Boltzmann constant, T is the temperature, and \({I}_{{{{{{\rm{D}}}}}}}\) and \({I}_{{{{{{\rm{S}}}}}}}\) are the drain and leakage currents, respectively. Equation (1) corresponds to SS = (ηkBT/e)log(10) hence values η < 1 correspond to SS below the thermionic limit. The characteristic curve at a negative gate voltage in Fig. 1b exhibits rectification behaviour with η < 1 observed over more than four decades of drain current, a minimum η of 0.78, and a large rectifying ratio (>108).

Steep-slope switching mechanism of Dirac-source diode

To explore the switching mechanism of the DS diode, we developed an analytical formula for the ideality factor and performed numerical device simulations (Supplementary Note 6). Both the two methods show that the ideality factor less than 1 is obtained in the DS diode due to the linear density of states of graphene. The switching slope of a diode is determined by the energy-dependent current density injected from an electrode, which is related to DOS and the distribution function. Graphene has a linear energy-dependent electronic DOS near the Dirac point, which is different from conventional metals with a constant DOS around the Fermi level. Therefore, the thermal tail of the Boltzmann distribution function is suppressed by the Dirac point tuned to the off-state region by doping. Namely, as the bias voltage is decreased on the graphene electrode as shown in Fig. 1d, the part of current density related to the distribution function is increased exponentially similar to conventional metals, which results in the ideal factor limit of 1. While, the injected DOS over the top of the channel barrier is also increased linearly from off-state to on-state, as shown in Fig. 1d. Therefore, the current is increased super-exponentially and the ideal factor below 1 is obtained in the diode with graphene electrode as the injection source.

Therefore, the switching slope of a diode, i.e. η < 1, is obtained in the diode with a graphene electrode as the cold electron injection source because of the linear DOS of the DS. Detailed simulation results are presented in Supplementary Fig. 7. Quantum transport simulations show that the DS diode has promising device performance. The ideality factor as small as 0.69 is obtained in the simulated DS diode and is less than 1 in more than five decades of current at room temperature.

The on-state current is larger than 103 μA/μm and the rectifying ratio is over 107.

Properties of asymmetric graphene/MoS2 and graphite/MoS2 contacts

Figure 2a presents the ID-Vbias characteristic curve of the DS diode at different back-gate voltages. For the DS diode to work as a diode, an asymmetric Schottky barrier height between the source and drain is necessary19,20,21,22. To satisfy this condition, we placed asymmetric graphene and graphite contacts with the monolayer MoS2 channel with gates. Without gate modulation, graphene has a work function of 4.3–4.7 eV from a monolayer to a few layers23,24,25. Because the work function of graphene (~4.3 eV) does not differ significantly from the electron affinity of MoS2 (~4.2 eV)26,27,28,29, the Schottky barrier height at the graphene/MoS2 interface is negligible, compared to the Schottky barrier height at the graphite/MoS2 interface. This also indicates that the Dirac point of pristine graphene is located near the conduction band edge of MoS2. As shown in Supplementary Fig. 10, in case of the metal/n-type semiconductor junction, the positive voltage on metal became forward bias. In our case, we applied bias voltage on the graphene side, and negative bias became forward bias, i.e., positive bias on the graphite side is forward bias, which indicates the Schottky barrier between the graphite/MoS2 junction is dominated in our device. Supplementary Fig. 6 indicates that the graphene/MoS2 device shows an almost Ohmic IV curve, whereas graphite/MoS2 does not show an Ohmic IV curve at room temperature. Figure 2a shows that as the gate voltage decreases, the rectification behaviour becomes dominant at negative gate voltages. As the back-gate voltage exceeds VBG > 0, non-diode ID-Vbias characteristic curves appear.

Fig. 2: Characteristic ID-Vbias curve for various VBG and its band diagram.
figure 2

a Characteristic ID-Vbias curve in the range of VBG = −10 to +60 V. As VBG decreases, change from non-diode to diode behaviour is observed. b Band diagram when VBG < 0 (diode regime). Owing to the larger work function of graphite than that of graphene, the device becomes a graphite/MoS2-interface Schottky barrier-dominant Schottky diode. c Band diagram when VBG > 0 (non-diode regime). As VBG increases, the work function of graphite decreases, and the Schottky barrier height of the graphite/MoS2 interface decreases.

To clarify the origin of the gate-dependent modulation of the ID-Vbias characteristic curves, we measured the modulation of the Schottky barrier height with back-gate voltages from the activation energy in the reverse bias regime. The Schottky diode equation (Eq. 1) can be rewritten as

$${I}_{D}=A{A}^{* }{T}^{\alpha }{e}^{-q{\Phi }_{B}/{k}_{B}T}\left({1-e}^{\frac{q{V}_{{bias}}}{\eta {k}_{B}T}}\right),$$

where A is the area of the Schottky junction, A* is the Richardson constant, α = 3/2 is an exponent for a two-dimensional semiconducting system30, kB is the Boltzmann constant, q is the elementary charge, T is the temperature and ΦB is the Schottky barrier height. When a large negative bias in absolute value is applied, i.e. \({e}^{q{V}_{{bias}}/{k}_{B}T}\) ≈0, the saturated drain current is proportional to \({T}^{3/2}{e}^{-{q\varPhi }_{B}/{k}_{B}T}\). The inset of Supplementary Fig. 11a shows a plot of ln(Isat/T3/2) versus 1/kBT in the reverse bias saturation regime (Vbias = +1 V). We extract ΦB for a given VBG from the slope of each curve. Supplementary Fig. 11a shows the Schottky barrier height obtained from the slope of each curve in the inset of Supplementary Fig. 11a. As shown in Supplementary Fig. 11b, in the highly positive VBG regime, the device shows an almost linear ID-Vbias curve, exhibiting nearly Ohmic contact behaviour (negligible Schottky barriers on both sides of the contacts, graphene and graphite with MoS2).

Dirac-source field-effect transistor measurement

To prove that the proposed diode is operated via cold carrier injection from a graphene DS at negative back-gate voltages, we measured the SS to determine if it showed sub-thermionic values. Supplementary Fig. 12b shows the characteristic ID versus control-gate voltage (VCG) transfer curve under the working conditions of the DS-FET, i.e. VBG < 0 V, where the graphene is p-type. When we apply VBG = −3 V, graphene slightly p-type. When the control-gate is placed on the MoS2 channel and the graphene/MoS2 overlapped region is swept from the off-state to the on-state, the DOS of the graphene increases according to the band diagram presented in Supplementary Fig. 12a, thereby operating as a DS-FET. As shown in Supplementary Fig. 12b, the SSave_1dec and SSave_3dec exhibits 53.6 and 58.75 mV/dec, respectively, which indicates that the proposed diode acts as a DS-FET owing to the linear energy dispersion relationship of the graphene-source electrode, resulting in a super-exponential change in the DOS. Both DS-FET and DS diode have the same origin for SS < 60 mV/dec and η < 1.

Steep-slope diode curves in the p-doped graphene region

Figure 3 shows the ID-Vbias characteristic curve in the steep-slope diode regime at VBG = −6 to −2 V in 2 V step with fixed top- and control- gate voltages (VTG = −0.7 V and VCG = 0 V), where the graphene is p-doped. In the measured regime, where the top of the Schottky barrier is located below the Dirac point of graphene, η of the device is less than 1 in more than four decades of current owing to the cold charge injection from the DS at a forward bias (Vbias < 0). The minimum η that we measured in one decade of current is 0.78. The red dotted line in Fig. 3 is an ideal diode curve (η = 1) in the forward bias direction. The DS diodes in these gate voltage regions show rectification ratios exceeding 108 at VBG = −6 V (>106 when VBG = −2 V and >107 when VBG = −4 V). We note that the device leakage current level is limited by the leakage currents (~10 fA) from the measurement equipment. Therefore, the reverse bias leakage current level from the diode should be lower than the measured values.

Fig. 3: Slopes of DS Schottky diode versus ideal diode and recorded ideality factor in 2D vdW material-based diode.
figure 3

Comparison of slopes between the DS Schottky diode and an ideal diode. Black and red dotted data represent those of the DS Schottky diode and an ideal diode, respectively. The Green dashed line indicates off-state current in the reverse bias regime. a DS Schottky diode curve at VBG = −2 V. b DS Schottky diode curve at VBG = −4 V. c DS Schottky diode curve at VBG = −6 V. The DS Schottky diode exhibits a ηave_3dec of 0.98, 0.95, 0.94 when VBG = −2, −4, and −6 V, respectively with fixed top- and control- gate voltage of VTG = −0.7 V and VCG = 0 V.


In conclusion, we successfully demonstrated the DS diode that operates based on cold charge injection from a graphene source owing to the linear DOS and a Schottky barrier at the interface between graphite and monolayer MoS2. As the linear DOS of the injected charges from p-type graphene over the top of the Schottky barrier between graphite and n-type monolayer MoS2 increases linearly from reverse to forward bias, an ideal factor below 1 is obtained in the diode with a graphene electrode as the injection source. Using gate modulation of the Schottky barrier height of the graphite/MoS2 junction, gradual switching between the diode and non-diode behaviours was also observed. The fabricated DS diode presents a minimum η as low as 0.78 in one decade of current, and it remains less than 1 for more than four decades of current at room temperature (ηave_4dec < 1), with a high rectifying ratio exceeding 108. Additionally, the device shows SS < 60 mV/dec for the same origin as that for η < 1. By using CVD-grown MoS2, graphene and graphite, integrated circuits using steep-slope DS-FETs and DS diodes can be fabricated in a large scale and pave the way for energy-efficient circuit technology.


Device fabrication

Supplementary Fig. 2 illustrates the fabrication of the Dirac-source (DS) Schottky diode. As can be seen, the first step involves the preparation of a polydimethylsiloxane (PDMS) stamp covered with a polycarbonate (PC) film on a glass slide. Subsequently, MoS2 flakes are mechanically exfoliated on a Si/SiO2 wafer. In this study, the MoS2 exfoliation was performed in an Ar-filled glovebox to prevent contamination. Using the standard dry-transfer method, each flake is picked up in the order—top hexagonal boron nitride (hBN), graphite, graphene, MoS2, and bottom hBN. After fabrication of the PC film and confirming sufficient adherence of the prepared flakes, the wafer was slowly heated to 90 °C, during which time, the sliding glass is slowly raised. During the pick-up process, owing to the large area of the top hBN, graphene, graphite, and MoS2 do not directly touch the PC film. After fabrication of the heterostructure on the PC film, the latter is slowly placed onto a prepared 285-nm-thick Si/SiO2 wafer. Subsequently, the wafer is heated to 180 °C, thereby melting the PC film. Thereafter, the PC film is successively washed using chloroform, acetone, and isopropyl alcohol (IPA). After transfer of the heterojunction to a new wafer, the device is exposed to chemicals to erase the released PC film. However, graphene, graphite, and MoS2 layers are encapsulated within large areas of the top and bottom hBN layers, which the chemicals cannot percolate. After fabricating the heterostructure on a 285-nm Si/SiO2 wafer, the standard e-beam lithography and plasma etching procedures are performed via e-beam deposition (Cr/Au = 5/60 nm) to place electrical contacts in the graphene and graphite layers. One-dimensional edge contact on graphene was formed in this process31. The hBN and graphite layers are etched using CF4/O2 and Ar/O2, respectively. Additional e-beam lithography and deposition processes are performed to facilitate top- and control-gate placement.


Supplementary Fig. 13 depicts the measurement protocol of the DS diode. Using the Keithley 6430, bias voltage was applied to the graphene electrode and measured the drain current from the graphite electrode. Keithley 2400 was used to apply a gate voltage to the Si back-gate electrode (VBG) and two Yokogawa 7651 were used to apply gate voltages to the top- and control-gate electrodes (VTG and VCG, respectively). Measurements were performed in a vacuum probe station with tri-axial cables to reduce leakage current from the measurement setup.