It is challenging for conventional top-down lithography to fabricate reproducible devices very close to atomic dimensions, whereas identical molecules and very similar nanoparticles can be made bottom-up in large quantities, and can be self-assembled on surfaces. The challenge is to fabricate electrical contacts to many such small objects at the same time, so that nanocrystals and molecules can be incorporated into conventional integrated circuits. Here, we report a scalable method for contacting a self-assembled monolayer of nanoparticles with a single layer of graphene. This produces single-electron effects, in the form of a Coulomb staircase, with a yield of 87 ± 13% in device areas ranging from < 800 nm2 to 16 μm2, containing up to 650,000 nanoparticles. Our technique offers scalable assembly of ultra-high densities of functional particles or molecules that could be used in electronic integrated circuits, as memories, switches, sensors or thermoelectric generators.
The assembly of molecules and nanoparticles (NPs) into nanoscale circuitry is a potential route to device miniaturisation1 and, as such, could help maintain the exponential increase in component densities. Furthermore, single-electron transport (SET), as realised in this way, can produce novel electronic behaviours that are desirable in commercial systems, such as negative differential resistance2,3. Such transport was demonstrated in scanning-tunnelling-microscope experiments on granular films4, which progressed to lithographically defined quantum dots (QDs) with adjustable tunnel barriers5. Separately, tunable barrier gates were added with an extra ‘plunger’ gate to control the number of electrons without changing the tunnelling probability6. These dots are too large to work much above 1 K, so self-assembled, nm-sized clusters7 and single-molecule junctions8,9 were investigated using scanning-probe techniques. However, the severe difficulty of contacting such small objects with a wafer-scale process has thus far prevented the integration of nanocrystals and molecules into conventional microelectronic circuitry.
The variety of electronic behaviour in organic molecules and NPs may enhance Si-based devices10: molecules or NPs used as functional components in microelectronics offer smaller, faster, more energy-efficient electronic and photonic systems. Single-molecule and single-NP junctions usually display much variability in their electrical responses11, owing to the many atomic-scale configurations available to them. The use of a self-assembled monolayer (SAM) of identical molecules allows one to average the variation due to the attachments of the molecules and hence arrive at repeatable electronic behaviour12. In addition, self-assembly can take place on Pt, which is compatible with CMOS processes. Whilst NPs have the advantage of being slightly bigger than molecules, and so are easier to contact or observe, their ~ 10% size variation can cause desirable electronic responses, such as Coulomb staircase, to be washed out in SAMs. Thus, most research studying these behaviours has addressed individual NPs, which is incompatible with mass-fabrication.
Nanogap junctions containing SAMs were fabricated using shadow evaporation13,14,15, mechanically controlled break-junctions16,17,18,19, electromigration20 and NP chains21. Other approaches focus on nanopores22, cross-wires23, direct metal transfer24, vacuum spray25, eutectic Gallium-Indium (EGaIn) liquid metal26 and vertical growth27,28. Whilst these processes successfully probe zero-dimensional electronic structure, each either measures the averaged electronic behaviour of many NPs/molecules or sacrifices potential parallel fabrication to measure just single-digit numbers of NPs/molecules. These are termed the “ensemble-molecule” and “single-molecule” regimes, respectively29.
Graphene as an electrode has been explored for both regimes. Such studies include scanning-tunnelling-microscope measurements of alkanedithiol molecules with single-layer graphene (SLG) as a bottom electrode30, laterally spaced SLG nanogaps31,32,33, and using graphene34,35, graphene oxide films36 and EGaIn37 as top electrodes to contact SAMs. The electronic properties of a SLG-sandwiched CdSe nanocrystal heterostructure have also been measured38. However, all of this research, so far, reports either the average of a large number of varied contributions, which is scalable, or single-molecule/NP behaviour, which is not.
Here, we present a SLG-covered SAM of NPs that produces functioning SET devices displaying a Coulomb staircase in their I–V characteristics with a yield of 87 ± 13%. The fabrication uses ensemble techniques, such as self-assembly, and layer-by-layer lithography, both of which are scalable. The devices work at temperatures up to at least 70 K and demonstrate unaltered electronic behaviour after a year stored in air at room temperature.
Device structure, fabrication and characterisation
Each device contains an array of double-barrier NP-molecule structures in parallel contacted between common source and drain electrodes (Fig. 1a,b,g). These are created by sandwiching a single layer of semiconducting PbS QDs between Au and SLG (grown by chemical vapour deposition, CVD, see Methods). The QDs are capped with insulating ligands and bonded to an alkanethiol molecule that is itself part of a molecular SAM assembled on the Au. This results in Au/tunnel barrier/QD/tunnel barrier/SLG junctions, thousands of which in parallel make up a device. SLG’s thinness, strength, flexibility, high electrical and thermal conductivity, impermeability to gases and ability to sustain large current densities39,40 ensure good electrical contact without the risk of shorting through or damaging the films, as is typically seen with top metal electrodes41,42. Moreover, CVD can produce wafer-scale sheets of SLG, allowing for scalable device fabrication43,44,45.
The procedure described in Methods produces ~1400 devices in each batch. We use a 1,6-hexanedithiol SAM (C6S2) to attach preformed colloidal oleic-acid-capped PbS QDs46 to an Au electrode and cover the resulting SAM with SLG (Fig. 4). ~10% of our devices short electrically, and 87 ± 13%, with areas less < 2 μm2, display Coulomb staircase47,48 (see Fig. 1e and its caption) when a voltage V is applied across the device (Fig. 2).
We first consider the fabrication variables that best predict the occurrence of Coulomb staircase, then we fit ~ 1000 I–V steps to gather step parameters and quantify the step variation within and across devices. We also perform combined ultrasonic force microscopy and atomic force microscopy (AFM), scanning electron microscopy (SEM) and transmission electron microscopy (TEM) to gain further structural information. All of this is used to explain why we see a consistently high yield of SET characteristics for device areas ranging from <800 nm2 up to 16 μm2.
Devices are fabricated on a SiO2-coated Si substrate in a 160 μm × 30 μm rectangular region at the centre of each sample (Fig. 1b, f). In this area, 39 devices are made simultaneously by patterning the SLG such that it only covers the tips of the 39 QD-coated Au electrodes (seen as vertical lines in Fig. 1b). Each fabrication cycle (batch) produces 36 samples (~1400 devices) but this can be scaled up to much larger numbers by increasing the wafer size. The SLG also makes direct electrical contact with three horizontal electrodes, positioned in the centre of the devices, that are left bare. In all other areas, the SLG lies on the SiO2.
By staggering the Au electrodes such that they span the possible positions of the etched SLG edge—produced by optical lithography (OL) misalignment (Fig. 1g)—a range of device areas can be obtained for a given sample that, in some cases, gives smaller areas than could have been produced with a non-stochastic approach, the goal being to minimise these areas and observe the most interesting electronic behaviour. In these OL samples, device areas range from 0.18 ± 0.16 to 18.3 ± 0.2 μm2. In one batch, additional electron-beam lithography (EBL) reduces areas further by up to a factor of 2500, resulting in samples with areas from <0.0025 to 2.15 μm2 (Fig. 1h).
Measurements and types of results observed
The devices are measured at 4.2 K. I–V curves are obtained with triangle bias sweeps that are repeated and slowly increased in magnitude until each device’s voltage limit is reached (see Methods).
Based on the I–V measurements, the devices are classified into five categories, each representing a distinct electronic behaviour: (1) repeated current plateaux (Fig. 2) (labelled ‘step curves’, StC), (2) no current plateaux and non-Ohmic conduction of a type normally seen in tunnel-barrier junctions26, where current is suppressed at low voltage, then increases rapidly at high voltage (see Supplementary Fig. 9b) (‘smooth curves’, SmC), (3) linear characteristics (see Supplementary Fig. 9a) (‘short circuits’, ShC), (4) no conduction (‘open circuits’), (5) junctions exhibiting erratic conduction above some threshold voltage (‘breakdown curves’). 4, 5 occur in <8% of the devices and are ignored as they likely result from random processing failures unrelated to the junction.
StC arise from QD Coulomb blockade and ShC from direct contact between SLG and Au electrodes (ShC have comparable resistances to ground contacts and devices in which the SLG is deliberately in direct contact with the Au: 1–730 kΩ with a mean ~54 kΩ). SmC are likely to be conduction through just the alkanethiol SAM because their shape and conductivities match control devices containing the C6S2 SAM only, without QDs, in which the junction structures take the form Au/C6S2/SLG (see Supplementary Fig. 9d). However, the SmC conductivity range overlaps that of the StC for both EBL and OL devices, implying that some of these SmC may arise from the blurring out of sets of steps from parallel QD double-barrier junctions (see Supplementary Fig. 9c).
A series of reproducible discrete steps in current as a function of source-drain voltage (Fig. 2) is a signature of SET and is termed Coulomb staircase47,48. Each current step occurs when the increasing bias enables one more charge carrier to occupy the QD, providing a step change in the number of states available for tunnelling out of the QD, and hence in the probability of tunnelling through it (Fig. 1e). Whilst Coulomb blockade can be observed when series tunnel barriers are approximately equal, Coulomb staircase requires asymmetric barriers so that multiple electrons or holes can accumulate in the QD, with low probability of tunnelling out and high probability of being replenished if they do. In our devices, the tightly packed C6S2 SAM provides a fixed covalently bonded barrier ~0.83 nm long between the Au and QDs (see Methods). The oleic acid molecules that coat the QDs provide the other tunnel barrier in the junction, bridging SLG and QDs via van-der-Waals bonding. As this barrier length is ~1–2 nm (see Methods), the asymmetric-barrier condition should usually be fulfilled.
Whilst grouping of the StC measurements seems justified based on curve type, there is a significant variation of electronic behaviour within the group. Step heights (ΔI) and the voltage increase required to induce successive current steps (ΔV) are not constant between or within devices (see Supplementary Figs. 3 and 5 and Supplementary Note 2). However, almost all Coulomb-staircase devices display a very high level of electronic stability. Some are swept hundreds of times and remain unaltered, save for minor lateral shifts in their traces (see Supplementary 6, 7 and Supplementary Note 2). After thermal cycling, i.e. warming devices up to room temperature and then cooling them back to 4K, devices often retain the electronic structure with only minor changes to the sizes of some curve features. The lack of periodicity in ΔV, combined with the variations described (see Supplementary Note 2), indicate multiple QDs conducting in parallel. Furthermore, the inhomogeneity of behaviours between devices implies that the double-barrier structures are not identical, consistent with the TEM in Fig. 4a–c.
Our measurements indicate that StC are a consequence of currents through individual QDs superposing in such a way that they do not mask one another. As the number of parallel conduction pathways becomes large, steps in the I–V characteristic may be washed out, which could cause QD transport to be mislabelled as SmC, but the similarity between the shapes of SmC and of the control set makes this unlikely. Washed-out StC are more likely to appear as low-quality staircases with faint undulations, as occasionally observed.
Since the clear Coulomb staircase in many devices must result from most QDs not contributing significantly to the current, we propose three mechanisms for reducing the number of active QDs. (1) The electron tunnelling rate through a thick barrier varies exponentially with its thickness. AFM imaging shows an Au surface roughness Rq = 1.1 nm and Ra = 0.82 nm, where Rq and Ra are the one-dimensional root-mean-square and arithmetic-mean roughness respectively (see Supplementary Fig. 8). TEM shows a normally distributed QD size range with mean 5.0 nm and standard deviation 0.8 nm (Fig. 4a–c). Such a spread, combined with SLG’s ability to remain suspended over micron-sized gaps50, results in a range of QD-SLG tunnel-barrier lengths51,52 (see Supplementary Note 3). The exponential dependence, combined with the variation in barrier lengths, reduces the number of QDs contributing to a device’s current. (2) Quartz crystal microbalance (QCM) experiments on the monolayer (Fig. 4e, f) and AFM imaging (Fig. 4i) show gaps between the QDs ~ 9 nm on average. This further reduces the number of QDs contributing to a device’s current, as SLG can bridge these gaps. (3) Water molecules or contamination during fabrication could lower the number of active QDs. Any dust or polymer resting on the assembly will render the QDs beneath inactive.
To further understand these data, hyperbolic tangent functions are fitted to all individual steps across all StC (see Supplementary Note 4). For the first positive and negative steps (those closest to the origin), ΔI increases as a function of device area (Fig. 3a–d). Since, as discussed above, the step is unlikely to include current contributions from many QDs, it is probably the result of larger areas containing QDs with smaller effective barrier lengths—QDs in the tails of this length distribution are more likely to be present in large-area devices. This correlation is clear when the data are separated by fabrication batch (collections of 36 samples) (see Supplementary Note 5).
The trends in ΔI vs area for each batch can be split into groups showing higher and lower step heights. These form distinct clusters in the plots and appear in all batches (see Supplementary Note 5). One possible explanation is that sometimes QDs can be pulled into fixed positions through the C6S2 SAM below, when under bias, making more direct contact with Au. This would reduce the effective barrier length of those junctions and increase ΔI. The problem with such an explanation is that it must be a consequence of some physical event, e.g. a less dense or thinner SAM region, itself associated with some finite probability per unit area of occurring. Thus, the high-conductance trend should appear more often in larger devices, though currently there is no sign of this.
The trapped-charge effects point to local electronic behaviour in the SAM, hence corroborating the claim that our procedure allows for single or low-number QD measurements in large-area devices. In addition, there is a correlation between differential conductance at zero bias (G0) and current step height ΔI (or the ratio of step height to the voltage at which the step occurs) (see Supplementary Fig. 2). Since G0 is a global property of a single device, which results from all contributions from every part of a device, and a current step corresponds to electrons in a single QD overcoming Coulomb blockade, this correlation means that these single QDs must provide most of the conductance at V = 0. A similar argument can be used when looking at the relation between G0 and the current and voltage values just before the first positive and negative steps (Vs, Is): G0 correlates well with Is/Vs (see Supplementary Fig. 2c). Furthermore, the fact that all qualities of StC fit into this pattern, even when there is only one step in the curve, is evidence that all devices behave similarly and show tunnelling through low numbers of QDs.
In summary, our hybrid technique combines top-down lithography with bottom-up NP/molecular assembly to produce wafer-scale compatible devices that reliably display single-electron effects. These devices do not require nanoscale electrodes or nanogaps to make contact with single or low numbers of NP/molecules in order to produce Coulomb staircase. Thus, they can be scaled using industrial fabrication methods. Graphene’s ability to bridge defects in the SAM and conform to dominant QDs is key to producing local electronic behaviour in devices containing thousands of chemically tunable electronic building blocks. The Coulomb-staircase profiles could be made more similar by narrowing the QD size distribution and flattening the bottom electrode topography; however, since a wide size distribution and variable topography may have the beneficial effect of reducing the number of active QDs in a junction, homogenising these could destroy the staircase behaviour. Indeed, there may be a sweet spot in between these competing effects. The use of layered materials as electrodes in molecular/NP SAMs paves the way to harnessing the single-electron effects in molecular/NP systems for memories, switches and sensors.
A 3 cm2 piece of SiO2/Si is used to produce 36 samples at once. Each contains 39 devices in its 160 μm × 30 μm central region, resulting in 1404 devices per batch. In principle, the entire process can be scaled up to larger dimensions.
The first stage is vacuum evaporation of the central Au regions. This produces all 1404 device electrodes, seen as vertical lines on a single sample in Fig. 1b, and three additional horizontal electrodes per sample for grounding. The smallest device, with a width ~0.8 μm, can be seen centrally on the top row. Similar processing is used to evaporate an outer region of electrodes that connect the central devices electrodes to bond pads on the perimeter of each sample.
In order to selectively chemisorb the C6S2 and assemble the QDs, OL is used (Shipley S1813 photoresist) to create a deposition window over the Au electrodes’ tips. The C6S2 and QD assemblies take place in an inert nitrogen environment to prevent QD oxidation. The samples are placed in a C6S2-anhydrous isopropyl alcohol (IPA) mixture with a concentration ~1 mmol/L for 24 h. Once removed, IPA is deposited, left for 10 s, and spun off the samples at 2000 rpm three times to remove loose C6S2 molecules. Immediately following this, the substrate is placed in a 1 mg/L colloidal suspension of PbS QDs dispersed in octane for another 24 h. After the QD assembly is finished, clean octane (without QDs) is deposited on the samples, left for 10 s and spun off at 2000 rpm three times to remove loose QDs. Immersion in a large beaker of acetone for 10 min removes the remaining polymer. This is replaced with IPA. Whilst remaining in the inert environment, the samples are lifted into a PMMA/SLG membrane that is floating in DI water.
SLG is grown by chemical vapour deposition on 35 μm Cu53. The as-grown film is characterised by Raman spectroscopy at 514nm with a Renishaw InVia spectrometer equipped with a 50 × objective, Fig. 5, with Cu photoluminescence removed54. The 2D peak ~ 2710 cm−1 is a single Lorentzian, a fingerprint of SLG55. The G peak at ~ 1591 cm−1 has full width at half maximum (FWHM) ~25 cm−1, while the 2D peak has FWHM(2D) ~36 cm−1. The 2D to G intensity and area ratios are I(2D)/I(G) ~ 2.2 and A(2D)/A(G) ~ 3.8.
To transfer SLG onto the target substrate, a PMMA layer is spin-coated on the SLG/Cu surface and then the whole PMMA+SLG/Cu stack is placed in ammonium persulphate or iron chloride for Cu etching44. The remaining membrane is moved into DI water for cleaning APS residuals. Samples are then lifted into the floating PMMA/SLG membrane. The transferred SLG is again characterised by Raman spectroscopy. The target substrate has a background luminescence (red line). When SLG is transferred, the background signal adds to the SLG spectrum (blue line). The D peak is negligible, indicating that the transfer process has not damaged the SLG. The positions of the G and 2D peaks are ~ 1592 cm−1 and ~ 2692 cm−1, respectively, with FWHM(G) ~ 16 cm−1 and FWHM(2D) ~ 35 cm−1, I(2D)/I(G) ~ 1.6 and A(2D)/A(G) ~ 4.2, indicative of ~ 300 meV doping56.
In both OL and EBL device fabrication the PMMA is removed from the SLG with acetone, followed by rinsing with IPA. For OL devices, optical resist is spun on SLG, and the entire area outside the central region is exposed and developed. This leaves a rectangle of resist over the central region covering just the tips of the Au electrodes. The positions of the tips are staggered across the likely positions of this rectangle’s edges, caused by alignment error, to minimise device areas on each sample after the exposed SLG is etched by oxygen plasma in a reactive-ion etching (RIE) machine (20 s at 10 W and 75 mTorr). The remaining SLG only contacts the Au electrode tips, where the C6S2 SAM and QDs are assembled, and the grounding electrodes.
For EBL devices, four thicknesses (40, 50, 60, 100 nm) of 950,000 molecular-weight PMMA in anisole (1:1) are spun on the SLG. This is done to capture the minimum EBL resolution when patterning the SLG top electrodes as these define device sizes. Deep UV lithography is used to remove all but a PMMA rectangle over the samples’ central regions much like on the OL samples, the difference being that these can be subsequently patterned with EBL. The PMMA development is in IPA:methyl isobutyl ketone:methyl ethyl ketone 15:5:1 for 5–10 s at 21 °C. The remaining PMMA is then patterned with EBL and the SLG is etched with RIE to create the smallest device areas in the dataset.
In both sample designs, final device areas are measured with either an SEM or an optical microscope. 18 devices of the 39 on each sample are selected for wire-bonding along with an additional 2 grounding electrodes. Control samples are fabricated with identical EBL and OL procedures but omitting the QD assembly.
Each sample package is attached to a dipstick and immersed in liquid helium to reduce the temperature to 4 K. I–V measurements are taken in triangle bias sweeps using a source-measure unit (Keithley 236) with a current resolution ~ 0.1 pA. The first sweep starts at 0 V, and is increased to ~ 0.1 V and then swept down to an equivalent negative voltage and finally back to zero. The magnitudes of these triangle bias sweeps are then increased in increments of 0.1–0.5 V until the extremely high electric field causes the device’s behaviour to become erratic.
The C6S2 hexanedithiol molecules in the dense SAM consist of six carbon units (C6) and two thiol terminal groups (S2) for anchoring to both QDs and Au. The inclusion of more than one thiol anchor allows for an alternative linking scenario where C6S2 is attached as a chelating ligand to the Au surface. This may preclude a direct covalent linkage to the QD, but our assembly process is designed to lower the occurrence of this binding mode. The weakly bound oleic-acid capping ligands prevent QD agglomeration in the octane. During assembly these are displaced locally through an exchange process to form chemical bonds between QDs and C6S2 molecules57,58. This immobilises the QDs and allows for the removal of any excess QDs, ensuring a monolayer (Fig. 4).
Using molecular modelling59, we estimate the S-to-S length of C6S2 to be 0.94 nm. Alkanethiolate SAMs assembled on Au are reported to have a typical tilt angle of 28∘ with respect to the surface normal49. This allows us to estimate the film thickness to be ~ 0.83 nm. When C6S2 molecules replace the oleic acid ligands that surround the PbS QD, free S atoms at the surface of the C6S2 SAM bond to the QD’s surface anchoring it to the substrate, and allowing the formation of a QD SAM. The oleic acid itself provides the other tunnel barrier in the junction separating the QD and the SLG. In 6 nm PbSe QDs, it has been reported that oleic-acid molecules conform in such a way as to produce a capping layer of thickness ~ 1 nm, despite having an isolated length ~ 2 nm60. These ligands behave similarly with PbS QDs, so the asymmetric-barrier condition should often be fulfilled.
AFM with mechanical scraping
The selective formation of the QD SAM is confirmed by a mechanical cleaning process that uses an AFM tip to sweep away the assembly in specific device regions, so a height difference can be measured61,62,63 (Fig. 6). A small area of the SAM is scanned repeatedly (16 times) in contact mode at high force (30 nN), then scanned over a larger area at low normal force (2 nN). A clean ‘window’ is observable in the small high-force-scanned region where the SAM is scratched away so its height can be determined (5.1 ± 0.9 nm). This matches the TEM measurements (Fig. 4) of the diameters of the NPs. Scanning is repeated in areas where no SAM is expected to form, due to photoresist protection during assembly. A height difference of 1.3 ± 0.4 nm is measured (21 sweeps).
Quartz crystal microbalance
A QCM is used to measure the surface functionalisation of the Au electrodes. When an alternating voltage is applied to two electrodes of known geometry sandwiching a quartz plate, the current response has a resonant frequency. This is shifted by the deposition of a film on the electrodes’ surfaces and can be measured by a frequency counter. The linear relation between the observed frequency shift and mass deposited is given by the Sauerbrey equation64:
where Δf is the frequency shift, f0 the resonant frequency, Δm the mass deposited, A the area of the electrode on the QCM, μq the shear modulus of quartz, and ρq the density of quartz. In our system, with a 10 MHz QCM, the relation between frequency shift and mass per unit area is:
The frequency shift after the self-assembly of C6S2 on the QCM’s Au electrodes is ~ − 58.3 Hz, corresponding to a packing density ~ 5.19 molecules/nm2. After the QD assembly, this is ~ − 135.6 Hz, representing a mass-per-unit-area gain of ~ 3.0 × 10−12 ng nm−2. Using the size distribution obtained through TEM, and assuming an OA ligand packing density ~ 4 nm−2 on the QDs’ surface, we estimate the average QD mass ~ 6.4 × 10−10 ng. From this we deduce a coverage ~ 5.0 × 10−3 nm−2 and an average centre-to-centre distance between neighbouring QDs ~ 14.1 nm, and 9.2 nm surface-to-surface. The poor mechanical coupling between the heavy QDs and the substrate means that QCM may underestimate the QD number density so the gaps may be smaller than this.
Au substrates are prepared using standard template-stripping recipes65,66. Thermally evaporated Au on SiO2/Si is transferred onto a second SiO2/Si wafer using epoxy to create an Au surface with roughness ~ 0.15 ± 0.2 nm. The self-assembly recipe is used to create the QD SAM. Contact-mode AFM with a NuNano Scout 70 tip is then used to resolve the QDs (Fig. 4e,f). These appear wider than expected due to a common artefact of AFM imaging which exaggerates the lateral dimensions of nanoscale protuberances67.
Data associated with this work are available68.
Scripts for analysing the data associated with this work are available68.
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We thank Yiqing Jin, Antonio Lombardo and Angelo Di Bernardo for experimental help in the early stages of the project, James Xiao for discussion regarding quantum-dot chemistry, Xintai Wang for SAM characterisation, and Richard Langford and Jon J. Rickard for electron-microscopy support. This work was supported by UK EPSRC grants EP/P027172/1, EP/K01711X/1, EP/K017144/1, EP/N010345 /1, EP/K016636/1, EP/N010345/1, EP/L016087/1, the EU Graphene and Quantum Flagships, ERC grants Hetero2D and Minergrace.
The authors declare no competing interests.
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Fruhman, J.M., Astier, H.P., Ehrler, B. et al. High-yield parallel fabrication of quantum-dot monolayer single-electron devices displaying Coulomb staircase, contacted by graphene. Nat Commun 12, 4307 (2021). https://doi.org/10.1038/s41467-021-24233-2