## Introduction

Semiconductor nanowires exhibit superior and configurable electronic and optical properties1,2. Their disruptive potential has been demonstrated in photonics3 (e.g. for lasers4 or quantum optics5), electronics6, thermoelectricity7, energy storage with batteries8, gas9 and mechanical10 sensing, topological quantum states11, and much more. For these reasons their growth has been tackled with a plethora of techniques aiming at the production of controlled, ultra-long structures matching the needs of high yield, scalability (e.g. integration of a large number of devices on the same monolithic nano-wire) and material quality (e.g. smooth interfaces).

As such, the range of available approaches to grow elongated crystalline structures steadily increases1, from direct top-down design, as, e.g., three-dimensional mesoscale lithography12, superlattice nanowire pattern transfer13 up to the exploitation of natural phenomena such as the renowned Plateau-Rayleigh instability14. Several bottom-up, self-assembly methods can be employed to obtain high-quality parallel wires15. Nevertheless, a full control over their morphology, size, position, direction, inter-connection, and electrical isolation remains a challenge as current techniques are not versatile and are limited to a few micrometers length. On the other side, lithographic top-down methods can be used to precisely prepare a substrate for further engineering, as for instance shown for the cases of controlled wetting16 or nano-imprint lithography17. Hybrid top-down/bottom-up approaches18,19,20,21 can marry the crystalline quality of epitaxial self-assembly with the ultimate control of nano-structures position and size and create quantum-grade materials, such as complex assemblies of connected wires and membranes. However, their exploitation in scalable devices is often hindered by the complexity of their implementation requiring too many, cumbersome nano-fabrication steps. In fact, these approaches often need high-resolution etching (e.g. in order to set the final size of the epitaxial structures) and provide out-of-plane objects eventually requiring further processing before their implementation in a device18,22. These methods are hardly scalable as they exploit complex epitiaxial growth steps, often involving a metallic catalyst and are limited to structures extending only over a few micrometers.

Here we fabricate arrays of in-plane, ultra-long nano-wires (up to 0.75 mm) and complex inter-connected circuits of monocrystalline silicon using a catalyst- and epitaxy-free, hybrid top-down/bottom-up approach based on the natural morphological evolution of thin solid films. We control the metamorphosis of a commercial (001)-oriented ultra-thin silicon film on insulator (UT-SOI) relying only on low-resolution etching and annealing, directly transforming it in monocrystalline nano-wires. The final structures have a lateral size up to five times smaller than the etched patch width, are obtained with size- and position-control and are electrically-isolated from the substrate. Phase field simulations of surface-diffusion-limited kinetics elucidate the key role of the surface-energy anisotropy in stabilizing the dewetting outcome against breaking. They quantitatively reproduce the main features of the morphological evolution of the patches.

Exploiting the orientation-dependent edge faceting promoted by surface energy minimization23 which hinders the onset of the typical Rayleigh-like instability along the wire axis24 we extend these results to arbitrary in-plane crystallographic directions, building complex circuits of wires featuring splitting, changes in their directions and inter-connections. Finally, with a simple spin-on-dopant post-fabrication method, we render the wires conductive, demonstrating the possibility to use them as field-effect transistor6 with trans-conductance and electron mobility similar to state-of-the-art nanowires devices.

## Results

### Templated dewetting along stable dewetting fronts

Dewetting of monocrystalline thin silicon films is a spontaneous phenomenon where capillary forces drive mass transport via surface-diffusion-limited kinetics25,26. It leads to a complete metamorphosis of the flat layer in three-dimensional structures through hole nucleation, rims formation (where mass accumulates while receding), followed by finger-like structures and finally, in isolated islands. This natural shape evolution can, however, be controlled by engineering the dewetting fronts by patterning the UT-SOI prior to annealing27,28.

Although silicon dewetting is also possible starting from an amorphous UT-SOI29,30, the need of a precise and controlled dewetting front in order to form regular nano-architectures requires mono-crystalline wafers where the dewetting process only affects the shape of the layer which always remains a mono-crystal31,32,33. The potential of templated dewetting was showcased for a mono-crystalline 12 nm thick UT-SOI where, in analogy with metals34, arrays of complex nano-architectures of islands and wires (hundred nanometer high and few micrometer long, circa) were reported28. The key tool used to enhance the stability of the dewetting outcome against breaking leading to reproducible patterns was the creation of ad hoc dewetting fronts triggering the formation of opposite rims that move one towards the other. So far, this approach was limited to patches extending over a few $$\upmu$$m (aspect ratio $$\sim$$1/400) and, due to the anisotropy of surface energy, strictly oriented along the stable dewetting fronts (e.g. [110])28.

Following this concept, we tested the stability against annealing of a 12 nm thick UT-SOI (at temperature between 720 and 775 $${}^{\circ }$$C, for periods ranging from 15 min to 2 h) patterned by electron-beam lithography and reactive ion etching in long trenches with variable pitch ($${d}_{{\rm{LL}}}$$ = 0.5 up to 4 $$\upmu$$m) defining patches featuring a width $$w$$ ranging from $$\sim$$400 nm up to $$\sim$$3.8 $$\upmu$$m. We first consider patches oriented along the stable dewetting front [110] (Figs. 13). Figure 1a describes the method while a more detailed description is provided in the Methods section and reference28.

In optimized conditions (annealing temperature and time, and patterns width) we observe the formation of extremely long wires, with a length limited only by the patch design (up to 0.75 mm, Fig. 1b, c and high-resolution Supplementary Data 1). Wires with no breaks and perfectly homogeneous height and width over their full length can be formed with a 100$$\%$$ success rate. All the UT-SOI available in the patch ($$w$$ = 700 nm) collapsed in individual wires featuring a base of about 160 nm ($$\sim$$4 times smaller than $$w$$) and a height of 50 nm. In these conditions of annealing temperature and time, a simple stable dewetting front freely receding (semi-infinite UT-SOI) covers a distance of about $$\Delta x$$ = 650 nm (bottom-right inset in Fig. 1b), a length comparable to the overall patch width $$w$$.

In a similar sample, $$\sim$$0.9 and $$\sim$$1.9 $$\upmu$$m wide patches ($${d}_{{\rm{LL}}}$$ = 1 and 2 $$\upmu$$m, respectively) collapsed in an individual wire, whereas $$\sim$$3.9 $$\upmu$$m patches ($${d}_{{\rm{LL}}}$$ = 4 $$\upmu$$m) were partially dewetted in two parallel counter-propagating rims, as revealed by AFM measurements (Fig. 2a–d). These features are attributed to a faster dewetting dynamics (and in turn to an earlier onset of the morphological instabilities) associated to smaller radius (i.e. larger curvature at the surface35,36) even when considering a film in contact with a substrate37,38,39,40: the dewetting process for the larger pitches (lower overall curvature with respect to smaller pitch), is not concluded at the end of the annealing step. It is worth noting that, although the process for $${d}_{{\rm{LL}}}$$ = 1 $$\upmu$$m is faster than that one relative to $${d}_{{\rm{LL}}}$$ = 2 $$\upmu$$m, also in the former case the wires did not yet break into islands (the Plateau-Rayleigh instability along the wire did not take place).

In all investigated cases, the fluctuations around the average full width at half maximum (FWHM) and heights of the wires were only a few nanometers (Fig. 2f–g) accounting for the remarkable control of the dewetting process. We also observe that for longer annealing time and higher temperature, patches of any width produced isolated islands (eventually elongated), as expected from the conventional Plateau-Rayleigh instability (not shown)14.

### Phase field simulations

The former results are compared to 2D phase field simulations of surface diffusion41,42, including surface-energy anisotropy43,44 solved by a finite element approach45,46 (see the Supplementary Note 1 for more details on the simulation method in use). They are performed mimicking the evolution in time of the cross-section of the experimental cases (Fig. 3, Supplementary Movies 16). For each investigated aspect ratio ($$h/w$$ = 1.2/100, 1.2/200 and 1.2/400) we reproduce the dewetting dynamics, including the typical facets of the equilibrium shape of Si ({$$001$$}, {$$113$$}, {$$111$$}, and {$$110$$}) by means of the corresponding surface-energy values47,48 (Fig. 3 a–c, left panels). We systematically compare these results with the isotropic counterpart, by averaging the energies of different orientations (Fig. 3a–c, right panels).

The relevant features emerging from this analysis are summarized as follows:

1. (i)

For simulations reproducing $$h/w$$ = 1.2/100 and 1.2/200 (corresponding to $${d}_{{\rm{LL}}}$$ = 1 $$\upmu$$m and 2 $$\upmu$$m, respectively Fig. 3a, b, left panels), the patch effectively collapses in a single wire, directly reproducing the corresponding experiments (Fig. 3d, left and central panels), thus providing a confirmation of the diffusion-limited kinetics at play. Discrepancies between experiments and theory for $${d}_{{\rm{LL}}}$$ = 1 $$\upmu$$m can be attributed to convolution effects with the AFM tip leading to an overestimation of the wires FWHM also reflected in the large discrepancy between the wires width shown in Figs. 1c, 2e.

2. (ii)

The simulations for $$h/w$$ = 1.2/400 (corresponding to $${d}_{{\rm{LL}}}$$ = 4 $$\upmu$$m, Fig. 3c, left panel) show first the formation of two parallel, counter-propagating rims, leading finally to a breakup in two parallel wires as final stage (not observed in the experiment, as the dewetting process is not complete, Fig. 2c). A good agreement with experiments is found when focusing on the intermediate time steps (Fig. 3d, right panel).

3. (iii)

Surface faceting is found to play a central role in determining a quantitative outcome of the process49. For $$h/w$$ = 1.2/100 a single wire is obtained with and without anisotropy, whereas the case $$h/w$$ = 1.2/200 deviates from experiments, providing two parallel wires as final state of the process, when neglecting preferential orientations (Fig. 3b, right panel). Also for larger patches ($$h/w$$ = 1.2/400, Fig. 3c, d, right panel) the isotropic case predicts three islands against the two found in the anisotropic case, confirming the tendency of the surface anisotropy forces to stabilize the patch against break-up.

4. (iv)

For the largest patch, the experimental rims are smaller than the prediction by phase field simulations and the valleys next to the rims are not visible. This feature is attributed to an effective larger stiffness/anisotropy of the real structures with respect to those considered in these simulations. This could be readily accounted for by phase field simulations50 at the cost of a significant increase in the computational budget without however, delivering relevant, additional information than those discussed so far.

### Templated dewetting along arbitrary fronts

In a different sample, similar patch arrangements are etched with a slight mis-cut of 2° circa, with respect to a stable dewetting front. We now consider patches size of 800 nm in width ($${d}_{{\rm{LL}}}$$ = 1 $$\upmu$$m, Fig. 4a).

The mis-cut does not impede the formation of well-ordered arrays of parallel and uniform wires, mostly intact and following the macroscopic direction imposed by the etching. Small kinks are formed during edge retraction in analogy to what was observed in the metallic counterpart23,51,52,53. However, in our case, the periodicity of the edge undulation of the Si film is not as regular as those found in metals and is linked to the presence of small tips at the BOX surface (highlighted by white and yellow arrows in the bottom panel of Fig. 4a) on the denuded BOX and at the sides of the wires, where they touch the BOX (these are also found in spontaneously dewetted samples and are thus not attributed to the lithographic process, see the Supplementary Note 2). All the kinks form in presence of an impurity at the wires/box interface (yellow arrows in the bottom inset of Fig. 4a) whereas in some cases only a wrinkling of the {$$113$$} and {$$111$$} facets is observed (white arrows in the bottom inset of Fig. 4a). The top {$$001$$} facet is instead always flat.

The mechanism illustrated in Fig. 4a helps in setting arbitrary orientations of the etched profile and obtaining slightly curved structures. This can be expanded to more complex patterns leading to connected networks of wires. We address this point by etching parallel patches (700 nm large and 33 $$\upmu$$m long) and studying the effect of their orientation with respect to the crystallographic axes on the stability against breaking (Fig. 4b). Between the patches (etching highlighted by yellow areas in Fig. 4) we added several connectors with variable size and respective alignment. This design is repeated with 15° steps with respect to the [110] direction in order to cover 360° (Supplementary Note 2 and high-resolution Supplementary Data 27).

As found for metals23,51 we observe a general tendency to more frequent break-up of the patches along the unstable axis [100] whereas along the stable one [110] we find one individual, elongated island as previously shown for simple wires (Supplementary Note 2 and high-resolution Supplementary Data 2). Nonetheless, for short enough annealing time, well connected structures featuring a limited number of breaks can be found in a large range of patch orientations. Up to 15° with respect to [110] the structures are not broken along the wires nor at the level of large and small connectors (respectively 1.5 $$\upmu$$m and 0.8 $$\upmu$$m wide, Fig. 4b). Finally, for the larger connectors the structure is robust against breaking up to 45° (high-resolution Supplementary Data 27).

This demonstrates that it is possible to control the continuity, connectivity and curvature of the wires up to several degrees of misalignment with respect to the stable dewetting front without any optimization. A more appropriate choice of etching design and experimental conditions (e.g. annealing time, patch width and shape as well as ad hoc additional features etched within28) may improve the quality of the final outcome.

### Crystalline structure of templated dewetted wires

In order to rule out the presence of crystalline defects in the dewetted structures we performed atomic-resolution scanning transmission electron microscopy (STEM) imaging on a wire (Fig. 5). In line with previous evidences in Si- and SiGe-based islands27,31, we observe the typical crystalline structure of bulk Si and the absence of extended dislocations. A slight crystalline disorder can be observed in some part of the wire body, at the interface with the original UT-SOI substrate (at about 12 nm from the BOX, Fig. 5c, d). This feature has been previously observed in STEM images27,31 and we ascribe it to residual defectivity on the UT-SOI substrate, possibly due to a non ideal cleaning of the surface. For the sake of thoroughness we mention that geometric phase analysis performed on the full wire section does not reveal any strain in the crystal structure (not shown).

### Electric conduction from parallel wires arrays

Through the templated dewetting process we demonstrated crystalline silicon wires formed directly on an insulating substrate. To show the potential of these structures for electronic circuits a doping procedure involving phosphorus spin-on-dopant (SOD) deposition and rapid thermal annealing treatment has been carried out on 70 $$\upmu$$m long nanowires (base size $$\sim$$150 nm, height $$\sim$$75 nm) to render them conductive (Fig. 6 and Methods)54. All metal contacts (source, drain and gate, respectively S, D, and G) are 130 nm thick gold and were placed by e-beam deposition on 15 parallel nano-wires. S and D partially wet the silicon wires whereas G is separated from the wires by a 100 nm thick silicon dioxide (deposited via e-beam evaporation) covering the wires for about 30 $$\upmu$$m (Fig. 6). The oxide leakage characteristics is about 10 pA (not shown).

S-D current curves as a function of the S-D voltage are registered for different G voltages, demonstrating a typical behavior of a field-effect transistor (FET). This transistor works in enhancement mode, where the saturation and the S-D voltage are characteristic of a n-channel FET55. From the I–V curves obtained on 15 parallel nanowires for different G tension, we estimate a trans-conductance ($${G}_{{\rm{NW}}}$$ = $$\Delta {I}_{{\rm{SD}}}/\Delta {V}_{{\rm{G}}}$$, where $$\Delta {I}_{{\rm{SD}}}$$ is the source-drain current modulation against the corresponding change in gate tension $$\Delta {V}_{{\rm{G}}}$$) of the order of $$\sim \upmu$$S per wire (Fig. 6).

Adopting the common approximations for nanowire-based transistors56 and neglecting spurious effects57, we can estimate the electron mobility with the formula $${\upmu }_{{\rm{e}}}$$ = $$({L}^{2}{G}_{{\rm{NW}}})/({V}_{{\rm{SD}}}{C}_{{\rm{NW}}})$$, where $$L$$ is the gate contact length, $${V}_{{\rm{SD}}}$$ is the source-drain tension and $${C}_{{\rm{NW}}}$$ is the gate capacitance. In a cylindrical geometry, this latter characteristic can be expressed as $${C}_{{\rm{NW}}}$$ = $$2\pi {\epsilon }_{{\rm{0}}}{\epsilon }_{{\rm{r}}}L/{\mathrm{cos}}{h}^{-1}(t/R)$$, with $${\epsilon }_{{\rm{0}}}$$ vacuum permittivity, $${\epsilon }_{{\rm{r}}}$$ the static dielectric constant of the gate oxide, $${t}_{{\rm{tot}}}={t}_{{\rm{ox}}}+R$$ distance between wire center and metallic contact, where $${t}_{{\rm{ox}}}$$ is the oxide thickness ad $$R$$ the wire radius. Assuming $${\epsilon }_{{\rm{r}}} \sim$$ 3.9, $$L \sim$$ 30 nm, $${t}_{{\rm{ox}}} \sim$$ 100 nm, $$R$$$$\sim$$ 60 nm (estimated as average between height and base size), we obtain a gate capacitance $${C}_{{\rm{NW}}} \sim$$ 5 fF. With these values, we can roughly estimate an electron mobility ranging between 0.5 and 5$$\times$$10$${}^{3}$$ cm$${}^{2}$$ V$${}^{-1}$$s$${}^{-1}$$.

## Discussion

There are several differences and advantages of our wires with respect to previous demonstrations of similar structures implemented via dewetting and other fabrication techniques, particularly regarding the simplicity and versatility of implementation, improved comprehension of the dewetting mechanism and improved quality of the structures enhancing the electrical properties of the implemented devices. In what follows we discuss all these features with respect to the existing state-of-the-art.

In this work, we extend the coherent control of dewetting by more than 2 order of magnitude, going from patches of a few $$\upmu$$m28 to 0.75 mm (only limited by the pattern etched prior to annealing set by the writing field of the e-beam lithography in use). This is a record aspect ratio of a $$\sim$$1/60000 patch providing uniform and reproducible nanowires. In optimal annealing conditions and patch size we obtain a 100$$\%$$ success in forming perfect faceted nano-wires with no breaks along their length and size fluctuations in the few per cent range.

An important difference with respect to previous reports of Si dewetting28 is the control of patch evolution for patterns oriented along unstable fronts. The formation of kinks during dewetting (mediated by small defects at the BOX/wire interface) allows to adjust the macroscopic directions of the final structures without breaking. This feature has never been reported so far in semiconductor dewetting and it allows to curve, split and connect the wires ad libitum in order to form complex circuits.

The limit of this method is evident when considering patches larger than a few $$\upmu$$m. Although the fluctuation of the wires width and height is always well below 10$$\%$$, larger patches (d$${}_{{\rm{LL}}}$$ = 4 $$\upmu$$m, Fig. 2) provide wires showing a spread of their width about three times larger than those formed from smaller patches (d$${}_{{\rm{LL}}}$$ = 1 and 2 $$\upmu$$m, Fig. 2). This lower level of control over the rim evolution for larger structures was reported for the case of simple square patches28: above 3 $$\upmu$$m, disorder effects play an important role leading to marked deviations of the dewetting dynamics with respect to what expected for ideal systems (as those shown in the simulations, Fig. 3 and reference28). These spurious effects could be attributed to extrinsic disorder locally perturbing the rim evolution and affecting in a more marked way larger patches with respect to smaller ones (e.g. native oxide not properly removed or other impurities present in the ultra-high vacuum used for silicon dewetting). Furthermore, small tips found at the rim/BOX interface can perturb the dewetting dynamics28. Thus, although these defects allow the formation of kinks along the wires and thus to curve them with respect to the preferential axes orientations, they may be a limit for a coherent control of larger patches (e.g. those that would result in two parallel wires instead of an individual one). In the present case of 12 nm thick UT-SOI, a coherent control of the patch evolution (in absence of additional features in the initial patch design) is limited to <3 $$\upmu$$m.

In the present work, we also managed to compare real systems with realistic models taking into account anisotropic surface diffusion. So far, simulations of templated dewetting of UT-SOI based on a phase field approach considered patches featuring an aspect ratio of, at most, 1/16028. This was in stark contrast with the real systems featuring a much smaller value of $$\sim$$1/400. Furthermore, this attempt to reproduce the experimental outcomes did not take into account the underlying crystal anisotropy. A reasonable agreement between experiments and simulations was found for short time evolution while showing marked discrepancies for longer times. More generally, in the last few years several theoretical works tried to tackle the anisotropic dewetting dynamic with sharp interface models for both cases of weak58 and strong50 anisotropy. However, in all these cases the patch aspect ratio was at most 1/60 which is pretty far from the actual experimental conditions used for metal and semiconductor dewetting. Here we used a phase field model taking into account surface diffusion and surface-energy anisotropy for a 1/1 scale case (aspect ratio up to 1/330).

Our novel theoretical understanding of the anisotropic dewetting problem allows therefore to correctly predict long-time evolution of the main features observed in experiments showing that the presence of facets (due to anisotropic surface energy) stabilizes the dewetting outcome against breaking. Isotropic models (e.g. showing two parallel wires instead of only one) fails in this task, at least for larger patches.

From a fabrication standpoint our approach offers several advantages with respect to other bottom-up methods. We implemented our wires on commercial UT-SOI wafers, available in a large set of device thickness, orientation, doping, composition (e.g. SiGe and Ge on insulator), BOX thickness, and up to 12 inches in size. These features are not matched by other methods implemented on, at most, a few inches and expensive epilayers19,20,21 (e.g. for III–V-based structures).

Our structures are implemented only in two steps, etching and annealing. Thus, templated dewetting of wires offers a versatility in directions, splitting and connections not attainable with catalyst-based approaches for in-plane wires growth59 (where all the structures were parallel) and an easier implementation with respect to recent demonstrations were the wires were bound together with complex patterning and epitaxial nano-fabrication methods18,19,20,21,22,60,61 (eventually requiring cumbersome post-growth processing for the implementation of an electronic device).

Other self-assembly methods are not suitable for the formation of crystalline structures on amorphous SiO$${}_{2}$$. Bottom-up methods for semiconductor-based 3D structures rely on strain-induced assembly (e.g. via Stranski Krastanov for III–V and IV–IV)62, droplet epitaxy and droplet etching (only for III–V)63, vapor-liquid-solid growth via gold catalyst59, or more advanced hybrid top-down/bottom-up approaches19. All these strategies can be exploited only when a precise epitaxial relation holds between the substrate and the deposited material. As such, they require a crystalline support. In contrast to this, we directly produce well-ordered, monocrystalline nano-architectures on amorphous SiO$${}_{2}$$ without any epitaxial relation. A straightforward consequence is that silicon dewetting provides electrical isolation of the three-dimensional nano-achitectures from the substrate, a clear advantage for the implementation of electronic devices (e.g. the field-effect transistors shown here) with respect to recent in-plane nano-architectures epitaxially grown on a III–V substrate18,21 that becomes insulating only at very low temperature19. Another important difference between dewetting and recent reports of advanced epitaxial structures based on selective area growth, is the lack of strain and alloy disorder that is known to complicate the interpretation of the device behavior19,20.

The width of our wires is 4–5 times smaller than the initial patch width, implying that a low-resolution etching (e.g. based on optical or nano-imprint lithography) can in principle be exploited. This constitutes an advantage with respect to current hybrid top-down/bottom-up approaches, where the resolution of the lithography directly sets the final size of the structures19,21. In this respect, it is worth stressing that a high resolution for electron-beam lithography inevitably requires a reduced writing field, limiting the size of nanowires to rather short channel length (a few $$\upmu$$m for both top-down57,64 and bottom-up18,19,20,21 approaches). In our case, a low resolution allows for mm scale structures providing an aspect ratio of the order of 1/10$${}^{4}$$.

Our approach allows to tune the wires height on the same substrate in contrast with top-down approaches that lead to structures with a height fixed by the thickness of the UT-SOI in use or by the etching depth. We achieved this by setting the initial patch lateral width (e.g. from $$w$$ = 0.8 $$\upmu$$m up to $$w$$ = 2 $$\upmu$$m) providing wires having a base between 150 and 400 nm and height ranging from 50 to 100 nm. In order to obtain smaller wires, it is in principle possible to use thinner UT-SOI layers (e.g. by etching a few nm of the top silicon layer).

One of the most important features of nano-wires is their electrical properties. For instance, the changes in conduction of wire-based transistors can be efficiently exploited for sensing64 or for thermoelectricity7 with wires having rough interfaces. Nevertheless, most works on nanowires have focused on studying and optimizing their surface smoothness. Surface defects are very common and lead to electron-surface roughness scattering influencing the charge carrier density in the underlying silicon matrix64 modifying the electronic properties of a device (e.g. drop of the electron mobility)65. Thus, trans-conductance and electron mobility are important figures of merits that account for the quality of the interfaces and the limits of a wire-based device.

In our wires, the measured value of trans-conductance is $${G}_{{\rm{NW}}} \sim$$1–9 $$\upmu$$S. This is quite similar to state-of-the art FET transistors based on Si-nanowires grown via conventional bottom-up methods. In fact, for these devices, $${G}_{{\rm{NW}}}$$ is at most a few $$\upmu$$S66,67 even when considering wires having size close to those shown here6.

From the electric characterization, a rough estimation of electron mobility in our FET transistors provides $${\upmu }_{{\rm{e}}}$$ = 0.5–5$$\times$$10$${}^{3}$$ cm$${}^{2}$$V$${}^{-1}$$s$${}^{-1}$$. These values are in line with those found in Si-based bottom-up nanowires devices6,10,66. For top-down FET wires (usually fabricated via e-beam lithography and reactive ion etching) typical values of $${\upmu }_{{\rm{e}}}$$ lie in few hundreds of cm$${}^{2}$$V$${}^{-1}$$s$${}^{-1}$$56,68. Larger values of $${\upmu }_{{\rm{e}}}$$, up to $$\sim$$10$${}^{3}$$ cm$${}^{2}$$ V$${}^{-1}$$s$${}^{-1}$$, can be reached with top-down wires at the price of cumbersome fabrication methods (e.g. for smoothing the wires walls via oxidation), Ge alloying or strain engineering69,70. Thus, even without any kind of optimization of our devices, we can reach relatively high electron mobility. We interpret this feature as a possible consequence of the reduced surface roughness in our structures with respect to those obtained via vapor-liquid-solid growth and top-down methods.

In conclusion, we showed that dewetting, a spontaneous shape instability common to many different thin films of organic and inorganic substances, can be efficiently controlled in order to form extremely long and connected circuits of monocrystalline silicon wires on SiO$${}_{2}$$. We extended the control of this process to silicon patches having the record aspect ratio of 1/60000 (to be compared with the case of metals 1/10034, and semiconductors 1/40028) forming extremely elongated silicon mono-crystals.

We directly compare the experimental outcomes with 1/1 scale phase field simulations of surface diffusion that quantitatively reproduce their morphological evolution. We show a clear evidence of the key role played by faceting in stabilizing the dewetting outcome against breaking and thus for the reproducibility of the process and the stability of the final structures. Phosphorous-doped conductive Si wires are implemented showcasing the possibility to fabricate conducting nano-channels and transistors on an insulating substrate. Since the proposed approach is very general, it can be adapted to tune the Si wires aspect ratio by choosing suitable UT-SOI thickness and pattern periodicity combined with more complex, connected nano-architectures towards a full exploitation of their record length and atomically smooth facets.

Owing to a similar dewetting dynamic ruled by surface-diffusion-limited kinetics observed in SiGe alloys32 similar results can be extended to these materials rendering this method attractive for wires formation with different materials with the perspective of band-gap engineering and carrier mobility enhancement.

## Methods

### Sample preparation

A 12 nm-thick UT-SOI on a 25 nm thick buried oxide (BOX) was etched by electron-beam lithography and reactive etching with parallel trenches, from 0.75 mm to 70 $$\upmu$$m long, with variable pitch (0.5–4 $$\upmu$$m line-to-line distance, d$${}_{{\rm{LL}}}$$) and orientations with respect to the crystallographic axes. Thus, the samples were processed by plasma and wet chemical cleaning in N$${}_{2}$$ atmosphere for 20–30 s in a 5–10$$\%$$ HF. Finally, they were annealed in the ultrahigh vacuum ($$\sim$$10$${}^{-10}$$ Torr) of a molecular beam epitaxy reactor.

### Sample doping

Deposition of Spin on dopant (SOD, OD P508) was performed by spin-coating at 4000 rpm for 1 min and baking on a hot plate (10 min at 120 $${}^{\circ }$$C). Thermal diffusion of dopant was induced by rapid thermal annealing (30″ at 850 $${}^{\circ }$$C in N$${}_{2}$$ atmosphere). The SOD was removed by wet etching for 60″ in dilute HF (1:10). The metal pads (5 nm Ti/150 nm Au), after the definition of the contact design process by electron-beam lithography, are deposited by e-beam deposition.

### Electronic imaging

Scanning transmission electron micrograph have been acquired in z-contrast with a Cs probe corrected JEOL ARM 200F operated at 60 keV.