## Introduction

Tungsten diselenide (WSe2), as a two-dimensional (2D) semiconductor with one layer of W atoms sandwiched between two layers of Se atoms, has been regarded as one of the promising materials in future electronics, spin-electronics, and optoelectronics, owing to its excellent physical, optical, and electrical properties1,2. Whereas, the relatively low field-effect mobility is one of the main constraints preventing WSe2 from becoming a competing channel material for practical applications3,4,5. Till now, the room-temperature field-effect mobility of WSe2 grown by chemical vapor deposition (CVD) is normally around 30 cm2 V−1 s−1, lower than that required in high-performance electrical or photoelectrical devices3,4,5. Meanwhile, due to the ultra-low thermal conductance of WSe2 (0.05 W m−1 K−1)6, the requirement for efficient thermal dissipation is another significant factor in practical device application. In an electrical device, charge transport occurs at the interface between the semiconductor layer and the underlying substrate, where joule heating is generated. Thus, it is well known that the device mobility can be largely affected by charge impurities and roughness at the dielectric interface7,8,9,10,11,12,13,14,15. On the other side, the contact thermal interface is normally considered to be the bottleneck for efficient thermal dissipation rather than the material’s thermal conductivity itself16,17,18. Therefore, the dielectric interface is of great importance not only for improving the device mobility but also for removing heat from source. Till now, modifying the dielectric interface by self-assembled monolayers, bilayer polymeric dielectrics, plasma treatment, etc. has been developed to improve the device mobility19. To solve the interfacial thermal dissipation issue, some attempts such as covalent bonding or forming epitaxial interface have been made20,21, however practical applications of these approaches have had limited success due to the high cost, complicated modification process, lack of scalability, negative impact on the device mobility as well as poor compatibility with microelectronic processes. Till now, a simple, scalable, and compatible methodology to modify the dielectric interface for improving both the mobility and the thermal dissipation is still lacking, hampering recent efforts toward high-performance and stable electrical devices based on WSe2 or other 2D semiconductors.

Hexagonal-boron nitride (h-BN) has attracted much attention in recent years, as this material combines atomic-scale thickness with high dielectric constant (4), a wide bandgap, chemical inertness, excellent mechanical strength, and flexibility9,14,22. The in-plane thermal conductivity is up to ~200 to ~500 W m−1 K−1, several hundred times higher than that of amorphous SiO2 currently used in silicon-on-insulator device23. More importantly, 2D h-BN (2D-BN) has been normally regarded as a promising dielectric interface material for future electronics9,14. It has an atomically smooth surface without dangling bonds or charge traps, avoiding substrate surface roughness and carrier scattering from charge surface states or impurities. As a result, greatly improved carrier mobility of graphene (up to 100,000 cm2 V−1 s−1), black phosphorus, MoS2, organic crystals has been achieved on 2D-BN9,10,11,14,15, however its potential application in thermal dissipation at the semiconductor/dielectric interface is usually ignored. In the application, large-area 2D-BN needs to be placed on a desired surface. Current preparation methods require 2D-BN to be transferred from metals or solutions onto another surface for various applications12,14,24,25,26. The transfer process normally induces impurities, wrinkles, or breakage of the 2D-BN samples, which destroy the ideal van-der-Waals dielectric surface and cause interstices or incompact contact at the interface12,14,24,25,26, leading to the possibility of degraded performance or inefficient interfacial thermal dissipation for the WSe2 or other 2D semiconductor-based devices.

Although CVD on metal catalyst surface such as Cu, Ni, Pt, and Cu–Ni alloy can produce highly crystalline large-area 2D-BN27,28,29,30, it still requires the transfer process and a high growth temperature of 900–1000 °C. Recently, a few attempts on catalyst-free CVD have been made to grow 2D-BN directly on SiO2/Si31 or sapphire32. However, these processes require extremely high growth temperature above 1100 or 1400 °C, respectively. In an industrial-scale production, high temperature implies large energy consumption, high cost, and a decrease in compatibility with microelectronics fabrication processes. Plasma-enhanced CVD (PECVD) is a widely used industrial technology, which has high compatibility with current microelectronics fabrication process. To solve this problem, PECVD is particularly attractive, since the high energy plasma environment can decompose the precursor molecules at room temperature, thus enabling low-temperature growth of boron nitride (BN) materials directly on various surfaces33,34,35. Without metal catalysts, structural defects readily form at the edges and terminate the crystal growth. As a result, amorphous BN, disordered h-BN, or cubic-BN thick films are normally obtained by PECVD33,34,35, with a thickness about tens or hundreds of nanometers and a quality lower than that required for device applications. Till now, the catalyst-free growth of 2D-BN (mono-layered or few-layered) by PECVD is still absent.

Herein, we find that efficient crystal growth of 2D-BN takes place in a near-equilibrium state between the competition of etching and growth in PECVD. Based on this finding, we develop a near-equilibrium PECVD (ne-PECVD) to modify the dielectric interface, which realizes catalyst-free growth of uniform poly-crystalline 2D-BN with domains around 20–200 nm directly on SiO2/Si, quartz, sapphire, silicon, or even SiO2/Si with three-dimensional (3D) structures at a temperature as low as 300 °C, hundreds of degrees lower than that previously reported for 2D-BN growth. The thickness is precisely controlled from monolayer to four-layer by the growth time. After modification, the substrates have a smooth, atomically clean, and tightly contacted conformal van-der-Waals dielectric interface, which can be directly used to grow WSe2 by CVD (CVD-WSe2) for field-effect transistors (FETs). As a result, the device has an improved mobility around 56–121 cm2 V−1 s−1, higher than that on bare SiO2/Si (2–21 cm2 V−1 s−1) and the reported results of CVD-WSe2 FETs on SiO2/Si3,4,5, and exhibits high stability with increased saturated power density up to 4.23 × 103 W cm−2. Both experimental and simulation results show that the conformal 2D-BN produced by ne-PECVD can better bridge the vibrational spectrum at the semiconductor/dielectric interface against substrate roughness. After modification, the interfacial thermal resistance of CVD-WSe2 on SiO2/Si decreases by 4.55 × 10−8 m2 K W−1 to a value smaller than 4.2 × 10−8 m2 K W−1, indicating an improved thermal dissipation at the dielectric interface.

## Results

### Growth of 2D-BN by ne-PECVD

The PECVD setup is shown in Fig. 1a, which is composed of a 2-inch quartz tube mounted inside two tubular furnaces and a radiofrequency (13.56 MHz) plasma generator between them. Solid ammonia borane was placed in the center of the tubular furnace (T1) upstream, and then was evaporated and diffused into the zone downstream by an Ar/H2 (100 sccm/10 sccm) carrier gas when the temperature of T1 rose to 110 °C. In the experiment, to obtain a steady precursor supply, ammonia borane was placed in a small quartz tube with one end sealed. 2D-BN films (Fig. 1b) were grown on SiO2/Si at 500 °C in 30 W plasma (860 mTorr) for 30, 40, 50, and 60 min in the center of the tubular furnace (T2) downstream. Figure 1c, d and Supplementary Fig. 1 show the atomic force microscope (AFM), optical, and scanning electron microscope (SEM) images of the as-grown 2D-BN (30 min) on SiO2/Si, respectively. The sample has a homogeneous color contrast and an ultra-smooth surface with roughness (around 0.2 nm) similar or even lower than that of bare SiO2/Si (Supplementary Fig. 2). Raman spectra (Fig. 1e) are collected from different locations of the sample, all of which have a homogeneous peak at ~1369 cm−1, corresponding to the E2g phonon vibration of h-BN, indicating high uniformity of the as-grown film. The peak at ~1450 cm−1 is assigned to the third-order transverse optical phonon mode of Si of SiO2/Si substrate29. The E2g band is located at a similar position to that of CVD 2D-BN (Supplementary Fig. 3), while the full width at half maxima (FWHM, ~49 cm−1) of the peak is larger than that (~24 cm−1) of CVD 2D-BN, revealing the poly-crystalline nature of the as-grown film with smaller grain size. After transferring the film to a carbon-copper grid, transmission electron microscope (TEM) image (Fig. 1f) shows a clean, continuous, uniform membrane-like structure. Cross-section TEM images (Supplementary Fig. 4) reveal layered crystalline structures, indicating the 2D nature of the material. The diffraction spot rings in the selected area electron diffraction (SAED) patterns (Supplementary Fig. 5a, 5b) indicate the poly-crystalline nature of the 2D-BN. With smaller electron beam spot size, six-fold symmetric diffraction spots (Supplementary Fig. 5c, 5d) can be observed, showing that the sample is composed by small crystalline h-BN domains. Energy-dispersive spectroscopy (EDS) collected from the membrane (Supplementary Fig. 6) exhibits B, N element peaks without any other peaks except C, Cu, and O (from carbon-copper grid), indicating the high sample purity. X-ray photoelectron spectroscopy (XPS, Fig. 1g) reveals an almost equal composition of B and N elements (1:1.12). Symmetrical B 1s and N 1s peaks are located at 190.4 and 398.3 eV, respectively, indicating that the as-grown sample is predominantly composed of B–N bonds with sp2 hybridization31. To measure the thickness, the as-grown samples with continuous areas up to several square centimeters are transferred to another SiO2/Si substrate using poly-methyl-methacrylate (PMMA). The thicknesses (Fig. 1h–k, Supplementary Fig. 7) measured from the boundaries between the sample and SiO2/Si are 0.85 nm (30 min), 1.2 nm (40 min), 1.6 nm (50 min), and 2.1 nm (60 min), which correspond to 1, 2, 3, and 4 atomic layers of 2D-BN excluding the roughness of SiO2/Si30. The thickness shows a good correlation with the growth time (Supplementary Fig. 8), in consistence with the cross-section TEM results (Supplementary Fig. 4). Therefore, large-area uniform 2D-BN films are grown on SiO2/Si with controllable thickness from monolayer to multilayers (Supplementary Figs 4, 9).

The samples are transferred to highly oriented pyrolytic graphite (HOPG) for scanning tunneling microscopy (STM) studies. The grain size is measured in the range of 20 nm to more than 200 nm (Supplementary Fig. 10). Magnified low-temperature STM (LT-STM) image (Fig. 2a) reveals a honeycomb-like crystalline structure with a nearly atomically clean surface, while the fast Fourier transform (Fig. 2b, Supplementary Fig. 11) image confirms the hexagonal lattice structure. Moiré patterns (Supplementary Fig. 12), which are attributed to the lattice mismatching and rotation of the 2D-BN on HOPG, are observed, indicating high crystallinity of the 2D-BN domains. The scanning tunneling spectroscopy (STS, Fig. 2c) curve collected from HOPG is a typical dI/dV of graphite with no bandgap, while the density of states of 2D-BN is remarkably depressed near the Fermi level with a measured band gap around 5.0 eV. Compared with intrinsic 2D-BN (5.9 eV), the reduced bandgap is attributed to the weak interaction and the screening from the HOPG substrate36,37. The bandgap can also be measured by ultraviolet-visible (UV-vis) absorption spectroscopy. UV-vis spectrum (Fig. 2e) of the 2D-BN grown on quartz (Fig. 2d) exhibits zero absorbance in the visible-light region and a sharp peak at ~200 nm, consistent with the results reported previously27. The optical energy gap is calculated by Tauc’s equation: αhν = A( − Eg)1/2, where α is the optical absorption coefficient, is the energy of incident photon, A is the proportionality constant, and Eg is energy gap27. The (αhν)2 vs. curve acquired from the sample is shown in Fig. 2e, and the calculated optical energy gap is 5.81 eV, which is larger than that of bulk h-BN and close to intrinsic 2D-BN27.

To confirm the conformal growth of 2D-BN, SiO2/Si with 3D structures (Fig. 2f) were used as the growth substrate. After ne-PECVD, XPS spectra (Supplementary Fig. 13) indicate the growth of 2D-BN, while SEM images (Fig. 2g, h, Supplementary Fig. 14) show a clean 3D surface without any bubbles, wrinkles, or incompact contacts, which normally exist in the post-growth transfer CVD samples (Supplementary Fig. 15). The 3D structures were cut and transferred to a copper grad. Cross-section TEM images (Fig. 2i, j) show a closely contacted layer of 2D-BN on the 3D surface, indicating the conformal growth and the potential of ne-PECVD in modifying 3D dielectric interface for devices with 3D configuration. Besides SiO2/Si, substrates like sapphire, silicon, quartz (Supplementary Fig. 16) can also be used in ne-PECVD, and the growth temperature on SiO2/Si can decrease to as low as 300 °C (Supplementary Fig. 17), hundreds of degrees lower than that reported previously27,28,29,30,31,32.

### Near-equilibrium growth mechanism

In the growth, ammonia borane is evaporated (H2, monomeric aminoborane, borazine also exist owing to thermal decomposition)38, and then decomposed into boron and nitrogen species (radicals, ions, and atoms) by the plasma. These highly reactive species overcome the large threshold barrier required, leading to catalyst-free growth of BN materials directly on the inert surface at low temperature. However, these species are inclined to form structural defects on edges, which prevent the crystal growth of 2D-BN. Some literatures have demonstrated the etching of BN materials by H2, Ar, O2, or H2/Ar plasma39,40,41, thus a competition process of etching and nucleation/deposition exists in the PECVD process42, however the 2D-BN lattice is energetically highly stable. Experiments show no obvious etching of 2D-BN in H2/Ar plasma even after 60 min treatment (Supplementary Fig. 18). Thus, in normal cases, the nucleation/deposition dominates, and disordered or amorphous BN films are grown in a non-equilibrium state as shown in Supplementary Fig. 19, 2033,34,35. Nevertheless, the literature and first-principle calculation (Supplementary Note 1) show that the edge defect has a higher energy43, compared with pristine h-BN lattice and H-passivated edges. The energy increases by 7.458 and 9.526 eV, when a B3N2 or B2N3 pentagonal defect forms on H-passivated armchair edges (Supplementary Fig. 21). Thus, the etching tends to occur at the edge defects. Owing to the low etching rate, a slow and steady precursor feeding is required to establish a reversible competition between the nucleation/growth and the etching. Therefore, controlled experiments (Supplementary Fig. 22, 23) show that a slow and steady precursor feeding is pivotal for the 2D-BN growth, which requires placing the precursor in a small quartz tube with one end sealed and maintains at a temperature (T1) below 115 °C. In such a near-equilibrium state (Supplementary Note 2), moderate etching by the H2/Ar plasma removes defects generated on the edges and keeps the edges atomically smooth (Fig. 3b) and active during the whole PECVD process, resulting in efficient crystal growth of 2D-BN directly on the inert surface without any catalyst (Fig. 3c). The 2D-BN crystals nucleate and the grain sizes gradually increase up to more than 200 nm (Fig. 3d–f), and finally a continuous 2D-BN film is obtained on the substrate.

### CVD growth of WSe2 on 2D-BN

The benefit of ne-PECVD is that it modifies flat or 3D substrates with an atomically clean conformal van-der-Waals dielectric surface, which can be directly used in electrical devices. We grew 2D WSe2 crystals (CVD-WSe2) on 2D-BN/SiO2/Si by CVD for back-gated FETs. In the growth, a quartz boat with 450 mg Se powder was placed upstream in the furnace, while 130 mg WO3 powder was placed downstream (Supplementary Fig. 24). The substrates were placed on the top of WO3 with the surface facing down. The upstream and downstream zones were gradually heated from room temperature to 300 and 920 °C in 300 sccm pure Ar within 30 min. And then, a mixture of 85 sccm Ar and 15 sccm H2 was introduced into the furnace. After 15 min growth, the furnace was naturally cooled down to 300 °C, and was fast cooled down to room temperature. AFM and optical images (Fig. 4a, Supplementary Fig. 25) show that most of the as-grown CVD-WSe2 crystals have a triangular or hexagonal shape with a size of about 30–200 μm and a height of about 1.2 nm. The high-resolution TEM image and the hexagonal arrangement of the SAED pattern (Fig. 4b, c) show the CVD-WSe2 sample is well crystallized with the measured lattice spacing of 0.28 nm, in consistent with the (100) plane spacing of 2H-WSe2. In Raman spectrum (Fig. 4d), an intrinsic E12g band at 248 cm−1 and the absence of the B12g mode at 307 cm−1 indicate the monolayer nature of the CVD-WSe27,25,44. The photoluminescence (PL) spectrum (Fig. 4e) exhibits strong emission at 768 nm, corresponding to the direct bandgap of monolayer WSe2 7,8,24,25. The highly crystalline structure (Fig. 4b), as well as the narrow E12g Raman peak (a FWHM of 5.7 cm−1) and the sharp PL emission (a FWHM of 49 meV) without the defect emission at 1.54 eV7,8,25,44, indicate high quality of the CVD-WSe2 samples grown on the ne-PECVD 2D-BN.

### Enhanced mobility of WSe2 on 2D-BN

After CVD growth, the back-gated FETs were directly fabricated by using 2D-BN/SiO2/Si as gate dielectric and back gate, using CVD-WSe2 as the conducting channel (Fig. 5). All devices were current-annealed or thermal-annealed, and then were measured under ambient conditions. As a comparison, CVD-WSe2 FETs were also fabricated using bare SiO2/Si. Drain-source current (Ids) vs. drain-source voltage (Vds) (output curve, Fig. 5b) and Ids vs. gate voltage (Vg) (transfer curve, Vds at −2 V, Fig. 5c) show a typical p-type characteristic with an on/off ratio up to 1 × 108 and 1 × 107 for CVD-WSe2 FETs on 2D-BN/SiO2/Si and on bare SiO2/Si substrates, respectively, when the gate voltage sweeps from −80 to 80 V. The mobility is calculated (Supplementary Note 3, Supplementary Fig. 26) by the equation3,4,5:

$$\mu = (\frac{L}{{WC_{\mathrm{i}}V_{\mathrm{ds}}}})(\frac{{\Delta I_{\mathrm{ds}}}}{{\Delta V_{\mathrm{g}}}})$$

where Ci is the dielectric capacitance, W is the channel width, L is the channel length, and (ΔIdsVg) is the slope of the transfer curves in the linear regime. The calculated mobility of CVD-WSe2 on 2D-BN/SiO2/Si is around 56–121 cm2 V−1 s−1, which is higher than that of CVD-WSe2 grown on bare SiO2/Si (Fig. 5e, 2–21 cm2 V−1 s−1) and the room-temperature mobility (10–30 cm2 V−1 s−1) of monolayer WSe2 on bare SiO2/Si or Al2O3 reported previously3,4,5. The increased mobility is in good agreement with that of 2D semiconductor devices on peel-off or CVD 2D-BN reported previously9,12,13,14,15, indicating the high quality of the 2D-BN produced by ne-PECVD.

There are several reasons for the increased mobility of CVD-WSe2 on ne-PECVD 2D-BN. The main reason is the smooth van-der-Waals conformal surface of the 2D-BN, as shown in STM image (Fig. 2a). Atomically thin 2D materials have a large surface-to-volume ratio, thus the carrier conduction is significantly influenced by the dielectric interface. At the interface, the modification with 2D-BN avoids surface roughness, dangling bonds, surface charge impurities or traps, which normally exist on bare SiO2/Si7,8,9,10,11,12,13,14,15, and decreases charge carrier scattering. As a result, the 2D-BN remarkably improves the carrier mobility of 2D or organic materials7,8,9,10,11,12,13,14,15,25. For instance, Kim et al. reported that MoS2 mobility increased from 10 to 42 cm2 V−1 s−1 by introducing highly crystalline CVD h-BN between MoS2 and SiO2/Si25. In the case of CVD-WSe2 on ne-PECVD 2D-BN (Fig. 4e), the narrow symmetrical PL peak originated from the neutral exciton emission is observed7,24,25, while the PL of CVD-WSe2 on SiO2/Si is weaker with a red shift (17 meV) and unsymmetrical profile, corresponding to a charged exciton (trion) emission7,24,25. The PL spectra indicate that the ne-PECVD 2D-BN is more charge-neutral, which strongly suppresses and screens out the influence of charge impurities existing on bare SiO2/Si7,24,25. Moreover, the inert 2D-BN surface has low charge trap density. Joo et al. observed the reduction of interfacial traps density by 100 times compared with that on SiO2/Si11. To clarify trap states on 2D-BN, we investigated the hysteresis in the transfer characteristics of CVD-WSe2 FETs (Fig. 5g, h, Supplementary Fig. 27). On bare SiO2/Si or disordered PECVD BN film, an obvious hysteresis exists, while it becomes much smaller on ne-PECVD 2D-BN. This result reveals a charge trap-free dielectric interface of the ne-PECVD 2D-BN10,11,14,15, thus it avoids accumulation of charge impurities at the interface of SiO2/Si, which are normally regarded as carrier scattering centers to decrease the mobility10,11,14,15.

The other reason is the clean dielectric interface. Moderate etching effect of Ar/H2 plasma in ne-PECVD removes the surface impurities generated on 2D-BN, resulting in an atomically clean surface (Fig. 2a). After ne-PECVD, CVD-WSe2 crystals are directly grown on 2D-BN/SiO2/Si, avoiding post-growth transfer. The post-growth transfer normally involves a deposition of polymers and a solution-washing process, thus this process introduces contamination or defects at the interface and causes low quality of interlayer contact8,26,45, leading to reduction of the device performance7,8,45. Control experiments show that the post-growth transferred CVD-WSe2 (PT-WSe2) on 2D-BN/SiO2/Si has an obvious hysteresis in the transfer curve (Supplementary Fig. 27). The mobility (Fig. 5e, f) decreases to 26.3–70.2 cm2 V−1s−1, lower than that (56–121 cm2 V−1s−1) of the directly grown samples. Therefore, the moderate plasma etching as well as the direct CVD growth, in principle, realizes a clean and smooth interlayer interface between 2D-BN and WSe2, compared with the transferred structures, which is one of the key factors to obtain the intrinsic properties of WSe2 or other 2D materials7,26,46,47.

Moreover, the improved sample quality, when using 2D-BN as the growth substrate2,24,48, should be one of other probable reasons for the increased mobility of CVD-WSe2 on ne-PECVD 2D-BN. Uchida et al. and Okada et al. show that higher quality of transition metal dichalcogenides (TMDs) such as WS2 can be produced on flat 2D-BN without dangling bonds and contaminations compared with the sample grown on SiO2 or post-growth transferred 2D-BN2,24. Similarly, in this work, the FWHM of the Raman E12g peak (Fig. 4d) and the FWHM of the PL peak (Fig. 4e) decreases from 12.3 cm−1 and 54 meV (grown on SiO2/Si) to 5.7 cm−1 and 49 meV (grown on 2D-BN), respectively, indicating that higher crystallinity of the CVD-WSe2 is obtained when the growth takes place on ne-PECVD 2D-BN2,24,44. In order to avoid the difference in sample quality, we grew CVD-WSe2 on SiO2/Si and then transferred to other substrates (Fig. 5d–f). Although the mobility of PT-WSe2 on 2D-BN/SiO2/Si (26.3–70.2 cm2 V−1 s−1) is lower than that of CVD-WSe2 on 2D-BN/SiO2/Si due to the impurities or defects introduced by the post-growth transfer process7,26,46,47, it is still higher than that of PT-WSe2 on bare SiO2/Si (3.8–18.6 cm2 V−1 s−1), indicating that the improved WSe2 mobility on 2D-BN/SiO2/Si mainly originates from the 2D-BN layer rather than the sample quality.

### Improved thermal dissipation of WSe2 FETs on 2D-BN

The thermal dissipation is a great challenge for devices or integrated circuits with ultrahigh operating frequency, especially for WSe2 FETs, as the WSe2 is normally regarded as a material with the lowest thermal conductivity6. Although much research has demonstrated the 2D-BN as an ideal dielectric material for improving the device mobility, its potential application in improving the thermal dissipation of a FET device is usually ignored. We measured the saturated power density of CVD-WSe2 FETs on different substrates when current breakdown took place (Fig. 5i, j, Supplementary Fig. 28). The saturated power density (Fig. 5e, f), calculated by the power at the current breakdown divided by the device area, reaches up to 4.23 × 103 (CVD-WSe2) and 1.87 × 103 W cm−2 (PT-WSe2) on 2D-BN/SiO2/Si, higher than that on bare SiO2/Si, indicating that the ne-PECVD 2D-BN not only increases the device mobility but also increases device stability with higher saturated power density.

The increased saturated power density is attributed to the improved interfacial thermal dissipation at the dielectric interface with 2D-BN. Different from thermal conductivity, interfacial thermal conductivity is a measure of an interface’s conductivity to thermal flow, which exists even at atomically perfect interfaces. Despite the large in-plane thermal conductivity of 2D-BN, it is atomically thin, the in-plane thermal flow can be ignored, and the interfacial thermal resistance across the dielectric interface dominates the thermal conduction18,49, which plays a critical role in the saturated power density of the devices. A scanning thermal microscope (SThM), which operates by scanning a sample solid surface with a sharp temperature-sensing tip, is a powerful tool for imaging sub-micron heat transfer at surface and subsurface levels50. When the tip scans on the sample surface by an active and contact mode; 2D-mapping thermal images of CVD-WSe2/2D-BN/SiO2 and CVD-WSe2/SiO2 (Fig. 6a, b) are obtained by monitoring the temperature changes (∆T) of the tip. As a comparison, other TMDs materials (CVD-MoSe2, Fig. 6c, d) are also measured. No obvious ∆T change is observed on 2D-BN/SiO2, owing to efficient thermal dissipation between the tip and the substrate across the 2D-BN. Although the sample (CVD-MoSe2 or CVD-WSe2)/2D-BN/SiO2 has more interfaces compared with the sample/SiO2, the former has lower ∆T change (Fig. 6e, f), indicating that the 2D-BN layer helps thermal dissipation from tip to substrate across the sample/dielectric interface (Supplementary Note 4).

To quantify the thermal dissipation, interfacial thermal resistance measurements were carried out by differential 3ω method (Fig. 7a, b, Supplementary Fig. 29, Supplementary Note 5)18,49. Although the channel/2D-BN/SiO2 contains two interfaces, i.e. the channel/2D-BN interface and the 2D-BN/SiO2 interface, while the channel/SiO2 contains only one interface, all results, including CVD-WSe2/2D-BN/SiO2, PT-WSe2/2D-BN/SiO2, and CVD-MoSe2/2D-BN/SiO2 (Supplementary Fig. 30), exhibit an improved thermal dissipation in the case of the channel/2D-BN/SiO2. Compared with that of CVD-WSe2/SiO2 and CVD-MoSe2/SiO2, the interfacial thermal resistance of CVD-WSe2/2D-BN/SiO2 (Fig. 7a) and CVD-MoSe2/2D-BN/SiO2 (Supplementary Fig. 31) reduces by (4.55 ± 0.25) × 10−8 and (1.21 ± 0.20) × 10−7 m2 K W−1, respectively (Fig. 7c). In the case of the WSe2, to avoid the difference in sample quality on different growth substrates48, we measured PT-WSe2/2D-BN/SiO2 and PT-WSe2/SiO2 by differential 3ω method. The measurement shows reduced interfacial thermal resistance of PT-WSe2/2D-BN/SiO2 by (1.2 ± 0.20) × 10−8 m2 K W−1 compared with PT-WSe2/SiO2 (Supplementary Fig. 32). The calculated thermal resistance (4.2 × 10−8 or 1.1 × 10−7 m2 K W−1) by differential 3ω method corresponds to the sum of the substrate thermal resistance and the interfacial thermal resistance of CVD-WSe2/2D-BN/SiO2 or CVD-MoSe2/2D-BN/SiO2, respectively. Thus, the interfacial thermal resistance of CVD-WSe2/2D-BN/SiO2 and CVD-MoSe2/2D-BN/SiO2 is lower than 4.2 × 10−8 and 1.1 × 10−7 m2 K W−1 (Supplementary Note 5), showing better thermal dissipation compared with the results of graphene/SiO2 (1.24–5.56 × 10−8 m2 K W−1)49, MoSe2/Au/SiO2 (100–1000 × 10−8 m2 K W−1)51, etc.

Moreover, one benefit of ne-PECVD is that the conformal 2D-BN avoids impurities, interstices, or incompact contacts, which normally exist in post-growth transferred 2D-BN produced by CVD. The direct CVD growth of WSe2 on 2D-BN provides strong interlayer coupling46. As a result of the clean and tightly contacted interface, the differential 3ω measurement (Fig. 7d) shows that the interfacial thermal resistance of PT-WSe2/2D-BN (prepared by ne-PECVD)/SiO2 decreased by 1 × 10−7 m2 K W−1, compared with PT-WSe2/2D-BN (post-growth transferred CVD 2D-BN)/SiO2, indicating the significance of ne-PECVD 2D-BN with conformal van-der-Walls interface in device thermal management.

### Molecular dynamics simulation of interfacial thermal dissipation

The discrepancy in thermal dissipation should be related to the roughness of the interface that an additional layer of 2D-BN could help the WSe2 (or MoSe2) to conform onto the SiO2 surface, resulting in a reduced roughness and interface thermal resistance18,49. To clarify the mechanism, we compare the interfacial thermal resistance for WSe2/SiO2 (R1) and WSe2/2D-BN/SiO2 (R2) under different substrate surface roughness conditions by molecular dynamics (MD) simulations (Supplementary Note 6, Supplementary Fig. 33). Because of the broadened vibrational frequency distribution52, the 2D-BN layer works as an external material that can better fit the vibrational spectrum between SiO2 substrate and WSe2 layer. Therefore, the insertion of 2D-BN layer can reduce the interfacial thermal resistance, regardless of the substrate roughness. In the MD simulations, the size of the amorphous SiO2 substrate is 12.4 nm × 12.4 nm × 4 nm, and the monolayer 2D-BN and WSe2 conformally cover the substrate. In order to simulate the practical surface roughness of SiO2 substrate, we randomly removed surface atoms to form holes with a diameter of Ra, as shown in Fig. 7e. For the smooth substrate, R1 is reduced by almost 50% after inserting a 2D-BN layer. More interestingly, R1 increases rapidly with the substrate roughness as a result of the enhanced rough surface scattering, while the interfacial heat conduction is protected by the 2D-BN layer against the substrate roughness, leading to the almost constant value of R2. As a result, the improvement in the interfacial heat conduction via the insertion of 2D-BN layer is even more pronounced at larger surface roughness (Fig. 7f, Supplementary Fig. 34). With 2 nm substrate roughness, R1 is reduced by 60%, which agrees well with our experimental results.

## Discussion

In this article, we directly modify the dielectric interface with poly-crystalline mono-/few-layer 2D-BN with domain size around 20–200 nm at a temperature as low as 300 °C. To the best of our knowledge, it is the lowest reported temperature for growing 2D-BN. The conformal growth on 3D surface is important for microelectronics manufacturing, however it is still difficult to be realized by existing 2D-BN preparation methods. Using ne-PECVD, large-area 2D-BN with desired thickness is directly grown on not only flat but also 3D inert surface without using metal catalyst. This method avoids the post-growth transfer process required in normal CVD process, forming a clean conformal van-der-Waals dielectric interface.

After modification, the as-grown 2D-BN was directly used to grow CVD-WSe2 for FET devices. The clean flat dielectric interface has low density of dangling bonds, charge impurities and charge traps, which lead to improved mobility compared with that of CVD-WSe2 grown on bare SiO2/Si. MD simulation shows that the 2D-BN can better bridge the vibrational spectrum across the dielectric interface, and protect the interfacial heat conduction against substrate roughness. Thus, the clean and conformal 2D-BN produced by ne-PECVD not only improves the device mobility but also reduces interfacial thermal resistance. After ne-PECVD modification, the interfacial thermal resistance of CVD-WSe2/SiO2 and CVD-MoSe2/SiO2 decreases by 4.55 × 10−8 and 1.21 × 10−7 m2 K W−1 to a value lower than 4.2 × 10−8 and 1.1 × 10−7 m2 K W−1, respectively. As a result, the saturated power intensity of the CVD-WSe2 FET increases by several folds up to 4.23 × 103 W cm−2. More importantly, the dielectric interface with ne-PECVD 2D-BN exhibits lower interfacial thermal resistance than that with post-growth transferred CVD 2D-BN, indicating the great importance of the clean conformal interface in efficient thermal dissipation. Therefore, the ne-PECVD modification results in electrical devices with both high performance and power stability, compared with that on a bare SiO2 or CVD 2D-BN dielectric surface. These, as well as the advantages of low modification temperature, atomically smooth and clean surface, no requirement of post-growth transfer, conformal growth on 3D surface, capability for scaling up and industrial compatibility with microelectronic process, make this approach an ideal dielectric interface modification methodology for future micro/nanoelectronics.

## Methods

### Growth of 2D-BN

Continuous 2D-BN films were produced on SiO2/Si in a PECVD system. Ammonia borane (BH3-NH3, Sigma-Aldrich), which was used as the precursor, was placed in an isolated semi-enclosed quartz tube in T1 zone. Semi-enclosed quartz tube was used to reduce the precursor feeding rate and to obtain a steady precursor supply. A clean SiO2/Si was placed in T2 zone and heated to 500 °C in a constant Ar/H2 flow of 100 sccm/10 sccm (860 mTorr). After the T2 reached 500 °C, 20 mg ammonia borane was heated up to 110 °C. Meanwhile, the plasma generator (30 W) was opened, and the plasma flame filled the whole quartz tube, resulting in high efficient growth of 2D-BN. After growth for 30–60 min, the furnace was fast cooled to room temperature.

### Characterization

The 2D-BN and WSe2 samples were measured by AFM (Multimode 8, Bruker, tapping mode), high-resolution TEM (Tecnai G2 F20 S-Twin, acceleration voltage: 200 kV), EDS (equipped on TEM), optical microscopy (DM2500P, Leica), XPS (Perkin-Elmer PHI 5300 with 250 W Mg Kα source, 1253.6 eV), Raman spectra (HORIBA XploRA, 532 nm laser), UV-vis absorption spectrophotometer (Perkin-Elmer, Lambda35), and field-emission SEM (ZEISS, Ultra 55). The thermal images were measured by using a SThM probe (VITA-DM) mounted in the tip cantilever of Bruker Dimension Edge AFM (Supplementary Note 7, Supplementary Fig. 35). For TEM, AFM, or STM measurements, PMMA was spin-coated on the 2D-BN/SiO2/Si, and then the PMMA/2D-BN film was lift off from SiO2/Si by etching in 20% hydrofluoric acid. The PMMA/2D-BN film was rinsed in deionized water and transferred to the TEM grids, SiO2/Si, or HOPG, respectively. Finally, the PMMA was removed by either immersion in acetone or heating at 400 °C in Ar atmosphere. STM measurements were carried out in a custom-built multi-chamber ultrahigh vacuum system housing an Omicron LT-STM in the analysis chamber with a base pressure better than 1.0 × 10−10 mbar. All STM images were recorded in constant current mode at liquid nitrogen temperature (77 K) using electrochemically etched tungsten (W) tips. The STS data were acquired using a lock-in amplifier by applying a small sinusoidal modulation to the tip bias voltage (typically 3 V at 600 Hz). All STM images were processed using WSxM.

### Device fabrication and measurement

CVD-WSe2 was directly grown on 2D-BN/SiO2/Si by CVD. PT-WSe2 was prepared by post-growth transfer of CVD-WSe2 to 2D-BN/SiO2/Si using PMMA. After that, the source-drain electrodes (5/50 nm Cr/Au or 50 nm Au) were patterned on the sample by electron beam lithography and thermal deposition (Kurt J. Lesker). To obtain a better contact between the sample and the electrodes, thermal-annealing or current-annealing was performed. The electrical measurement was carried out in air at room temperature by a probe station (EVERBING, PE-4) and a semiconductor analyzer (Keysight B1500A). Details of the differential 3ω measurement were discussed in Supplementary Note 5.