http://newsroom.intel.com/docs/DOC-2035 (May 2011)

Feature sizes have been getting smaller in the semiconductor industry for decades, but devices have remained resolutely flat. Now Intel has announced that it will start manufacturing three-dimensional transistors later this year. The new Tri-Gate transistors will have gate lengths of 22 nm, compared with the 32-nm gates found in the company's existing devices.

In a conventional transistor the electric current between the source and drain electrodes is controlled by a voltage applied to a third electrode, the gate, which is separated from the channel carrying the current by a flat insulating or dielectric layer. In the Tri-Gate transistors, the dielectric layer and gate electrode cover the sides and top of an extremely thin silicon fin. Moreover, it is possible to have two or more fins connected together.

The increased control over the channel current provided by the 3D design means that these transistors have lower operating voltages and leakage currents than existing devices, which will reduce power consumption. The performance of the new devices is also 37% better than that of existing ones at low voltages. And if the semiconductor industry continues to follow Moore's law, gate lengths will continue to drop, to 14 nm in 2013 and 10 nm in 2015.