Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties

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Abstract

We describe a versatile approach for preparing flash memory devices composed of polyelectrolyte/gold nanoparticle multilayer films. Anionic gold nanoparticles were used as the charge storage elements, and poly(allylamine)/poly(styrenesulfonate) multilayers deposited onto hafnium oxide (HfO2)-coated silicon substrates formed the insulating layers. The top contact was formed by depositing HfO2 and platinum. In this study, we investigated the effect of increasing the number of polyelectrolyte and gold nanoparticle layers on memory performance, including the size of the memory window (the critical voltage difference between the ‘programmed’ and ‘erased’ states of the devices) and programming speed. We observed a maximum memory window of about 1.8 V, with a stored electron density of 4.2 × 1012 cm−2 in the gold nanoparticle layers, when the devices consist of three polyelectrolyte/gold nanoparticle layers. The reported approach offers new opportunities to prepare nanostructured polyelectrolyte/gold nanoparticle-based memory devices with tailored performance.

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Figure 1: Thickness and charge density measurements of (PE/AuNP)n multilayers for n = 1–4.
Figure 2: Structure of a typical memory device prepared with the LbL technique.
Figure 3: Capacitance versus voltage (CV) curves for (PE/AuNP)n multilayers for n = 1–4.
Figure 4: Real-space imaging of programmed and erased states.

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Acknowledgements

This work was supported by the ERC Program of the MOST/KOSEF (R11-2005-048-00000-0) and the Australian Research Council under the Federation and Discovery Project Schemes. We acknowledge assistance from S. Oh in obtaining the SEM images and Y. J. Choi for the SNDM images.

Author information

J.S.L. and J.C. conceived and designed the experiments, C.L., I.K., J.P. and Y.M.K. performed the experiments, J.S.L and J.C analysed the data, H.S. and J.L. contributed to materials/analysis tools, and F.C. assisted with data interpretation and provided fruitful discussions. J.S.L, J.C. and F.C. co-wrote the paper.

Correspondence to Jang-Sik Lee or Jinhan Cho.

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Lee, J., Cho, J., Lee, C. et al. Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties. Nature Nanotech 2, 790–795 (2007) doi:10.1038/nnano.2007.380

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