High-resolution non-destructive three-dimensional imaging of integrated circuits

Abstract

Modern nanoelectronics1,2 has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography3,4—a high-resolution coherent diffractive imaging technique—can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques5,6,7. Foreseeable developments in X-ray sources8, optics9 and detectors10, as well as adoption of an instrument geometry11 optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.

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Figure 1: Measurement principles of PXCT.
Figure 2: PXCT of detector ASIC chip.
Figure 3: Imaging a set-reset latch, a functional unit within the detector ASIC chip.
Figure 4: PXCT imaging of Intel processor.

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Acknowledgements

We thank S. Stutz and S. Finizio for helping with the preparation of the Intel sample, and B. Schmitt, X. Shi and A. F. J. Levi for discussions. The measurements were performed at the cSAXS beamline of the Swiss Light Source (SLS) at the Paul Scherrer Institut (PSI). We thank ScopeM, the scientific centre for optical and electron microscopy, for providing access to the xenon FIB/SEM (Tescan, Fera3). This work was supported by the Swiss National Science Foundation (grant no. 200021_152554) and R'EQUIP (project number 145056).

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Contributions

The sample preparation was done by E.H.R.T., R.D., E.M. and J.R. The experiment was carried out by M.H., M.G.-S. and E.H.R.T. The data were analysed and visualized by M.H., M.G.-S., E.H.R.T., J.R., R.D. and G.A. The FIB/SEM data were collected by E.M. The manuscript was written by M.H., M.G.-S., O.B. and G.A.

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Correspondence to Mirko Holler.

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The authors declare no competing financial interests.

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Reviewer Information Nature thanks J. Bruley and J. Hastings for their contribution to the peer review of this work.

Extended data figures and tables

Extended Data Figure 1 Sample preparation of the detector ASIC and the Intel processor.

ad, Detector ASIC; e, f, Intel processor. a, An area was chosen based on the manufacturing layout. The blue circle is 10 μm in diameter and marks the position from which the sample was prepared. b, A circular pillar was cut from the sample (see also Fig. 1a). The micromanipulator of the FIB/SEM was attached using carbon deposition. c, The sample was lifted from the chip and d, mounted on the sample holder for the tomographic measurement. e, Image of the 10 μm diameter pillar prepared from the 22 nm technology Intel processor sample. In the surrounding flat area to the left of the prepared pillar, no functional structure was visible on the surface prior to the milling process; therefore, in contrast to the sample from the detector ASIC, the sample from the Intel processor was extracted from a position without prior knowledge from either a design or useable image file. V1 is the diameter of the sample as measured in the SEM. Images in be were recorded using the SEM of the FIB/SEM machine. f, After sample extraction, the interconnect layer was removed by chemical etching and mechanical polishing from the remaining chip area. This visible light micrograph of the Si shows that the sample was extracted from a very regular, repetitive area of the processor. The hole from which the 10-μm pillar was removed can be seen in the centre of this image.

Extended Data Figure 2 Detector ASIC projections and histograms.

a, b, Representative projections of the detector ASIC PXCT measurements with a 16 μm × 12 μm field of view; a, amplitude, b, phase. c, Axial slice extracted from the 3D PXCT dataset of the interconnect layer of the detector ASIC from which the bivariate histogram (d) of the complex-valued refractive index, n = (1 − δ) + , was created (frequency (in units of counts) colour-coded in logarithmic scale). Al and SiO2 can be clearly identified. e, Histogram over 1 μm sample height along the cylinder, including the material of the diffusion barrier and of the vias. The observed variances within different material phases (element/compound names arrowed) arise from the signal to noise ratio of the reconstruction and are comparable to the variance of values observed for the volume outside the pillar (air).

Extended Data Figure 3 Detector ASIC slices.

a, Side view coronal cut of the detector chip PXCT tomogram in e Å−3. b, Axial cut of the PXCT tomogram, showing the diffusion layer of the detector ASIC. An overlay from the design file is shown in yellow on top of the measurement (e Å−3).

Extended Data Figure 4 Fourier shell correlation (FSC).

a, b, FSC of the detector ASIC PXCT tomogram (a) and of the Intel processor tomogram (b). The detector ASIC was reconstructed to a voxel size of 21.5 nm and the FSC curve (red) intersects the half-bit threshold (black arrow) at 0.61 spatial frequency/Nyquist, corresponding to 35-nm tomographic resolution. In the case of the Intel tomogram, the voxel size was 14.3 nm and the FSC curve intersects the threshold at 0.98 spatial frequency/Nyquist, corresponding to 14.6-nm tomographic resolution. See also refs 17, 22.

Extended Data Figure 5 Intel processor projection and histogram.

a, 2D axial slice of the PXCT tomogram of the Intel processor chip (electron density). b, A coronal slice of the same tomogram, with the blue line indicating the height at which the slice in a was extracted. c, Electron density plot for an xy subregion of the lowest layer in the chip (blue rectangle in a). Sharply peaked structures are attributed to gates; they are under-resolved and allow a conservative estimate of 15.8 nm (full-width at half-maximum) for the resolution. d, Bivariate histogram of the Intel processor chip with values of bulk SiO2 and Cu shown (frequency (in counts) colour-coded in logarithmic scale).

Extended Data Figure 6 Intel processor projections and gate pitch.

a, 2D axial slice of PXCT tomogram of the Intel processor chip. b, Line profile taken through the source/drain contacts within the rectangular box in c showing the electron density (e Å−3) The red bars mark 13 cycles and have a separation of 1,166 nm. The average pitch determined is therefore 1,166 nm/13 = 89.7 nm, which matches the gate pitch of Intel 22 nm Haswell technology. c, A coronal slice perpendicular to the slice in a through the purple line in a. Scale bar, 500 nm. Similarly, a sagittal slice perpendicular to the slice in a through the cyan line is shown in Extended Data Figure 7.

Extended Data Figure 7 Intel processor projections and fin pitch.

a, Sagittal slice perpendicular to the slice shown in Extended Data Fig. 6a, and through the cyan line in that panel, integrated over 20 pixels. A faint fingered structure appears at the bottom. Scale bar, 500 nm. b, Magnified view of a region of a; scale bar, 200 nm. c, A line profile taken between the two red arrows in b, showing a repetitive structure (black bars) with a pitch of about 60 nm, matching the pitch of the fins in Intel 22 nm Haswell technology. The height of these fins is indicated by the two yellow arrows in b and is approximately 3 pixels, corresponding to 43 nm. The documented height of the fins in the literature is 34 nm (see Methods).

Extended Data Figure 8 FIB/SEM tomography.

a, b, Slices of the detector ASIC, and c, d, slices of the Intel processor sample, all measured by FIB/SEM tomography after PXCT. b and d show a close-up of the region marked by the red rectangle in a and c, respectively. Curtaining effects during the milling process can degrade the resolution and introduce significant distortions. Especially in a and b, this effect becomes clear when the material composition changes drastically resulting in a locally altered milling speed; see red arrows below W vias in b. Since FIB/SEM is destructive, imaging cannot be repeated in such cases. In the case of the detector ASIC, a back-scattering detector was used (ESB, grid 1.5 kV) to reduce the effect of charging. The SEM was operated at a voltage of 2 kV. The individual slices were 12 nm in thickness cut by a focused ion beam (FIB) of Ga ions at 30 keV and 40 pA. In the case of the Intel processor sample, a 5 keV acceleration voltage was used in the SEM. This explains the non-ideal signal to noise ratio in c and d, and causes a loss of lateral resolution due to mixing of information from different depths.

Extended Data Figure 9 Flat sample geometry.

a, b, SEM images of a flat sample prepared from the Intel processor chip as a test of resolution and imaging with a sample orientation akin to that used in ptychographic X-ray laminography (PyXL) because the interconnect layers are now perpendicular to the direction of X-ray propagation. The remaining sample thickness was 12 μm. c, Reconstructed phase image 2D projection, pixel size 7.8 nm. In the laminography configuration, the rotation axis is perpendicular to the chip layers and non-perpendicular to the direction of the X-ray beam propagation. This allows arbitrarily extended samples to be measured and removes the need to obtain small cylindrical pillars. d, Fourier ring correlation (FRC) of two identical measurements indicates a resolution of 8.4 nm of the combined dataset using the half-bit criterion, that is, corresponding to the resolution of the average of the two datasets. The acquisition of one 2D dataset of this 5 μm × 5 μm area took 26 s, corresponding to 7,800 resels s−1. To obtain depth information, many such projections would need to be acquired at different orientations in the laminography measurement geometry.

Extended Data Figure 10 Fourier shell correlation of two projections of the measurements on the cylindrical (PXCT) sample from the Intel processor chip.

The FRC curves in a and b are shown in blue, and the 1-bit threshold in red. The pixel size of the reconstruction was 14.3 nm. a, FSC of projections recorded before the tomographic measurement, showing a single pixel resolution because the 1 bit threshold curve is never intersected. b FSC between one projection from before and one projection after the tomographic measurement. The correlation decreases to 16.4 nm (intersection at 0.87 spatial frequency/Nyquist). The decrease could result from radiation damage in the sample and/or drifts of the tomographic measurement set-up. The time between the measurement of these two projections is almost 24 h.

Supplementary information

3D rendering of the detector ASIC

This video shows the 3D rendering of the detector ASIC. (MOV 16337 kb)

3D rendering of the Intel® chip

This video shows 3D rendering of the Intel® chip. (MOV 12208 kb)

Axial slices of the Intel® chip

This video shows moving up and down through the axial slices of the Intel® chip. (MOV 7443 kb)

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Holler, M., Guizar-Sicairos, M., Tsai, E. et al. High-resolution non-destructive three-dimensional imaging of integrated circuits. Nature 543, 402–406 (2017). https://doi.org/10.1038/nature21698

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