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Programmable nanowire circuits for nanoprocessors

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A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up1,2,3. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes1,4,5,6,7,8, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array9, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor10,11 owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires12 coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of 960 μm2. The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input–output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

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Figure 1: Structure and characterization of the programmable NWFET.
Figure 2: Coupled NWFET devices and PNNTA architecture.
Figure 3: Fabrication, structure and logic function of a PNNTA tile.
Figure 4: Multifunctional PNNTA architecture.

Change history

  • 11 February 2011

    Figure 3d in the PDF was corrected on 11 February 2011


  1. Lu, W. & Lieber, C. M. Nanoelectronics from the bottom up. Nature Mater. 6, 841–850 (2007)

    ADS  CAS  Article  Google Scholar 

  2. Lu, W., Xie, P. & Lieber, C. M. Nanowire transistor performance limits and applications. IEEE Trans. Electron. Dev. 55, 2859–2876 (2008)

    ADS  CAS  Article  Google Scholar 

  3. Das, S. et al. Designs for ultra-tiny, special-purpose nanoelectronic circuits. IEEE Trans. Circuits Syst. Regul. Pap. 54, 2528–2540 (2007)

    Article  Google Scholar 

  4. Cui, Y. & Lieber, C. M. Functional nanoscale electronic devices assembled using silicon nanowire building blocks. Science 291, 851–853 (2001)

    ADS  CAS  Article  Google Scholar 

  5. Huang, Y. et al. Logic gates and computation from assembled nanowire building blocks. Science 294, 1313–1317 (2001)

    ADS  CAS  Article  Google Scholar 

  6. Zhong, Z. H., Wang, D. L., Cui, Y., Bockrath, M. W. & Lieber, C. M. Nanowire crossbar arrays as address decoders for integrated nanosystems. Science 302, 1377–1379 (2003)

    ADS  CAS  Article  Google Scholar 

  7. Bachtold, A., Hadley, P., Nakanishi, T. & Dekker, C. Logic circuits with carbon nanotube transistors. Science 294, 1317–1320 (2001)

    ADS  CAS  Article  Google Scholar 

  8. Javey, A. et al. High-κ dielectrics for advanced carbon-nanotube transistors and logic gates. Nature Mater. 1, 241–246 (2002)

    ADS  CAS  Article  Google Scholar 

  9. Borghetti, J. et al. ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature 464, 873–876 (2010)

    ADS  CAS  Article  Google Scholar 

  10. DeHon, A. Array-based architecture for FET-based, nanoscale electronics. IEEE Trans. Nanotechnol. 2, 23–32 (2003)

    ADS  Article  Google Scholar 

  11. Das, S., Rose, G. S., Ziegler, M. M., Picconatto, C. A. & Ellenbogen, J. C. Architectures and simulations for nanoprocessor systems integrated on the molecular scale. Lect. Notes Phys. 680, 479–513 (2005)

    ADS  CAS  Article  Google Scholar 

  12. Xiang, J. et al. Ge/Si nanowire heterostructures as high-performance field-effect transistors. Nature 441, 489–493 (2006)

    ADS  CAS  Article  Google Scholar 

  13. Liu, J., Wang, Q., Long, S. B., Zhang, M. H. & Liu, M. A metal/Al2O3/ZrO2/SiO2/Si (MAZOS) structure for high-performance non-volatile memory application. Semicond. Sci. Technol. 25, 055013 (2010)

    ADS  Article  Google Scholar 

  14. Sze, S. M. Physics of Semiconductor Devices 438–445 (Wiley, 1981)

    Google Scholar 

  15. Javey, A., Nam, S., Friedman, R. S., Yan, H. & Lieber, C. M. Layer-by-layer assembly of nanowires for three-dimensional, multifunctional electronics. Nano Lett. 7, 773–777 (2007)

    ADS  CAS  Article  Google Scholar 

  16. Snider, G., Kuekes, P. & Williams, R. S. CMOS-like logic in defective, nanoscale crossbars. Nanotechnology 15, 881–891 (2004)

    ADS  Article  Google Scholar 

  17. Whang, D., Jin, S., Wu, Y. & Lieber, C. M. Large-scale hierarchical organization of nanowire arrays for integrated nanosystems. Nano Lett. 3, 1255–1259 (2003)

    ADS  CAS  Article  Google Scholar 

  18. Sakamoto, W. et al. in Proc. Electronic Devices Meeting 2009, 10.1109/IEDM.2009.5424211 (IEEE, 2009)

    Google Scholar 

  19. Sedra, A. S. & Smith, K. C. Microelectronics Circuits 1014–1021 (Oxford Univ. Press, 2004)

    Google Scholar 

  20. Xia, Q. F. et al. Memristor-CMOS hybrid integrated circuits for reconfigurable logic. Nano Lett. 9, 3640–3645 (2009)

    ADS  CAS  Article  Google Scholar 

  21. Nam, S., Jiang, X. C., Xiong, Q. H., Ham, D. & Lieber, C. M. Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits. Proc. Natl Acad. Sci. USA 16, 21035–21038 (2009)

    ADS  Article  Google Scholar 

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We thank D. Bell and N. Antoniou for transmission electron microscopy sample preparation and imaging, Q. Qing for assistance with electrical measurements and J. L. Huang, X. Duan and X. Jiang for helpful discussions. C.M.L. acknowledges support from a National Security Science and Engineering Faculty Fellow award and a contract from the MITRE Corporation. S.D., J.F.K. and J.C.E. acknowledge support by the US government’s Nano-Enabled Technology Initiative and the MITRE Innovation Program.

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Authors and Affiliations



C.M.L., J.C.E., S.D., H.Y., H.S.C. and S.N. designed the experiments. H.Y., H.S.C., S.N., Y.H. and J.F.K. performed the experiments. S.D. performed simulations. H.Y., H.S.C., S.N., S.D., J.F.K., J.C.E. and C.M.L. analysed the data and wrote the paper. All authors discussed the results and commented on the manuscript.

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Correspondence to Shamik Das or Charles M. Lieber.

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The authors declare no competing financial interests.

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Yan, H., Choe, H., Nam, S. et al. Programmable nanowire circuits for nanoprocessors. Nature 470, 240–244 (2011).

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