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Electronic transport in nanometre-scale silicon-on-insulator membranes


The widely used ‘silicon-on-insulator’ (SOI) system consists of a layer of single-crystalline silicon supported on a silicon dioxide substrate. When this silicon layer (the template layer) is very thin, the assumption that an effectively infinite number of atoms contributes to its physical properties no longer applies, and new electronic, mechanical and thermodynamic phenomena arise1,2,3,4, distinct from those of bulk silicon. The development of unusual electronic properties with decreasing layer thickness is particularly important for silicon microelectronic devices, in which (001)-oriented SOI is often used5,6,7. Here we show—using scanning tunnelling microscopy, electronic transport measurements, and theory—that electronic conduction in thin SOI(001) is determined not by bulk dopants but by the interaction of surface or interface electronic energy levels with the ‘bulk’ band structure of the thin silicon template layer. This interaction enables high-mobility carrier conduction in nanometre-scale SOI; conduction in even the thinnest membranes or layers of Si(001) is therefore possible, independent of any considerations of bulk doping, provided that the proper surface or interface states are available to enable the thermal excitation of ‘bulk’ carriers in the silicon layer.

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Figure 1: Scanning tunnelling microscopy experiment and images of surfaces of clean SOI.
Figure 2: Proposed band diagrams showing interface, bulk and surface bands for ultrathin SOI.
Figure 3: Sheet resistance, as function of the Si layer thickness, of a thin Si membrane with different bounding layers.


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This research was supported by the US National Science Foundation, the US Department of Energy, and the US Air Force Office of Scientific Research.

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Correspondence to Max G. Lagally.

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Zhang, P., Tevaarwerk, E., Park, BN. et al. Electronic transport in nanometre-scale silicon-on-insulator membranes. Nature 439, 703–706 (2006).

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