Integrated circuits usually have only one layer of electronic devices, which limits their performance and functionality. A 3D integrated circuit that incorporates multiple device layers enables a wealth of applications. See Letter p.74
Integrated circuits are ubiquitous in modern electronic systems. Conventionally, they consist of a single layer of electronic devices and multiple layers of electrical connections (interconnects) that wire the devices to each other. Because there is a physical limit to how small such devices can be when they are created in two dimensions, researchers have targeted the third dimension to incorporate more device layers and continue the trend of increased integration density and functionality. On page 74, Shulaker et al.1 report a milestone in 3D integration. They present a fully functional prototype of a 'monolithic' 3D integrated circuit that brings together some of the most promising emerging device technologies in terms of sensing, memory and computing capabilities. To demonstrate it, the authors use the prototype to sense and distinguish between ambient gases and vapours.
Researchers began working on 3D integrated circuits almost two decades ago. In the first efforts, each stack, which contained a device layer and multiple interconnect layers, was fabricated separately. These stacks were then bonded, and wired by interconnects called through-silicon vias2. The separate fabrication was necessary to allow high-temperature annealing — rapid and precise heating of the device layers to temperatures3 greater than 1,000 °C — to activate dopants (impurities) in the devices that produce the desired electrical characteristics. Stacks could not be fabricated on top of each other because the annealing of one device layer would damage the interconnect structures of the underlying layers.
A major limitation of separate fabrication is that the diameter and pitch (separation) of the through-silicon vias need to be at least micrometre-sized. This constrains the density of the through-silicon vias that can be used, and therefore the bandwidth for data transfer in the 3D integrated circuits.
In the past few years, monolithic integration — in which additional device layers are built directly on top of the first layer — has gained momentum. Monolithic integration enables the fabrication of interconnects called inter-layer vias that have nanoscale diameters and pitches. This means that interconnects can be fabricated at 1,000 times the density of through-silicon vias, and allows data to be transferred through the integrated circuit at a much higher bandwidth and at lower power4.
To maintain the low temperatures3 (less than 400 °C) required for adding one or more device layers, a few methods have been proposed, depending on the target devices. For memory technology, it is possible to use non-silicon devices — for example, resistive random-access memory (RRAM) cells — that can be fabricated at such low temperatures5. For silicon-based transistors (electronic switches), a low-temperature method known as the μ-Czochralski process can be used, whereby laser pulses crystallize amorphous silicon6. For carbon-nanotube transistors, the nanotubes can be fabricated separately at high temperatures and then transferred to the integrated-circuit stack. The remaining parts of the transistors can then be directly fabricated on the stack using standard lithography techniques7.
Shulaker and colleagues used some of these developments in monolithic integration to create a 3D integrated circuit that can sense and distinguish between ambient gases and vapours, including nitrogen and vapours of lemon juice, vinegar and wine. Their integrated circuit is composed of four device layers (Fig. 1). The top layer comprises more than 1 million carbon-nanotube field-effect transistors (CNFETs) that act as sensors — the resistance of the CNFETs varies depending on the type of gas or vapour that is present. The layer beneath that contains RRAM cells that store the signals generated by the CNFET sensors. The RRAM cells are non-volatile, meaning that they retain information even when the power is switched off. Thanks to the monolithic integration of their integrated circuit, the authors were able to use densely packed inter-layer vias to achieve an unprecedented data-transfer bandwidth from the sensors to the RRAM cells.
The third layer down comprises an array of computational circuits built from CNFETs that use the sensor data captured in the RRAM cells to identify the gas or vapour. The identification is achieved using a machine-learning technique called support vector machines, in which data are classified on the basis of the results of previous training8. Finally, the bottom layer contains conventional silicon-based circuits that interface with the other layers to perform several required operations, such as reading data from the RRAM cells and steering these data to the computational circuits.
The authors' integrated-circuit design provides a path forward to address some of the hardest technological challenges in computing: namely, maximizing energy efficiency, scalability and communication bandwidth. The CNFETs used for the computations are considered to be some of the most promising low-power alternatives to existing silicon-based transistors9. The monolithic 3D integration circumvents the inherent physical limitations of scaling in 2D. The use of inter-layer vias, rather than through-silicon vias, provides a tremendous increase in communication bandwidth, which enhances performance and saves power. The non-volatile RRAM cells eliminate the need for an external memory system, improving both energy efficiency and scalability. Finally, the monolithic integration of sensors could lead to a new realm of computing applications.
Nevertheless, Shulaker and colleagues' fabrication process has room for improvement. For instance, the lithography technique that the authors used to fabricate their integrated circuit is based on a 1-micrometre technology node — the minimum feature size of the transistors is 1 μm — and requires an operating voltage of 3 volts. The technique therefore lags far behind state-of-the-art commercial integrated circuits that use 10- to 14-nm technology nodes and voltages of less than 1 V (see go.nature.com/2tngik1). Scaling the present system to use state-of-the-art fabrication technology could bring substantial improvements in integration density, connectivity, performance and power consumption. However, this scaling might be limited by physical and economic challenges3. The physical challenges arise from the increased temperatures generated when multiple device layers are operated in a relatively small volume. To alleviate this problem, 3D integrated circuits should incorporate cooling elements in the stack, such as thermally conductive heat-spreading structures or layers of convective microfluidic cooling channels.
A more practical limitation is yield, which is defined as the fraction of integrated circuits that are fully functional in a fabricated sample. As more layers are monolithically integrated, the probability of a defect in a particular integrated circuit increases, limiting the number of fabricated layers10. To mitigate this challenge, 3D integrated circuits will probably contain more redundant structures than conventional integrated circuits to compensate for defects. Nevertheless, unlocking the potential of monolithic 3D integration could usher in many applications that blend sensors, memory and computing. These applications include embedded smart cameras that have high-performance artificial-intelligence capabilities, intelligent robots that swim and deliver drugs through the bloodstream, and artificial retinas.