Radio-frequency application of graphene transistors is attracting much recent attention due to the high carrier mobility of graphene. The measured intrinsic cut-off frequency (fT) of graphene transistor generally increases with the reduced gate length (Lgate) till Lgate = 40 nm and the maximum measured fT has reached 300 GHz. Using ab initio quantum transport simulation, we reveal for the first time that fT of a graphene transistor still increases with the reduced Lgate when Lgate scales down to a few nm and reaches astonishing a few tens of THz. We observe a clear drain current saturation when a band gap is opened in graphene, with the maximum intrinsic voltage gain increased by a factor of 20. Our simulation strongly suggests it is possible to design a graphene transistor with an extraordinary high fT and drain current saturation by continuously shortening Lgate and opening a band gap.
Graphene is of particular interest for ultrahigh speed electronics due to its high carrier mobility and saturation velocity1,2,3,4,5,6. Because of its zero band gap, graphene field effect transistors (FETs) have a low on/off current ratio, which limits its application in logic devices. There is still a lack of reliable techniques to open a sizable gap without degrading the electronic properties of graphene. However, a large on/off ratio is not necessary for radio frequency (r. f.) electronic applications6, which are the core elements in wireless communication devices. Developing the high-performance r. f. graphene transistors is attracting enormous recent attention7,8,9,10,11,12,13,14,15,16. In order to facilitate high-performance r. f. applications, FETs should respond quickly to the gate voltage (Vg), which requires short gates6. Extensive gate length (Lgate) scaling work of graphene FETs has been experimentally pursued9,10,11,12,13,14, with the gate length scaling down to 40 nm14. The intrinsic cut-off frequency (fT) represents how fast the channel current is modulated by the gate and is one of the most important figure-of-merit for evaluating the performance of r. f. devices. All these experimental investigations reveal that fT of graphene transistors generally increases with the decreasing Lgate. The measured maximum fT is 300 GHz for a graphene FET with Lgate = 144 nm based on exfoliated graphene10. The maximum fT estimated from the static measurement is 1.4 THz from a graphene FET with Lgate = 45 nm fabricated by a self-aligned approach9. Therefore, as far as fT is concerned, graphene FETs have significantly outperformed conventional silicon metal-oxide-semiconductor field effect transistors (MOSFETs) with a highest measured fT of 485 GHz at Lgate = 29 nm6,17 and III-V high-electron-mobility transistors (HEMTs) with a highest measured fT of 660 GHz at Lgate = 20 nm for GaAs6.
However, the fT value does not always increase with the reduced Lgate in a transistor when Lgate approaches the size limit. For example, fT of GaAs metamorphic HEMT peaks at Lgate = 20 nm and then it slightly decreases with the reduced Lgate6. One fundamental issue arises naturally: is there a saturation of fT with the reduced Lgate in graphene FETs? If such a saturation is absent, a higher intrinsic cut-off frequency, even up to tens of terahertz (THz), can be obtained via continuously shortening Lgate to a few nm in graphene FETs. Besides fT, the maximum oscillation frequency (fmax) and intrinsic voltage gain (Av) are the other two important figure-of-merits evaluating the r. f. performance of devices. To obtain a high fmax and Av, a drain current saturation is required. Although a drain current saturation has been reported in some monolayer graphene (MLG) FET devices due to phonon scatter limited velocity saturation18 and in a dual-gated bilayer graphene (BLG) FET device due to an electrical-field-induced band gap opening19, all the existing short-channel graphene FETs with Lgate below 300 nm suffer from a lack of drain current saturation12,14, which lead to a small output conductance and a poor fmax and Av. Another fundamental issue of graphene FETs is: is there an effective method to induce a drain current saturation in sub-10 nm scale?
In this article, we investigate theoretically for the first time the performance limit of top-gated graphene FETs with the gate length scaling down from 9.86 to 0.91 nm using the density functional theory (DFT) coupled with the nonequilibrium Green's function (NEGF) method. We demonstrate that switching effects remain in such short gate graphene transistors. Remarkably, fT still increases with the decreasing Lgate, with values of 3.4–21 THz. The absence of a saturation in fT with the reduced Lgate clearly shows that fT of graphene transistors can be continuously improved by shortening Lgate. In order to create a drain current saturation, we design two schemes: one is a dual-gated FET made of a MLG sandwiched between two hexagonal boron nitride (h-BN) layers and the other is a dual-gated FET made of a pure BLG. A significant current saturation has been observed in both FETs under a proper vertical electrical field and the maximum voltage gain has been increased up to 2.3 and 1.5, respectively, a factor of 20 and 13 higher than that of pure MLG FETs. Experimentally, sub-10 nm gate length carbon nanotube transistors have been recently manufactured via top-down approach20. It has been pointed out by Duan et al. that a sub-10 nm gate length graphene FET can be realized by using the self-aligned approach with a sub-10 nm nanowire as the top gate9. Finally, we envision an alternative method to fabricate a sub-10 nm graphene transistor, namely, using a sub-10 nm diameter boron nitride (BN) or carbon nanotube as the top gate. We expect our work can inspire experimentalists to further push graphene transistors to performance limit by continuously shortening Lgate and opening a band gap.
In an actual graphene FET, metal is always used to contact graphene as electrodes. In our schematic model of a MLG FET presented at Fig. 1, we design the graphene channel contacted underneath two aluminum (Al) electrodes (source and drain). The distance between Al contact and graphene layer is 0.34 nm, according to the previous work21,22. We further set the thickness of the dielectric region to be di = 1.4 nm and the dielectric constant to be εr = 3.9, which models after SiO2.
As the gate of FETs scales down to very short lengths, like sub-10 nm region, the transport mechanism turns from channel-dominated diffusive regime to the contact-dominated ballistic regime, so the contact effect between the metal electrode and the channel becomes very important for the device transport properties20,23. We first study the contact effect between the aluminum (Al) electrode and graphene. In Fig. 2(a) and (b), we show the projected density of states (PDOS) on the carbon (C) atoms of graphene in the left/right lead (gL/R(E)) and in the channel (gch(E)), respectively, for a graphene FET with Lgate = 5.6 nm under zero drain-source voltage and zero gate voltage. The inset in Fig. 2(a) is the density of states (DOS) of the pure MLG graphene, with the Dirac point exactly at the Fermi level (Ef). We find that the Dirac points of graphene in the left/right lead (DL/R) and in the channel (Dch) are shifted to DL/R = Ef − 0.9 eV and Dch = Ef − 0.25 eV, respectively, indicative of heavy n-doping of graphene in the contact part and light n-doping in the channel part by Al contact. This contact effect is also reflected on the transmission spectrum of this device. As shown in Fig. 2(c), there are two transmission minima in the transmission spectrum of this graphene FET but only one minimum in the transmission spectrum of the corresponding MLG FET without being contacted underneath Al electrodes (See the inset in Fig. 2(c)). The transmission coefficient of the device T(E) behaves like three resistors composed of the channel and the two electrodes in series24,25,26:
The two minima in the transmission spectrum originate from the DL/R in gL/R(E) and Dch in gch(E), respectively. Consequently, there is a lack of symmetry in the transmission spectrum with respect to both DL/R and Dch, causing the asymmetry in electron and hole conductance. The existence of two minima in the transmission spectrum and electron-hole conductance asymmetry agrees well with both previous theoretical and experimental works24,25,27,28,29,30.
Fig. 3(a) shows the transmission spectra of this device under Vg = 6.0, −3.0 and −5.0 V with a fixed bias voltage of Vds = 0.5 V. There are three transmission minima (DL, DR and Dch) in each transmission spectrum because DL and DR are separated by the bias voltage. DL and DR are unchanged by Vg. However, Dch is shifted by Vg: first it is at Ef under Vg = −5 V, then shifted to Ef −0.25 eV under Vg = −3 V and finally shifted to Ef − 0.9 eV under Vg = 6 V. This shift of Dch with Vg in the transmission spectrum stems from the shift of Dch with Vg in gch(E), as shown in Fig. 3(b). As Dch is at Ef (Vg = −5 V), the T(E) values within the bias window are small and the current is minimized (off-state). As Dch is moved gradually out from the bias window, the T(E) values within the bias window increase, the currents increase gradually and the FET is finally switched from the off-state (Vg = −5 V) to the on-state (Vg = 6 V). The on/off current ratio of this device is 13.3.
We calculate the transmission eigenvalues of all the k-points in the 1D Brillouin zone at Ef. For a given energy E, the transmission coefficient T(E) is given by
where λn are the eigenvalues of the transmission matrix T. In Fig. S1 of Supplementary Information, we show the transmission coefficients T(Ef, k) as a function of k of the off-state (Vg = −5.0 V, black curve) and the on-state (Vg = 6.0 V, red curve) in the 1D Brillouin zone. The width and height of the T(Ef, k) spectrum for the on-state are much larger than those for the off-state and therefore the total transmission factor T(Ef) of the on-state is larger than that of the off-state. To visualize the difference between the off- and on-state of this graphene FET, we choose the (2π/5a, 0) point of the k-space at Ef and show its transmission eigenchannel in the off-state (left panel) and on-state (right panel) in Fig. 3(c). The largest transmission eigenvalue at this point of the off-state is λ1 = 1.1 × 10−3 and the rest are nearly zero; correspondingly, the incoming wave function is almost completely scattered and unable to reach the other lead. In contrast, the largest transmission eigenvalue at this point of the on-state is λ1 = 0.97 and the rest are also nearly zero; consequently, the incoming wave function is scattered little and most of the incoming wave reaches the other lead.
We show the transfer characteristics of the devices with Lgate scaling down from 9.86 to 0.91 nm in Fig. 4(a), at a fixed drain-source voltage of Vds = 0.5 V. As expected, all of them show an n-type feature. The on-currents, which are defined as the current at Vg = 6.0 V, remain almost constant for all the Lgate. By contrast, the leakage currents in the off-state increase with the decreasing Lgate. As shown in Fig. 4(b), the on/off current ratio drops significantly from 15.8 at Lgate = 9.86 nm to 3.35 at Lgate = 0.91 nm and this scaling trend agrees with the experimental results for short gate graphene FETs (Lgate = 5.6 um – 50 nm)12,23. Such a scaling behavior is attributed to the increasing off-state leakage current with the decreased Lgate: as the gate scales down to very short lengths, the off-state average PDOS on each C atom of the channel graphene at Dch increases (Fig. S2, Supplementary Information) and the channel graphene behaves more like metal and away from semi-metal. Our calculated on/off ratio of MLG FETs is larger than the previous experimental data (For example, in the work of Wu et al., the on/off current ratios are about 3.5–6 for p-type graphene FETs with Lgate = 50–500 nm)23. This difference is mainly ascribed to the fact that the thickness of the dielectric region in our model is only 1.4 nm, which is much thinner than those (90 nm in Ref. 30) of the experimental devices. The effect of the thickness of the dielectric region on the performance of graphene FETs has been studied in detail by Guo et al.31. They find that a thinner dielectric region will improve the on/off current ratio and transconductance significantly because the gate modulation is more effective as the dielectric region becomes thinner. The method to fabricate an ultrathin dielectric (sub-10 nm) will be discussed in the next section.
Transconductance gm is another important parameter to characterize switching effect of an electronic device and can be extracted from the transfer characteristics. In Fig. 4(c), we present its dependence on Lgate. The gm values first decrease slowly from 3670 μS/μm at Lgate = 9.86 nm to 2900 μS/μm at Lgate = 2.19 nm and then start to drop dramatically to 1296 μS/μm at Lgate = 0.91 nm. The reduced gm with the reduced Lgate agrees with both previous experimental and theoretical results13,31 and is not favorable for fT. We attribute the reduced gm to the increasing leakage current and the shift of Dirac voltage (VDirac, defined as the gate voltage at the point of the off-state). The increasing leakage current is apparent. The shift of VDirac can be seen in the transfer characteristics shown in Fig. 4(a). The shift is remarkable when Lgate scales below 2.19 nm (from VDirac = −8 to −22 V as Lgate scales from 2.19 to 0.9 nm), which is responsible for the dramatic drop of gm. The main reason for the shift of VDirac is the short channel effect32,33: when the Lgate is very small, the electrostatic potential profile is strongly affected by the drain-source potential and a bigger gate voltage is needed to turn off the channel. We notice that gm = 3670 μS/μm of our results at Lgate = 9.86 nm is larger than 2300 μS/μm for a self-aligned graphene FET with Lgate = 90 nm at Vds = 1.0 V reported experimentally by Duan et al.9. This difference is also owing to the extremely thin dielectric region in our model compared with the experiment.
To get fT, we need to calculate another key parameter: the intrinsic gate capacitance Cg. As shown in Fig. 4(d), Cg decreases approximately linearly with Lgate, because Cg is related to Lgate through the following equation14: Cg = ε0εrWgateLgate/tox, where ε0 is the dielectric constant of vacuum, εr the relative dielectric constant of the gate dielectric, Wgate the gate width and tox the gate dielectric thickness. Actually, besides Cg, transistors also include another kind of capacitance named parasitic capacitance (Cp), which exists between the gate and source (drain) electrode and is an important parameter to determine the extrinsic cut-off frequency (fT, ex): fT, ex = gm/(Cg + Cp)15. Ideally, one can make fT, ex close to fT through reducing the parasitic capacitance, such as by redesigning the device layout and reducing the total parasitic series resistance between the device's source (drain) electrode and the gate to increase the current density10,34,35.
Fig. 4(e) shows Lgate dependence of fT based on the calculated gm and Cg. fT increases monotonically from 3.4 to 21 THz as Lgate scales down from 9.86 to 0.91 nm, because Cg reduces faster than gm with the reduced Lgate. We notice that fT exhibits a 1/Lgate dependence as Lgate scales from 9.86 to 2.19 nm, which agrees well with the scaling trend reported experimentally by Wu et al. with Lgate from 550 to 40 nm14. The 1/Lgate scaling trend suggests that the transport of our devices is in the contact-dominated ballistic regime and the electric field along the channel is dominated by the value of the contact resistance at the device's source (drain)14. This 1/Lgate dependence is also usually observed for short-channel conventional Si and III-V FETs14. As Lgate scales below 2.19 nm, the scaling trend deviates from the 1/Lgate dependence, due to the dramatic drop of gm. The product fTLgate = gmtox/2πε0εrWgate is expected to be linearly proportional to gm for devices with the same parameters and dimensions. In Fig. 4(f), we show the plot of fTLgate against gm and it exhibits the expected linear dependence.
We summarize the gate length scaling works of the intrinsic cut-off frequency for MLG FETs in Fig. 5. An increase trend of fT with the reduced Lgate is available in all works. Almost all the data can be roughly fitted by the uniform fT = a/Lgate relation (a = 38600 GHz nm) except that the data based on CVD grown graphene has a different coefficient (a = 8000 GHz nm). It is noteworthy that in the 40–100 nm region, the theoretical fT data obtained by Guo et al. using a self-consistent ballistic quantum transport simulation approach with the NEGF formalism31 agrees well with those reported by Duan et al. with a self-aligned approach9. This agreement shows the reliability of the quantum transport simulation in predicting fT of graphene FETs and the condition will be discussed in the next section.
We study the output characteristics of a graphene FET with Lgate = 6.4 nm and show them in Fig. 6(a). The source-drain ballistic current increases linearly with the applied bias voltage in the checked bias region. In most experimental graphene FET devices, the absence of drain current saturation degrades the maximum oscillation frequency (fmax) and the intrinsic voltage gain (Av), which represent how fast power transmission is modulated by the gate and the amplification factor of an input signal, respectively. fmax is defined as the frequency at which the power gain becomes unity and a typical approximation for it is 36, where gd is the output conductance, Rg the gate resistance and Rds the drain-source resistance. Av is defined as Av = gm/gd.
The reason of the absence of current saturation in graphene FET devices is attributed to zero band gap of graphene, high electrical resistance between the device's source and drain electrode and its gate and the short channel effect6,32,33,37. One way to get current saturation is to open a band gap in graphene6. Both theoretical and experimental works show that a vertical external electric field can induce a tunable band gap up to 0.25 eV for BLG without degrading the electronic properties of graphene38,39,40 and a current saturation in BLG FETs (Lgate = 4 ~ 9 μm) is indeed observed and reproduced in a simulation (Lgate = 40 nm) within the tight-binding Hamiltonian and NEGF formalism as a result of the band gap opening19,40. Our previous theoretical work predicts that a vertical external electric field can induce a tunable band gap up to 0.34 eV for a MLG properly sandwiched between two h-BN single layers without degrading the electronic properties of graphene41. Such a BN/MLG/BN sandwich structure has been prepared experimentally recently42.
The schematic model of a dual-gated graphene BN/MLG/BN sandwich FET with Lgate = 6.4 nm and a dual gated BLG FET with Lgate = 9.6 nm are presented in Fig. 1 (b) and (c) and the two individual gates allow us to create a larger band gap and tune channel's conductance individually. The device performance of MLG and BLG FET with the same Lgate is similar if the band gap of BLG is not opened19. The vertical electrical field applied to sandwich structure is obtained as. The corresponding total gate voltage is , reflecting the total doping level. In Fig. 6(b), we compare the simulated output characteristics of a pure MLG FET and a BN/MLG/BN sandwich FET (under a vertical external electric field of −1 V/Å) with the same Lgate. A significant current saturation appears for the sandwich FET at Vg = −1.6, −2.0 and −2.4 V (a positive gate voltage has no such effect) and its output conductance gd is lowered at most by a factor of 80 compared with the pure MLG FET. The calculated Cg of this sandwich FET is nearly intact and gm is a quarter of those of the pure MLG FET (its transfer characteristics are shown in Fig. S3(a)) and the fT of this sandwich FET is 1.5 THz (it is degraded by a factor of 4 compared with a value of 6.35 THz for the pure MLG FET with the same Lgate). The maximum Av of this device is therefore increased to 2.3, a factor of 20 higher than that of the pure MLG FET (the experimental enhancement factor and simulation enhancement factor of Av for BLG FETs (Lgate = 4–9 μm experimentally and 40 nm theoretically) by a vertical external electric field are 6 and 10, respectively)19. The fmax is increased by a factor of 2 if we assume that Wgate is 1 μm, Rds 980 Ω and Rg 47 Ω16. We also observe a significant current saturation in the output characteristics of the BLG FET at Vg = −4.0 V under a vertical external electric field of 3 V/nm (Fig. 6(c)) and its output conductance gd is lowered at most by a factor of 40 compared with the pure MLG FET with the same Lgate. The calculated Cg of this BLG FET is nearly intact with the pure MLG FET with the same Lgate and gm is one third of those of the pure MLG FET (its transfer characteristics are shown in Fig. S3(b)), the fT is 1.1 THz (it is degraded by a factor of 3 compared with a value of 3.4 THz for the pure MLG with the same Lgate), the maximum Av is increased to 1.5 and the fmax is increased by a factor of 1.6. Therefore it is possible to design a sub-10 nm graphene FET that can operate at extraordinary high fT and with greatly improved Av by introducing a band gap in graphene. The gain factor in gd and Av is one order of magnitude larger than the degradation one in fT. Besides the sandwich and bilayer scheme, adsorption of Li on MLG and formation of LiC6 structure43 is able to open a larger band gap of about 0.4 eV and thus LiC6 monolayer is also a proper candidate of the channel of MLG FET with a current saturation. Since MLG grown on insulating SiC substrate already has a band gap of 0.26 eV44, we can alternatively use a single-gated MLG grown on SiC as the channel to create a drain current saturation although a simulation of such a device is a challenge due to the difficulty to reproduce a band gap in the calculation45,46.
The mechanism of the current saturation in the BN/MLG/BN sandwich FET and the BLG FET can be both attributed to the band gap induced by the vertical external electric field. Taking the BN/MLG/BN sandwich FET for example, the band gap improves the electrostatic pinch-off of the channel, which is reflected on the transmission spectrum of this device (Fig. 6(d)). The center of the transport gap (Δ ~ 0.13 eV) induced by the vertical external electric field is about 0.06 eV above Ef at Vds = 0.2 V. As the Vds increases from 0.2 to 0.25 V, the bias voltage shifts the transport gap to the left. Namely, the bias voltage functions like a positive gate voltage here. As a result, the integral area of the transmission coefficients within the bias window at Vds = 0.25 V is almost the same as that at Vds = 0.2 V and the current is thus saturated. From the point view of transport theory, the ability of a bias voltage to shift the transmission spectrum is as important as the opening of a band gap of graphene to create a drain current saturation. If the bias voltage does not shift the transmission spectrum, the current will not be saturated. The similar drain current saturation mechanism of the BLG FET is provided in Supplementary Information (Fig. S4).
To fabricate short-channel graphene transistors, Duan et al. used an ultrathin nanowire as the top gate and the gate length depends on the diameter of the nanowire9,10,35. In principle, sub-10 nm gate length graphene transistors can be fabricated by this way if a sub-10 nm diameter nanowire is used as the top-gate9. In view of the difficulty to fabricate sub-10 nm diameter nanowires, we suggest to use a sub-10 nm diameter BN or carbon nanotube, which is experimentally accessible, as an alternative top gate. We build a graphene and (5, 0) BN nanotube junction model (Fig. 7(a)) and simulate its I-Vbias characteristic curve (Fig. 7(b)). The diameter of this BN nanotube is 0.4 nm and the band gap of it is 2.15 eV. A clear rectification is observed and there is little leakage current between the graphene channel and the BN nanotube when the bias voltage is below 1.0 V, indicating that the BN nanotube itself can function as the local gate with the interface depletion layer in the BN nanotube as a gate dielectric9. We can also use sub-10 nm diameter metallic carbon nanotubes as the local gate. In this case, a few h-BN layers (sub-10 nm thick) can be used as high-quality dielectrics16.
Two factors are critical to ensure the high performance in our sub-10 nm gate length graphene transistors: ultrathin dielectric (1.4 nm) and very small access resistance due to the very small gaps (0.32 nm) between the gated graphene channel and source/drain contacts. An ultrathin dielectric implies a better gate modulation on the channel current31. If we use sub-10 nm diameter semiconducting nanowires, BN nanotubes, or carbon nanotubes as the top-gate to fabricate sub-10 nm graphene transistors, the dielectric region is the depletion layer, whose thickness can be controlled by doping concentration and is obviously smaller than the nanowire/nanotube diameters. Therefore, the ultra-thin dielectric (a few nm) can be realized in such fabrication schemes. If we use sub-10 nm diameter metallic nanowires or carbon nanotubes as the local gate and a few h-BN layers (sub-10 nm thick) as dielectrics, the ultra-thin dielectric can also be realized.
A substantial access resistance due to the significant gaps between source/drain and gate electrodes (a large portion of the graphene channel in the gap area is not gated) limits the achievable transconductance and has adverse impact on short channel devices9,47,48. Experimentally, the access resistance has been significantly reduced with a self-alignment approach9,10,47, through which the edges of the source, drain and gate electrodes are automatically and precisely positioned so that no overlap and significant gaps exist between them. This process improves the transconductance and the drain current density significantly9,10,47 and a slight current saturation was even observed35. As a result, this self-alignment approach finally improves the r. f. performance of short-channel graphene transistors. For example, the fT values estimated from the static measurement of graphene FETs by Duan et al. in the 40–100 nm gate region have reached 700 ~ 1400 GHz as a result of ultrathin dielectric and ultrasmall access resistance. Such a fT-Lgate relation agrees well with the simulation reported by Guo et al. within a model also with an ultrathin dielectric (16 nm) and an ultrasmall access resistance due to the ultrasmall distance between the source/drain and gate electrodes9,31.
In our model, we assume that electron transport is in the ballistic region. Another issue we need to discuss here is the probable roles of electron-phonon scattering. For carbon nanotubes, some works on this issue reveal that the measured or calculated high-field electron mean free path (MFP) is about 10 nm or longer due to optical phonon scattering and the low-field MFP 1600 nm due to acoustic phonon scattering49,50,51. The experimental and theoretical work by Dai et al. also points out that transport through very short (~10 nm) nanotubes is free of significant acoustic and optical phonon scattering and thus ballistic and quasiballistic at the low and high field limit, respectively51. For graphene, the measured electron MFP is from tens to hundreds of nanometers on rugged SiO2 substrate, depending on the carrier concentration52 and several micrometers in suspended ultraclean membranes53 or in graphene encapsulated between inert and ultraflat h-BN layers at room temperature54,55. The channel of our graphene transistor is sub-10 nm, which is much smaller than electron MFP of graphene on smooth h-BN substrate or even on rugged SiO2 substrate in high carrier concentration, so the transport mechanism should be safely in the ballistic regime if a smooth substrate is used and the Landau- Büttiker transport formalism is applicable.
In summary, we have investigated the switching effect and r. f. performance of the sub-10 nm gate length graphene FETs with Al electrodes by employing ab initio quantum transport simulation for the first time. We find that switching effects remain in these ultra-short gate graphene transistors. The intrinsic cut-off frequency increases monotonically from 3.4 to 21 THz, which are a few to tens of times larger than the experimental maximum values of the competitive r. f. FETs6, when the gate length scales down from 9.86 to 0.91 nm. A significant current saturation can be created in sub-10 nm graphene FETs by introducing a band gap to graphene. We expect that our theoretical work can stimulate experimental fabrication of sub-10 nm gate length graphene FETs operating at an intrinsic cut-off frequency exceeding the available best experimental values and with current saturation.
The current of graphene FETs under a finite drain-source voltage (Vds) and gate voltage (Vg) is computed using the Landauer-Büttiker formula56
where fL/R are the Fermi-Dirac distribution function for the left (L)/right (R) electrode, μL/μR are the electrochemical potential of the left (L)/right (R) electrode and T(E, Vds, Vg) is the transmission coefficient. T(E) is calculated by using the Fisher and Lee relationship57.
Then, the gate effect is calculated by solving the Poisson and Kohn-Sham equations self-consistently with the fixed boundary condition56. Namely, we first calculate the Hartree potential VH from the Poisson equation: , where the initial electron density ρ(r) is computed from the DFT and NEGF methods under no gate voltage. Afterward the new Hartree potential is used to calculate a new electron density by solving the Kohn-Sham equation. These procedures are iterated until the desired numerical accuracy is reached, which at present are carried out by using the well developed ATK 11.2 package58,59,60. Single-zeta (SZ) basis set is used, the real-space mesh cutoff is 150 Ry and the temperature is set at 300 K. The local-density-approximation (LDA) is employed for the exchange–correlation functional. The electronic structures of electrodes and central region are calculated with a Monkhorst–Pack61 50 × 1 × 100 and 50 × 1 × 1 k-point grid, respectively.
where fT is determined by the intrinsic gate capacitance Cg and the transconductance gm, which are computed from
where Qch is the total charge of the channel and Ids the drain-source current.
In our previous work, we used the same DFT + NEGF approach to simulate the transport properties of sub-10 nm functionalized metallic single-walled carbon nanotube FETs and pentacene molecule FETs62. The reliability of this approach to simulate sub-10 nm FETs is verified from the fact that the order of magnitude of the calculated on/off ratio and the on-current of our results basically agree with the experimental data for the sub-10 nm single-walled carbon nanotube transistors and pentacene molecule FETs20,63. For example, our calculated on/off ratio and on-current for a pentacene molecule FET with Lgate = 0.8 nm are ~102 and 7.0 × 10−2 μA respectively, comparable with the experimental on/off ratio of ~103 and on-current of ~3.0 × 10−2 μA for a pentacene molecule FET with Lgate ≈ 1–3 nm63.
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This work was supported by the NSFC (Grant Nos. 11274016, 51072007, 91021017, 11047018 and 60890193), the National Basic Research Program of China (Nos. 2013CB932604 and 2012CB619304, MOST of China) Program for New Century Excellent Talents in University of MOE, Fundamental Research Funds for the Central Universities, National Foundation for Fostering Talents of Basic Science (No. J1030310/No. J1103205) of China and Nebraska Research Initiative and DOE DE-EE0003174 in the United States.
The authors declare no competing financial interests.
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Zheng, J., Wang, L., Quhe, R. et al. Sub-10 nm Gate Length Graphene Transistors: Operating at Terahertz Frequencies with Current Saturation. Sci Rep 3, 1314 (2013). https://doi.org/10.1038/srep01314
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