The out-of-plane electric polarization at the surface of SrTiO3 (STO), an archetypal perovskite oxide, may stabilize new electronic states and/or host novel device functionality. This is particularly significant in proximity to atomically thin membranes, such as graphene, although a quantitative understanding of the polarization across graphene–STO interface remains experimentally elusive. Here, we report direct observation and measurement of a large intrinsic out-of-plane polarization at the interface of single-layer graphene and TiO2-terminated STO (100) crystal. Using a unique temperature dependence of anti-hysteretic gate-transfer characteristics in dual-gated graphene-on-STO field-effect transistors, we estimate the polarization to be as large as ≈12 μC cm−2, which is also supported by the density functional theory calculations and low-frequency noise measurements. The anti-hysteretic transfer characteristics is quantitatively shown to arise from an interplay of band bending at the STO surface and electrostatic potential due to interface polarization, which may be a generic feature in hybrid electronic devices from two-dimensional materials and perovskite oxides.
The rich and diverse phenomenology of perovskite oxides,1,2,3,4 which includes electronic and structural phase transitions, colossal magnetoresistance to ferroelectricity and superconductivity, holds great promise for new concepts in device technology and material engineering. The crystal structure of SrTiO3 (STO), a crucial member of the perovskite oxide family that forms the building block of complex oxide heterostructures,5,6 is centrosymmetric and hence a paraelectric in the bulk. STO approaches an incipient ferroelectric state at low temperatures, but quantum fluctuations prohibit a long-range ferroelectric order to develop.7 The quest for stabilizing ferroelectricity in STO has a long history, and it is now known that chemical doping,8,9 nanostructuring,10 manipulation of oxygen stoichiometry11,12 or application of inhomogeneous deformation (flexoelectricity)13 can cause spontaneous electric polarization in the bulk. However, the surface of a STO (100) crystal, in both TiO2 and SrO terminations, can intrinsically host out-of-plane dipole moments due to inversion symmetry breaking at surface, where the Ti or the Sr ions are vertically displaced away from the corresponding oxygen planes. Although surface reconstruction in STO has been established with multiple spectroscopic14,15,16 and surface topography16,17 probes, a direct evaluation of the resulting electric polarization has been difficult. Experiments with piezoresponse force microscopy17,18 and flexoelectric response13 yield surface polarization of ~0.5–10 μC cm−2, which is strongly influenced by local oxygen stoichiometry,19,20 grain boundaries20,21 or surface strain.20 Apart from the natural relevance to in-built ferroelectricity, the importance of surface electrostatics in STO is paramount because it can directly impact charge transfer superconductivity,6 oxide heterostructures5,22,23 and two-dimensional (2D) electronics as active substrates.24,25,26
Hybrid field-effect transistors (FETs) from atomic membranes of layered solids such as graphene and molybdenum disulfide (MoS2) on STO substrate aim to combine the high crystallinity and atomically clean interface to spectacular bulk dielectric properties of STO (dielectric constant >104 at low temperatures). It is however unclear if the out-of-plane polarization at the STO surface is stable in the presence of graphene, for example, against possible atomic reorganization and screening. Recent observations of (anti-)hysteretic gate-transfer characteristics at slow sweep rates in graphene FETs fabricated on STO(100) substrate25,26 are attributed to “ferroelectric-like” electric polarization at the STO surface, which indeed bear close resemblance to transfer characteristics of graphene FET on ferroelectric substrates.27,28,29,30,31 While this has been described as the effect of gate voltage-dependent dynamic trapping and detrapping of charge at the channel–substrate interface, identifying the microscopic origin of such interface states, and its connection to electric polarization at the surface, remains an outstanding experimental challenge.
Here we have probed the interface of graphene and STO by constructing dual-gated graphene-on-STO FETs, which allow direct calibration of the graphene–STO interface against the interface between graphene and hexagonal boron nitride (hBN), a conventional trap-free32 well-characterized dielectric for graphene devices. While the transfer characteristics using hBN top gate shows no hysteresis, that using STO back gate becomes strongly anti-hysteretic at low temperature (≲200 K), which is quantitatively associated with in-built electric polarization at the graphene–STO interface. From detailed temperature dependence of the anti-hysteresis, and independently from noise measurements, we estimate out-of-plane polarization magnitude P ~ 12 μC cm−2, which also agrees with that obtained from density functional theory (DFT) calculations within a factor of two. We have also developed a phenomenological model for anti-hysteretic transfer characteristics using band reconstruction and electrostatic potential at the STO surface, which may be applicable to graphene FETs on other polarized substrates as well.
Results and discussion
Device fabrication and electrical measurement
The transport and 1/f noise measurements were carried out in a dual-gated single-layer graphene (SLG) field-effect transistor with hBN as the top gate and STO as the back gate dielectric. The schematic of a typical dual-gated SLG transistor with the electrical layout is shown in Fig. 1a. The TiO2 surface termination of the 0.5 mm thick STO (100) substrate (from CrysTec GmbH) was achieved through chemical processes and annealing (Fig. S1 in Supplementary Information). The SLG and hBN flakes were exfoliated on SiO2/Si++ substrates, and subsequently transferred onto the TiO2−terminated surface of STO through van der Waals epitaxy33,34 (see Methods for more details). The layer number of graphene was verified by Raman spectroscopy as shown in Fig. 1d. The absence of D peak at 1350 cm−1 in the Raman spectrum confirms a defect-free graphene channel. The metal contacts were patterned by e-beam lithography followed by thermal deposition of 5/50 nm of chromium/gold. The optical microscope image of the SLG/hBN heterostructure before transferring onto STO, and the dual-gated transistor after depositing contact pads, are shown in Fig. 1b, c, respectively. All measurements of resistance and noise were carried out using low-frequency AC technique34,35,36,37,38,39,40 in four probe geometry under high vacuum condition (~10−5 torr). The carrier mobility of the graphene channel, similar for both electrons and holes, was found to be ~2000 cm2 Vs−1 at 140 K which increases to ~7300 cm2 Vs−1 at 10 K, in agreement with recent experimental report24 (Fig. S2 in the Supplementary Information). The resistivity of the graphene channel increases with increasing temperature upto ~60 K beyond which it either saturates or decreases marginally (Fig. S3 in the Supplementary Information).
Measurement of dielectric constant of STO
The resistance of the dual-gated SLG transistor with varying top gate voltage (VTG) shows conventional bell curve with a charge neutrality point (CNP) or Dirac point at V (Fig. 1e). The hysteresis in the top gate sweep is nearly negligible, as expected from trap-free interface of SLG and hBN.32,41 The dual-gated geometry allows a direct measurement of the dielectric constant of STO () from the locus of the CNP in the (VTG, VBG) space, which balances the STO back gate capacitance with the known capacitance of hBN top gate. In Fig. 1f, the resistance (at T = 100 K) of the dual-gated SLG transistor is shown while sweeping VTG at different fixed back gate voltages (VBG). The CNP () shifts expectedly to the left with increasing VBG.42,43 Plotting vs. VBG (Fig. 1g) gives a straight line which can be fitted with the equation,
where CB and CT are the capacitances of the back gate with STO as dielectric and the top gate with hBN as dielectric, respectively, n0 is the intrinsic carrier density in graphene and e is the electronic charge. Since CT (=2.7 × 10−3 F m−2) is known from the thickness of hBN (≈13 nm, measured from atomic force microscopy), we obtain the dielectric constant (dSTO being the thickness of STO and ε0 the vacuum permittivity) (also see Fig. S4 in the Supplementary Information). The magnitude of , measured at different temperatures, as shown in Fig. 1h, are in agreement with previous reports7,44,45,46,47 and matches well with the value of estimated from Hall measurement at low temperatures. This agreement confirms that both graphene–hBN and graphene–STO interfaces in our device are atomically clean, and free of undesired adsorbates and chemical species.
Anti-hysteretic transfer characteristics
Unlike the top gate, sweeping of the back gate voltage VBG in forward and reverse directions led to strong anti-hysteresis in the transfer characteristics. The extent of anti-hysteresis depends on both temperature and sweep range of VBG. As shown in Fig. 2a, the anti-hysteresis decreases with increasing temperature and vanishes at the temperature range of 150–180 K whereas, it decreases with decreasing sweep range (Fig. 2b). See Fig. S5 in the Supplementary Information for results from different devices. Hysteretic transfer characteristics in graphene FET48 on SiO2 and other substrates49,50,51 are commonly attributed to slow charge transfer in the presence of impurity states and absorbed water molecules. Although our experiment was performed under high vacuum condition, and the collapse of the anti-hysteretic transfer characteristics is observed at significantly low temperature (~180 K), the possibility of physi/chemisorption of OH− and H+ on individual atomic site52 cannot be ruled out. However, the independence of the anti-hysteretic behaviour to the ramp rate in VBG (Fig. S6 in the Supplementary Information) suggests a fundamentally different physical mechanism in our case.
The similarity of the transfer characteristics to that observed in the earlier studies of graphene transistors on STO substrate25,26 and also in the single/multilayer graphene on ferroelectric substrates27,28,29,30,31 strongly suggests that electric polarization at the surface gives rise to quantum confined states that trap, store and release charge from graphene periodically as VBG is swept back and forth. The temperature and sweep range dependence provide crucial insight into the energy and confinement scale of these states. Figure 2c shows the CNPs (VCNP) for varying sweep range ΔVBG of the back gate. The symmetric positions of the CNPs about VBG = 0 for the forward and reverse sweep directions eliminate oxygen vacancy-mediated anti-hysteretic transfer characteristics.53 In all devices, the (anti-)hysteresis becomes undetectable for ΔVBG ≲ 20 V, i.e., maximum |VBG| = 10 V, which is insensitive to temperature (for T ≲ 200 K). This indicates the energy of the localized trapping state (measured from the Dirac point), eV, where υF is the Fermi velocity. The inset of Fig. 2c confirms similar behaviour in a different device (D1).
The temperature dependence of the hysteresis (Fig. 2a) provides an estimate of the energy barrier to charge exchange between the substrate (STO) and graphene. To quantify this, we have plotted the difference in CNP (ΔVCNP) for the forward and the reverse sweep directions in Fig. 2d as a function of temperature. For large sweep range ΔVBG ≳ 100 V, the anti-hysteresis in both D1 (inset) and D2 vanishes at K, suggesting a confinement energy scale eV. At lower ΔVBG, the hysteretic behaviour vanishes at lower T, possibly due to lower magnitude of effective polarization due to remnant domains.
The temperature-dependent anti-hysteretic behaviour can arise from two possible mechanisms. First, the structural transition to the tetragonal phase at low temperatures is known to form domains in the near-surface region, causing rumpling of the surface. This may potentially cause trap states of possibly both structural (domain) and electrostatic (dipole moments) origin. Although the tetragonal domains have been observed to persist up to ~105 K, the temperature dependence of resistance in our case seems to indicate the structural transition to be limited below ~60 K (Fig. S3 in supplementary information). The structural origin is further unlikely because the temperature scale of disappearance of the anti-hysteresis is found to be strongly sweep range dependent, being ~30 K and >200 K (extrapolated) for sweep ranges of ±10 and ±40 V, respectively, in the same device (D2, Fig. 2d). Second, an alternative origin of the hysteretic behaviour can be traced to electrostatically confined trap states arising due to formation of surface dipoles. Our DFT calculations at the graphene–STO interface indicate a possible origin of such surface dipole moments which can be attributed to the movement of Ti and Sr atoms at the surface of STO (Fig. 3a–d). The DFT calculation was performed to estimate the surface polarization, following the formalism adopted by Vanderbilt et al.54 considering slab geometries of paraelectric/ferroelectric bulk compounds.
Two key aspects of the DFT calculations can be summarized as below (see Fig. S8 and associated discussions in the Supplementary Information for more details). First, the vertical displacement (Δz, shown in Fig. 3d) of Ti atoms in TiO2 layer and Sr atoms in SrO layer result in a formation of out-of-plane dipole moment on the surface of STO. The surface dipole moment of bare STO ( μC cm−2, in agreement with ref. 54) is significantly enhanced to μC cm−2 in the presence of graphene. This result is obtained by assuming an epitaxial registration between graphene and STO (model-1). Calculations were also carried out considering model-2, where the lattice parameters of graphene were kept intact. See Supplementary Information section for details. The polarization () calculated for model-1 and model-2 turned out to be −34.9 and −24 μC cm−2, respectively. Thus, the polarization computed from model-2 geometry gives better agreement to experimental value and that obtained from simple phenomenological model. Such enhancement is presumably caused by the rumpling of the surface TiO2 layer in the presence of graphene, as observed in DFT optimized structure. Second, the band gap at the STO surface eV is considerably smaller than the band gap of bulk STO eV (Fig. 3e). Notwithstanding the intrinsic underestimation of band gap in DFT due to over-screening problem,55 this indicates a gradual bending of the bulk bands to surface,56 as shown in the schematic of Fig. 3f.
The competing effects of band bending and electrostatic energy due to polarization at the surface can be combined to develop a phenomenological model for the observed anti-hysteretic behavior (Fig. 3f–h). A quantum well may be formed by the decrease in the band gap and the increase in the electrostatic potential ΔzP2Acell/2ε0εr at the surface due to the dipolar field, where Acell is the area of the TiO2 unit cell. Equating the latter to the confinement scale ΦP ≈ 0.02 eV, and assuming air gap between Ti and O atoms (εr = 1) at the surface, we get P ≈ 13 μC cm−2, which is similar to that obtained from DFT for bare STO, but smaller than expected from graphene–STO hybrid. DFT is well known to overestimate the polarization value even as much as by an order of magnitude, as observed in bulk materials.57 Thus, we consider the agreement between DFT and the value obtained experimentally to be reasonable. The expected trap layer energy , where eV (Fig. 3e) is the surface band gap, is also close to that (~0.15 eV) estimated experimentally, although the underestimation of the band gap in DFT limits the accuracy of such a comparison.
Figure 3g, h describes the anti-hysteresis process schematically. As the sweep range of VBG (ΔVBG) increases beyond Et, more charge carriers (electrons or holes) get trapped at the interface quantum well which increase the screening of VBG leading to an increase in anti-hysteresis (Fig. 2c). At higher temperature ≳200 K, the anti-hysteresis decreases as thermal energy of the trapped charge carriers becomes too large to remain confined by ΦP.
Unconventional low-frequency 1/f noise
In addition to the transport measurement, the low-frequency 1/f noise in the channel resistance is also sensitive to the interface dipoles. We assume trapping–detrapping noise to be the dominant mechanism for resistnce fluctuation, which is the case for graphene FETs on conventional substrates.37 In the presence of out-of-plane polarization P at STO surface, the interfacial potential barrier that determines the trapping–detrapping rate of charge across the interface, and hence the 1/f noise, is modified by the local effective electric field () (Fig. 4a, b). The typical time dependence of resistance fluctuations of the graphene channel is shown in Fig. 4d for two representative VBG, with a 1/f-like power spectral density (SR/R2) (Fig. 4e). The details of the noise measurement technique58,59 are discussed in the Methods section and Supplementary Information. Figure 4c, f correlates the variation in noise magnitude with VBG (Fig. 4f) with the anti-hysteretic behavior in the channel resistance R (Fig. 4c). We find that (obtained by integrating SR/R2 over the experimental frequency range) displays a strong (anti-)hysteretic two-state behaviour as a function of VBG. The top gate dependence of noise in the same graphene channel is non-hysteretic and exhibits conventional ‘V’-shaped behavior37,60 (Fig. S7 in the Supplementary Information section), confirming that the anti-hysteretic behaviour is due to surface electrical polarization on STO. Remarkably, the VBG dependence of collapses on a single trace as function of density n, irrespective of the sweep directions or temperature (Fig. 4g). Since , the monotonic change in noise across the Dirac point () indicates an unconventional microscopic origin that depends on the direction of , rather than just its magnitude.
When the STO surface is spontaneously polarized, the interface potential barrier naturally leads to correlated number-mobility fluctuation noise in the graphene channel37,38 that is sensitive to the direction of with respect to the dipole moment at the surface. Here, is the zero-field surface barrier for electron exchange. When the characteristic trapping time scale is distributed as ~1/τ,61 where , and are the tunnelling wave vector and the distance between the channel and surface states of STO substrate, respectively, one obtains
As shown in Fig. 4h, from the exponential fitting of the experimental noise magnitude with Eq. 2, we obtain C m by assuming nm for the experimental bandwidth. Here, is the effective mass of the electron in STO.62 Estimation of surface polarization through slab calculation14 yields μC cm−2, which is in good agreement to that obtained from the T dependence of anti-hysteresis (Fig. 2a).
In conclusion, we have shown that the dipole field at the surface of STO, created due to the off-centric movement of atoms at the TiO2-terminated surface, strongly impacts both transfer characteristics and low-frequency noise in the graphene-STO hybrid FETs. The key observation of temperature and back gate voltage sweep range-dependent anti-hysteretic transfer characteristics in both resistance and noise suggest formation of trap states at the STO surface due to band renormalization and electrostatic confinement. We quantitatively estimate surface polarization μC cm−2, which is in good agreement with DFT calculated polarization at graphene/STO interface. Our experiment will be useful in characterizing and exploiting interfaces of graphene and polarizable materials.
TiO2 surface termination of STO
The STO substrates were held with a teflon holder and ultrasonicated in ethanol, deionized (DI) water, buffered hydrofluoric acid and then again in DI water for 30 min in each of them. After cleaning, the STO substrates were placed in a tube furnace and annealed for 2.5 h in an oxygen flow of 300 cc min−1 at 960 °C. Then, the substrates were cooled down to room temperature naturally which generates TiO2 terminated surface63,64 on STO.
Device fabrication and measurements
Graphene and hBN layers were first exfoliated on SiO2 substrate by conventional micromechanical exfoliation. We used a drop of EL9 (baked at 80 °C for 2 h) placed on a transparent plastic sheet to lift suitable layers of graphene and hBN with appropriate orientation and sequence from SiO2 substrate at ~60 °C. For this, we have used a custom-made transfer set-up consisting of an optical microscope-based high-precision mechanical micromanipulator. Subsequently, the stack of 2D heterostructure attached to the EL9 was transferred on to STO surface at T > 100 °C, and the EL9 was dissolved away with acetone to obtain the required heterostructure. Since the EL9 does not come into contact with the graphene/STO or graphene/hBN interfaces at any stage of the fabrication process, the method leads to highly clean van der Waals interfaces.
Transport and noise measurements were performed using a lock-in amplifier while biasing the device in the ohmic regime. The noise in the graphene channel on STO was measured by calculating the Fourier transform of the auto-correlation function of resistance fluctuations, (=), where is the resistance averaged over the experimental time period. We simultaneously measured the time series data for both in-phase and out-of-phase component of the channel resistance, which give total noise and background noise respectively. By subtracting the background noise from the total noise, we get the sample noise. See the Supplementary Information section for details.
DFT calculations were performed within the framework of plane-wave basis set as implemented in VASP65,66 with projector augmented-wave potential.67,68 For details please see Supplementary Information section.
The data regarding experimental and theoretical matter that support the findings of this study are available from A.S. (email: email@example.com) and T.S.D. (email: firstname.lastname@example.org), respectively, upon reasonable request.
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The authors thank the Department of Science and Technology (DST) and The Netherlands Organisation for Scientific Research (NWO) for a funded project. A.S., T.P. and A.G. thank the Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science for providing National Nanofabrication (NNfC) and Micro and Nano Characterization Facility (MNCF).
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