## Abstract

The electrical characterisation of classical and quantum devices is a critical step in the development cycle of heterogeneous material stacks for semiconductor spin qubits. In the case of silicon, properties such as disorder and energy separation of conduction band valleys are commonly investigated individually upon modifications in selected parameters of the material stack. However, this reductionist approach fails to consider the interdependence between different structural and electronic properties at the danger of optimising one metric at the expense of the others. Here, we achieve a significant improvement in both disorder and valley splitting by taking a co-design approach to the material stack. We demonstrate isotopically purified, strained quantum wells with high mobility of 3.14(8) × 10^{5} cm^{2} V^{−1} s^{−1} and low percolation density of 6.9(1) × 10^{10} cm^{−2}. These low disorder quantum wells support quantum dots with low charge noise of 0.9(3) μeV Hz^{−1/2} and large mean valley splitting energy of 0.24(7) meV, measured in qubit devices. By striking the delicate balance between disorder, charge noise, and valley splitting, these findings provide a benchmark for silicon as a host semiconductor for quantum dot qubits. We foresee the application of these heterostructures in larger, high-performance quantum processors.

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## Introduction

The development of fault-tolerant quantum computing hardware relies on significant advancements in the quality of quantum materials hosting qubits^{1}. For spin qubits in gate-defined silicon quantum dots^{2}, there are currently three material-science-driven requirements being pursued^{3}. The first is to minimise potential fluctuations arising from static disorder in the host semiconductor, to ensure precise control of the charging energies and tunnel coupling between quantum dots, and to enable shared control in crossbar arrays^{4}. The second requirement is to reduce the presence of two-level fluctuators and other sources of dynamic disorder responsible for charge noise, which currently limits qubit performance^{5,6}. Lastly, it is crucial to maximise the energy separation between the two low-lying conduction valleys^{7}. Achieving large valley splitting energy prevents leakage outside the computational two-level Hilbert space and is essential to ensure high fidelity spin qubit initialisation, readout, control, and shuttling^{2,8,9,10,11,12}. Satisfying these multiple requirements simultaneously is challenging because the constraints on material stack design and processing conditions may conflict. In gate-defined silicon quantum dots, single electron spins are confined either at the semiconductor–dielectric interface in metal-oxide-semiconductor (Si-MOS) stacks or in buried strained quantum wells at the hetero-epitaxial Si/SiGe interface. In Si-MOS, the large electric field at the interface between the semiconductor and the dielectric drives a large valley splitting energy in tightly confined quantum dots^{13}. However, the proximity of the dielectric interface induces significant static and dynamic disorder, affecting mobility, percolation density, and charge noise^{14}. The latter can be improved through careful optimisation of the multi-layer gate stack resorting to industrial fabrication processes^{15}.

In conventional Si/SiGe heterostructures, a strained Si quantum well is separated from the semiconductor-dielectric interface by an epitaxial SiGe barrier^{3}. The buried Si quantum well naturally ensures a quiet environment, away from the impurities at the semiconductor-dielectric interface, leading to lower disorder and charge noise compared to Si-MOS^{16,17,18}. However, strain and compositional fluctuations in the SiGe strain-relaxed buffer (SRB) below the quantum well result in band-structure variations and device non-uniformity^{19}. Furthermore, valley splitting is limited and may vary from device to device^{20,21,22,23,24,25,26,27} due to the weaker electric field compared to Si-MOS^{28,29} and the additional in-built random alloy composition fluctuations at the strained Si-SiGe hetero-interface^{30}, posing a challenge for device reliability and qubit operation.

Practical strategies have been recently considered to enhance valley splitting in Si/SiGe quantum wells^{31}, including the use of unconventional heterostructures that incorporate Ge to the interior^{30,32,33,34} or the boundary of the quantum well^{35,36,37}. Without a co-design for high electron mobility, enhancing valley splitting, which requires breaking translation symmetry, tends to occur at the expense of a deteriorated disorder landscape, posing challenges for scaling to large qubit systems. Indeed, the few experimental reports^{16,34,38} of large valley splitting (e.g. >0.2 meV) in Si/SiGe quantum dots have shown relatively low mobility (<6 × 10^{4} cm^{2} V^{−1} s^{−1}) of the parent two-dimensional electron gas, thereby spoiling one major advantage of Si/SiGe over Si-MOS. A large valley splitting up to 0.239 meV has been measured in quantum wells incorporating an oscillating Ge concentration^{34}. However, the additional scattering from random alloy disorder yields an electron mobility of 2–3 × 10^{4} cm^{2} V^{−1} s^{−1}. This mobility is significantly lower than what is obtained with conventional Si/SiGe heterostructures^{39,40} and is even comparable to the mobility in the best Si-MOS stacks^{15}. Instances of large valley splittings (up to 0.286 ± 0.026 meV) within a wide distribution have also been measured in 3 nm ultra-thin quantum wells^{41}. Likewise, ultra-thin quantum wells may degrade mobility due to increased scattering from random alloy disorder as the wave function penetrates deeper into the SiGe barrier^{42}, potentially compounded by interface roughness as well^{43}. Conversely, very high mobility of 6.5 × 10^{5} cm^{2} V^{−1} s^{−1} was reported in conventional Si/SiGe heterostructures although the quantum dots showed rather low valley splitting in the range of 35–70 μeV^{25}.

In this work, we present significant advancements in isotopically purified ^{28}Si/SiGe heterostructures by conducting a study across multiple Hall bars and quantum dots in spin-qubit devices. We demonstrate simultaneous improvement in the channel static disorder, qualified by mobility and percolation density, and in the mean valley splitting while keeping respectable levels of low-frequency charge noise. These advancements are achieved without resorting to unconventional heterostructures. Instead, they result from explicitly accounting for the unavoidable broadening of Si-SiGe interfaces and optimising the quantum well thickness, while considering the design constraints imposed by the chemical composition of the SiGe buffer. Specifically, we ensure that the quantum well thickness is chosen to maintain coherent epitaxy of the strained Si layer with the underlying SiGe buffer while also minimising the impact of disorder originating from barrier penetration effects.

## Results

### Description of the heterostructures

The ^{28}Si/SiGe heterostructures are grown on a 100 mm Si(001) substrate by reduced-pressure chemical vapour deposition (“Methods”). From bottom to top (Fig. 1a), the heterostructure comprises a thick SiGe strained relaxed buffer (SRB) made of a step graded Si_{1−x}Ge_{x} buffer layer with increasing Ge concentration followed by a SiGe layer with constant Ge concentration, a tensile-strained ^{28}Si quantum well, and a SiGe barrier passivated by an amorphous Si-rich layer^{17}. Given the in-plane random distribution of Si and Ge at the interfaces between Si and SiGe layers, the description of a realistic Si quantum well may be reduced to the one-dimensional Ge concentration profile along the growth direction^{30,44}. This is modelled by sigmoidal interfaces^{44} (“Methods”) as in Fig. 1b and is characterised by three parameters: *ρ*_{b} is the asymptotic limit value of the maximum Ge concentration in the SiGe barriers surrounding the quantum well; 4*τ* is the interface width, which corresponds to the length over which the Ge concentration changes from 12% to 88% of *ρ*_{b}; *w* is the quantum well width defined as the distance between the inflection points of the two interfaces. Our growth protocol yields a reproducible quantum well profile with *ρ*_{b} = 0.31(1)^{30,45}, 4*τ* ≈ 1 nm, and *w* ≈ 7 nm (see Supplementary Figs. 1 and 2). The quantum well thickness was chosen on purpose to fall within the range of 5–9 nm, which correspond to the thicknesses of quantum wells studied in ref. ^{18} and used here as a benchmark. We expect a quantum well of about 7 nm to be thin enough to suppress strain-release defects and also increase the valley splitting compared to the results in refs. ^{5,30,45,46}. At the same time, the quantum well was chosen to be sufficiently thick to mitigate the effect of disorder arising from penetration of the wave function into the SiGe barrier^{42} and possibly from the interface roughness^{43}.

Figure 1d shows aberration corrected (AC) atomic resolution high-angle annular dark field (HAADF) scanning transmission electron microscopy (STEM) images and superimposed intensity profiles to validate the thickness of the ^{28}Si quantum well by counting the (002) horizontal planes as in ref. ^{18}. We estimate that the quantum well is formed by 26 atomic planes, corresponding to a thickness *w* = 6.9 ± 0.5 nm (see Supplementary Fig. 1). Further electron microscopy characterisation of all quantum wells considered in this study highlights the robustness of our growth protocol (see Supplementary Fig. 2). Images in Fig. 1d, e, acquired in HAADF (Z-contrast) and bright field (BF) STEM modes, respectively, highlight two critical characteristics of the compositionally graded SiGe layers beneath the quantum well. Firstly, the step-wise increase of the Ge content corresponds clearly to the varying shades of contrast in Fig. 1d. Secondly, strain-release defects and dislocations in Fig. 1e are confined at the multiple and sharp interfaces within the compositionally graded buffer layer, highlighting the overall crystalline quality of the SiGe SRB below the quantum well.

### Characterisation of strain distribution

After confirming the quantum well thickness, we examine the coherence of the Si quantum well epitaxy with the underlying SiGe and quantify the in-plane strain (*ϵ*) of the quantum well, along with the amplitude (Δ*ϵ*) of its fluctuations. Following the approach in ref. ^{47}, we employ scanning Raman spectroscopy on a heterostructure where the SiGe top barrier is intentionally omitted. Since this configuration maximises the signal from the thin strained Si quantum well, we are able to efficiently map the shift in Si-Si vibrations originating from both the Si quantum well (*ω*_{Si}) and from the SiGe buffer layer below (*ω*_{SiGe}) (see Supplementary Fig. 3). Figure 2a shows an atomic-force microscopy image of a pristine grown ^{28}Si/SiGe heterostructure over an area of 90 × 90 μm^{2}. The surface is characterised by a root mean square (RMS) roughness of ≈2.4 nm and by the typical cross-hatch pattern arising from the misfit dislocation network within the SiGe SRB. The cross-hatch undulations have a characteristic wavelength of ≈5 μm estimated from the Fourier transform spectrum.

The Raman map in Fig. 2b tracks *ω*_{Si} over an area of 40 × 40 *μ*m^{2}. This area is sufficiently large to identify fluctuations due to the cross-hatch pattern in Fig. 2a, with regions featuring higher and lower Raman shifts around a mean value of \({\overline{\omega }}_{{{{\rm{Si}}}}}=510.4(2)\) cm^{−1}. In Fig. 2c, we investigate the relationship between the Raman shifts from the quantum well *ω*_{Si} and from the SiGe buffer *ω*_{SiGe}. We find a strong linear correlation with a slope Δ*ω*_{Si}/Δ*ω*_{SiGe} = 1.01(2), suggesting that the distribution of the Raman shift in the Si quantum well is mainly driven by strain fluctuations in the SiGe SRB, rather than compositional fluctuation^{47}.

We calculate the strain in the quantum well using the equation *ϵ* = (*ω*_{Si} − *ω*_{0})/*b*_{Si}, where *ω*_{0} = 520.7 cm^{−1} is the Raman shift for bulk, relaxed Si and *b*_{Si} = 784(4) cm^{−1} is the Raman phonon strain shift coefficient of strained silicon on similar SiGe SRBs^{48}. From \({\overline{\omega }}_{{{{\rm{Si}}}}}\), we estimate the mean value of the in-plane strain for the quantum well \(\overline{\epsilon }=1.31(3)\)%. This value is qualitatively comparable to the expected value of ≈1.19(4)% from the lattice mismatch between Si and the Si_{0.69}Ge_{0.31} SRB (see Supplementary Note 2). A more quantitative comparison would require a direct measurement of *b*_{Si} on our heterostructures based upon high-resolution X-ray diffraction analysis across multiple samples with varying strain conditions. Figure 2d shows the normalised distribution of strain fluctuations percentage around the mean value \(\Delta \epsilon /\overline{\epsilon }=(\epsilon -\overline{\epsilon })/\overline{\epsilon }\). The data follows a normal distribution (black line) characterised by a standard deviation of 3.0(1)%, comparable with similar measurements in strained Ge/SiGe heterostructures^{49}. Given the significant correlation between Raman shifts in the quantum well and the SiGe buffer, alongside the measured strain levels exhibiting a narrow bandwidth of fluctuations, we argue that, with our growth conditions, the Si quantum well is uniformly and coherently grown on the underlying SiGe buffer. As a consequence, we expect strain-release defects in the quantum well to be very limited, if present at all.

### Electrical characterisation of heterostructure field effect transistors

We evaluate the influence of the design choice of a 7-nm-thick quantum well on the scattering properties of the 2D electron gas (2DEG) through wafer-scale electrical transport measurements. The measurements are performed on Hall-bar-shaped heterostructure field-effect transistors (H-FETs) operated in accumulation mode (“Methods”). Multiple H-FETs across the wafer are measured within the same cool-down at a temperature of 1.7 K using refrigerators equipped with cryo-multiplexers^{40}. Figure 3a, b show the mean mobility-density and conductivity-density curves in the low-density regime relevant for quantum dots. These curves are obtained by averaging the mobility-density curves from 10 H-FETs fabricated from the same wafer (solid line), and the different shadings represent the intervals corresponding to one, two, and three standard deviations. The distribution of mobility and conductivity is narrow, with a variance lower than 5% over the entire density range. Furthermore, we observe similar performance from H-FETs fabricated on a nominally identical heterostructure grown subsequently (see Supplementary Fig. 5), indicating the robustness of both our heterostructure growth and H-FET fabrication process. At low densities, the mobility increases steeply due to the increasing screening of scattering from remote impurities at the semiconductor–dielectric interface. This is confirmed by the large power law exponent *α* = 2.7 obtained by fitting the mean mobility-density curve to the relationship *μ* ∝ *n*^{α} in the low-density regime^{50}. At high density, the mobility keeps increasing, albeit with a much smaller power law exponent *α* = 0.3. This indicates that scattering from nearby background impurities, likely oxygen within the quantum well^{39}, and potentially interface roughness^{51} become the limiting mechanisms for transport in the 2DEG.

From the curves in Fig. 3a, b, we obtain the distributions of mobility *μ* measured at high density (*n* = 6 × 10^{11} cm^{−2}) and of the percolation density *n*_{p}, extracted by fitting (black line) to percolation theory^{52}. In Fig. 3c, d, we benchmark these metrics for the 6.9-nm-thick quantum well against the distributions obtained previously^{18} for a quantum well thickness of 5.3(5) and 9.0(5) nm. The 6.9 nm quantum well performs the best, with a mean mobility at high densities of *μ* = 3.14(8) × 10^{5} cm^{2 }V^{−1} s^{−1} and a percolation density of *n*_{p} = 6.9(1) × 10^{10} cm^{−2}.

The distributions show two noteworthy features: a 50% increase in mobility between the 5.3 and 6.9 nm quantum well and a threefold reduction in the variance of the distribution between the 9.0 nm quantum well and the remaining two. We attribute the mobility increase to reduced scattering from alloy disorder, as the wave function delocalises further into the quantum well rather than penetrating into the barrier^{42}. We attribute the large spread in transport properties of the widest quantum well to some degree of strain relaxation and associated defects^{18}. This explanation is further supported by comparative measurements of Raman shift correlation (see Supplementary Fig. 4) and highlights the sensitivity of the transport properties and their distributions to strain relaxation in the quantum well.

### Charge noise measurements in quantum dots

Moving on to quantum dot characterisation, we focus on the measurement of low-frequency charge noise using complete spin qubit devices cooled at the base temperature of a dilution refrigerator (“Methods”). The device design is identical to the one in refs. ^{53,54} and features overlapping gates for electrostatic confinement and micromagnets for coherent driving. We tune the sensing dot in the single electron regime, measure time traces of the source-drain current *I*_{SD} on a flank of a Coulomb peak, and repeat for several peaks before the onset of a background current. From the time-dependent *I*_{SD}, we obtain the current noise power spectral density *S*_{I} and convert to charge noise power spectral density *S*_{ϵ} using the measured lever arm and slope of each Coulomb peak (“Methods”). We confirm that chemical potential fluctuations are the dominant contributions to the noise traces by measuring the noise in the Coulomb blockade and on top of a Coulomb peak (see Supplementary Fig. 6)^{55}. The latter measurement also excludes that the noise traces have any relation to the change of noise floor of the current amplifier^{56}.

Figure 4a shows a representative noise spectrum. We observe an approximate 1/*f* trend at low frequency, suggesting the presence of an ensemble of two-level fluctuators (TLFs) with a wide range of activation energies^{57,58}. Notably, a kink appears at a specific frequency, which is attributed to the additional contribution in the power spectral density of a single TLF near the sensor^{15,55}. We fit this spectrum to a function which is the sum of a power law and a Lorentzian of the form \(\frac{A}{{f}^{\alpha }}+\frac{B}{f^{2}/{f}_{0}^{2}+1}\), where *A*, *B*, *α*, and *f*_{0} are fitting parameters. We extract *f*_{0} = 10.38(3) Hz, *α* = 1.66(2), and the power spectral density at 1 Hz *S*_{ϵ}(1 Hz) = 0.60(5) μeV Hz^{−1/2}. We repeat the analysis on a set of 17 noise spectra obtained from measurements of two separate devices (Supplementary Figs. 7 and 8). We do not observe a clear monotonic dependence of the noise spectra on the increasing electron occupancy in the quantum dots, in agreement with the measurement in ref. ^{18} for devices with a similar semiconductor-dielectric interface and a thinner (*w* = 5.3 nm) quantum well.

In Fig. 4b, we evaluate the noise power spectral density at 1 Hz \({S}_{\epsilon }^{1/2}(1\,\,{{{\rm{Hz}}}})\) to compare the performance of the 6.9(5) and the 5.3(5) nm quantum well. In addition to the different thickness of the quantum well, the devices on the 5.3 nm quantum well are defined by a single-layer of gates, whilst the devices on the 6.9 nm quantum well are complete qubit devices featuring three layers of overlapping gates, additional dielectric films in between, and micromagnets. The noise power spectral density in the multi-layer devices (purple) and single-layer devices (green) are similar, with \(| {S}_{\epsilon }| =0.9(3)\left.\right)\,\mu {{{{\rm{eVHz}}}}}^{-1/2}\) and ∣*S*_{ϵ}∣ = 0.9(9) μeV Hz^{−1/2}, respectively. Because both narrow quantum wells are fully strained, we expect the two heterostructures to contribute similarly to the electrostatic noise. Therefore, our measurements suggest that using multiple metallic gates, dielectric layers, and micromagnets does not degrade the noise performance in our devices. Our observations are consistent with previous measurements in Si/SiGe heterostructures at base temperature when impurities in the dielectric likely freeze out^{55,59}. We attribute this robustness to the distinctive characteristics of Si/SiGe heterostructures, where the active region of the device resides within a buried quantum well, well separated from the gate stack, unlike Si-MOS. We speculate that the metallic layers in the gate stack, positioned between the quantum well and the micromagnets, may shield the effects of additional impurities and traps in the topmost layers.

### Valley splitting measurements in quantum dots

To complete the quantum dot characterisation, we measure the two-electron singlet–triplet splitting *E*_{ST} in quantum dot arrays as in the six spin qubit devices described in ref. ^{5} by mapping the 1e → 2e transition as a function of the parallel magnetic field (*B*). *E*_{ST} is a reliable estimate of the valley splitting energy *E*_{V} in strongly confined quantum dots^{20,30,60,61} and is the relevant energy scale for spin-to-charge conversion readout with Pauli spin blockade^{5,62}.

Figure 5a shows a typical magnetospectroscopy map with a superimposed thin line highlighting the 1e → 2e transition at a given magnetic field (“Methods”). The thick line is a fit of the transition to the theoretical model^{30,61}, allowing us to estimate the singlet-triplet splitting *E*_{ST} = *g**μ*_{B}*B*_{ST}. Here, *g* = 2 is the electron gyromagnetic ratio, *μ*_{B} is the Bohr magneton, and *B*_{ST} corresponds to the magnetic field at which the energy of the 1e → 2e transition starts to decrease, signalling the transition from the singlet state *S*_{0} to the triplet state (*T*_{−}) as the new ground state of the two-electron system. For this specific quantum dot, we find *B*_{ST} = 1.77(2) T, corresponding to *E*_{V} = 0.205(2) meV.

Figure 5 b compares the valley splitting of spin qubit devices on the 6.9 nm quantum well (purple, see Supplementary Fig. 9) and on the 9.0 nm quantum well (blue) from ref. ^{5}. While the dots in all devices measured have the same nominal design and share the same fabrication process (“Methods”), the heterostructures further differ in the passivation of the SiGe top barrier. The heterostructure with the 6.9 nm well is passivated by an amorphous self-terminating Si-rich layer, while the 9.0 nm well has a conventional epitaxial Si cap^{17} (“Methods”). Passivation by a self-terminating Si-rich layer yields a more uniform and less noisy semiconductor-dielectric interface, which in turn promotes higher electric fields at the Si/SiGe interface^{17,18}. We observe a statistically significant 60% increase in the mean valley splitting in the 6.9 nm quantum well with an amorphous Si-rich termination, featuring a mean value of \(\overline{{E}_{{{{\rm{V}}}}}}=0.24\pm 0.07\) meV (see Supplementary Note 5). Furthermore, the distribution of valley splitting in devices with the wider quantum well shows instances of low values (e.g., *E*_{V} < 0.1 meV), as predicted by prevailing theory^{31}. In contrast, these instances are absent (although still predicted) in the measured devices with the narrower quantum well.

While we cannot pinpoint a single mechanism responsible for the increase in the mean value of valley splitting, we speculate that multiple factors contribute to this observed improvement. The tighter vertical confinement within the narrower quantum well^{41}, coupled with the relatively wide quantum well interface width, increases the overlap of the electron wavefunction with Ge atoms in the barrier. This amplifies the effect of random alloy disorder, which is known to increase valley splitting^{30,31}. Similarly, the improved semiconductor-dielectric facilitates tighter lateral and vertical confinement of the dots, which leads to a stronger electric field, contributing to drive the valley splitting^{28,29}. Furthermore, the near-absence (or at most very limited density) of strain-release defects in the thin quantum well ensures a smoother potential landscape, promoting improved electrostatic control and confinement of the dot. Additionally, we suggest that a larger amount of experimental data points is required to comprehensively explore the distribution of valley splitting in the 6.9 nm quantum well. Mapping of valley-splitting by spin-coherent electron shuttling^{63}, for example, could enable a meaningful comparison with existing theory^{31} and help determine whether the absence of low instances of valley splitting results from undersampling the distribution or is influenced by some other underlying factor.

## Discussion

In summary, we developed strained ^{28}Si/SiGe heterostructures providing a benchmark for silicon as a host semiconductor for gate-defined quantum dot spin qubits. Our growth protocol yields reproducible heterostructures that feature a 6.9-nm-thick ^{28}Si quantum well, surrounded by SiGe with a Ge concentration of 0.31 and an interface width of about 1 nm. These quantum wells are narrow enough to be fully strained and maintain coherence with the underlying substrate, displaying reasonable strain fluctuations. Yet, the quantum wells are sufficiently wide to mitigate the effects of penetration of the wave function into the barrier. Coupled with a high-quality semiconductor-dielectric interface, these ^{28}Si/SiGe heterostructures strike the delicate balance between disorder, charge noise, and valley splitting. We comprehensively probe these properties with statistical significance using classical and quantum devices. Compared to our control heterostructures supporting qubits, we demonstrate a remarkable 50% increase in mean mobility alongside a 10% decrease in percolation density while preserving a tight distribution of these transport properties. Our characterisation of low-frequency charge noise in quantum dot qubit devices consistently reveals low charge noise levels, featuring a mean value of power spectral density of 0.9(3) *μ*eV Hz^{−1/2} at 1 Hz. These heterostructures support consistently large valley splitting with a mean value of 0.24(7) meV. This is a significant advancement considering that instances of similarly large valley splitting were obtained previously on heterostructures with about one order of magnitude less mobility^{16,34,38}. We envisage that fine-tuning the distance between the quantum well and the semiconductor-dielectric interface, as well as the Ge concentration in the SiGe alloy, could offer avenues to further increase performance. Our findings highlight the significance of embracing a co-design approach to drive innovation in material stacks for quantum computing. As quantum processors mature in complexity, additional metrics characterising the heterostructures will likely need to be considered to optimise the design parameters and to fully leverage the advantages of the Si/SiGe platform for spin qubits.

## Methods

### Si/SiGe heterostructure growth

The ^{28}Si/SiGe heterostructures are grown on a 100-mm n-type Si(001) substrate using an Epsilon 2000 (ASMI) reduced-pressure chemical vapour deposition reactor. The reactor is equipped with a ^{28}SiH_{4} gas cylinder (1% dilution in H_{2}) for the growth of isotopically enriched ^{28}Si with 800 ppm of residuals of other isotopes^{14}. Starting from the Si substrate, the layer sequence of all heterostructures comprises a step-graded Si_{(1−x)}Ge_{x} layer with a final Ge concentration of *x* = 0.31 achieved in four grading steps (*x* = 0.07, 0.14, 0.21, and 0.31), followed by a Si_{0.69}Ge_{0.31} SRB. The step-graded buffer and the SRB are ≈3 μm and ≈2.4 μm thick, respectively. We grow the SRB at 625 °C, followed by a growth interruption and the quantum well growth at 750 °C^{30}. The various heterostructures compared in Fig. 3 of the main text differ in the thickness of the Si quantum well, which are 9.0(5), 6.9(5), and 5.3(5) nm. We change the thickness of the quantum well by only acting on the quantum well growth time and leaving all the other conditions unaltered. This yields heterostructures with similar interface widths (see Supplementary Figs. 1 and 2 and analysis in ref. ^{30}). On top of the Si quantum well, the heterostructure is terminated with a 30-nm-thick SiGe spacer, grown using the same conditions as the virtual substrate. The surface of the SiGe spacer is passivated with DCS at 500 °C before exposure to air^{17}. We confirm the Ge concentration in the spacer and virtual substrate via secondary ions mass spectrometry (similar to Supplementary Fig. 13 from ref. ^{30}) and quantitative electron energy loss spectroscopy.

### Raman spectroscopy

The two-dimensional Raman mapping follows a similar approach as in ref. ^{47}. We perform the measurements on heterostructures where we stop the growth after the quantum well and do not grow the SiGe spacer. This maximises the Raman signal coming from the Si quantum well. The measurements were performed with a LabRam HR Evolution spectrometer from Horiba-J.Y. at the backscattering geometry using an Olympus microscope (objective ×100 with a 1 μm lateral resolution). We use a violet laser (*λ* = 405 nm) and an 1800 gr/mm grating to achieve the highest spectral resolution. We focus the laser spot to have a spatial dimension of ≈ 1 μm. Given the laser wavelength, we expect to probe the Si quantum well and the SiGe SRB below (which has a uniform composition of Ge). We calibrate the Raman shift using a stress-free single crystal Si substrate with a Raman peak position at *ω*_{0} = 520.7 cm^{−1}. We use this value as a reference for the calculation of the strain of the Si quantum well.

### Device fabrication

The fabrication process for H-FETs involves reactive ion etching of mesa-trench and markers; selective P-ion implantation and activation by rapid thermal annealing at 700 °C; atomic layer deposition (ALD) of a 10-nm-thick Al_{2}O_{3} gate oxide; sputtering of Al gate; selective chemical etching of the dielectric with BOE (7:1) followed by electron beam evaporation of Ti:Pt to create ohmic contacts. All patterning is done by optical lithography on a four-inch wafer scale. Single and multi-layer quantum dot devices are fabricated on wafer coupons from the same H-FET fabrication run and share the process steps listed above. Single-layer quantum devices feature all the gates in a single evaporation of Ti:Pd (3:17 nm), followed by the deposition via ALD of a 5-nm-thick AlOx layer and consequent evaporation of a global top screening gate of Ti:Pd (3:27 nm). Multi-layer quantum dot devices feature three overlapping gate metallizations with increasing thickness of Ti:Pd (3:17 nm, 3:27 nm, 3:37 nm), each isolated by a 5-nm-thick AlOx dielectric. Finally, a last AlOx layer of 5 nm separates the gate stack from the micro-magnets (Ti:Co, 5:200 nm). All patterning in quantum dot devices is done via electron beam lithography.

### H-FET electrical characterisation

H-FET measurements are performed in an attoDRY2100 dry refrigerator equipped with cryo-multiplexer^{40} at a base temperature of 1.7 K^{17}. We operate the device in accumulation mode using a gate electrode to apply a positive DC voltage (*V*_{G}) to the quantum well. We apply a source-drain bias of 100 μV and use standard four-probe lock-in technique to measure the source-drain current *I*_{SD}, the longitudinal voltage *V*_{xx}, and the transverse Hall voltage *V*_{xy} as a function of *V*_{G} and perpendicular magnetic field *B*_{⊥}. From here, we calculate the longitudinal resistivity *ρ*_{xx} and transverse Hall resistivity *ρ*_{xy}. The Hall electron density *n* is obtained from the linear relationship *ρ*_{xy} = *B*_{⊥}/*e**n* at low magnetic fields. The electron mobility *μ* is extracted as *σ*_{xx} = *n**e**μ*, where *e* is the electron charge. The percolation density *n*_{p} is extracted by fitting the longitudinal conductivity *σ*_{xx} to the relation \({\sigma }_{xx}\propto {(n-{n}_{p})}^{1.31}\)^{52}. We invert the resistivity tensor to calculate the longitudinal (*σ*_{xx}) and perpendicular (*σ*_{xy}) conductivity.

### Low-frequency charge noise

We perform low-frequency charge noise measurements in a Bluefors LD400 dilution refrigerator with a base temperature of *T*_{MC} ≈ 20 mK. We use devices lithographically identical to those described in ref. ^{53}. We tune the sensing dot of the devices in the Coulomb blockade regime and use it as a single electron transistor (SET). We apply a fixed source–drain excitation to the two reservoirs connected to the SET and record the current *I*_{SD} as a function of time using a sampling rate of 1 kHz for 600 s. We measure *I*_{SD} on the flank of each Coulomb peak where ∣*d**I*_{SD}/*d**V*_{P}∣ is the largest, and therefore, the SET is the most sensitive to fluctuations. We check that chemical potential fluctuations are the dominant contributions to the noise traces by measuring the noise in blockade and on top of a coulomb peak (see Supplementary Fig. 6)^{55}. The latter also excludes that the noise traces have any relation to the change of noise floor of the current amplifier^{56}. We divide the time traces into ten segments of equal length and use the Fourier transform to convert the traces in the frequency domain. We average the ten different spectral densities to obtain the final current noise spectrum in a range centred to 1 Hz between 25 mHz and 40 Hz to avoid a strong interference around 50 Hz coming from the setup. We convert the current noise spectrum (*S*_{I}) in a charge noise spectrum (*S*_{ϵ}) using the formula^{18,55}:

where *a* is the lever arm and ∣*d**I*/*d**V*_{P}∣ is the slope of the specific Coulomb peak selected to acquire the time trace. We calculate the lever arm from the slopes of the Coulomb diamonds as \(a=| \frac{{m}_{{{{\rm{S}}}}}{m}_{{{{\rm{D}}}}}}{{m}_{{{{\rm{S}}}}}-{m}_{{{{\rm{D}}}}}}|\), where *m*_{S} and *m*_{D} are the slopes to source and to drain, and we estimate ∣*d**I*/*d**V*_{P}∣ from the numerical derivative of the Coulomb peak. We perform this analysis for every Coulomb peak and use the specific values of the lever arm and slope to calculate the charge noise spectrum.

### Valley splitting

We perform magnetospectroscopy experiments in quantum dot devices cooled in a dilution refrigerator with a base temperature of *T*_{MC} ≈ 10 mK. We use devices lithographically similar to those described in ref. ^{5}. We tune the quantum dots in the single-electron regime to isolate the 1e → 2e transition. We start the magnetospectroscopy measurement from the quantum dot closest to the sensing dot and use the remaining dots as an electron reservoir. We use the impedance of a nearby sensing dot to monitor the charge state of every quantum dot. The impedance of the sensing dot is measured using RF reflectometry. The signal is measured by monitoring the reflected amplitude of the RF readout signal through a nearby charge sensor. We use the amplitude (Device 1) and the Y component (Device 2) of the reflected signal to map the 1e → 2e transition. We fit the 1e → 2e transition as a function of the magnetic field with the relation^{30,61}:

where *α* is the lever arm, *V*_{P} is the plunger gate voltage, *E*_{ST} is the single-triplet energy splitting, *k* = *g**μ*_{B}*β*_{e}, *β*_{e} = 1/*k*_{B}*T*_{e}, *g* = 2 is the *g*-factor in silicon, *μ*_{B} is the Bohr magneton, *B* is the magnetic field, *k*_{B} is Boltzmann’s constant, and *T*_{e} is the electron temperature. *E*_{ST} is linked to the position of the kink (*B*_{ST}) in the magnetospectroscopy traces by the relation *E*_{ST} = *g**μ*_{B}*B*_{ST}.

### (Scanning) transmission electron microscopy

For structural characterisation with (S)TEM, we prepared lamella cross-sections of the quantum well heterostructures using a Focused Ion Beam (Helios 600 dual beam microscope). HR-TEM micrographs were acquired in a TECNAI F20 microscope operated at 200 kV. Atomically resolved HAADF-STEM data was obtained in a probe-corrected TITAN microscope operated at 300 kV. EELS mapping was carried out in a TECNAI F20 microscope operated at 200 kV with approximately 2 eV energy resolution and 1 eV energy dispersion. Principal Component Analysis (PCA) was applied to the spectrum images to enhance the signal-to-noise ratio.

## Data availability

All data included in this work are available from the 4TU.ResearchData international data repository at https://doi.org/10.4121/a4e3765b-9e32-492b-96fe-a9b760baef48.v2.

## Code availability

All the code used to derive the figures and analyse the data is included with the data and is available at 4TU.ResearchData international data repository at https://doi.org/10.4121/a4e3765b-9e32-492b-96fe-a9b760baef48.v2.

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## Acknowledgements

We acknowledge helpful discussions with Y. Huang, G. Capellini, G. Isella, D. J. Paul, M. Mehmandoost, the Scappucci group, the Vandersypen group and the Veldhorst group at TU Delft. We thank M. Friesen for valuable comments on the manuscript. We thank V. Pajcini for the Raman spectroscopy mapping and the useful discussion. This research was supported by the European Union’s Horizon 2020 research and innovation programme under the Grant Agreement No. 951852 (QLSI project) and in part by the Army Research Office (Grant No. W911NF-17-1-0274). The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the Army Research Office (ARO), or the U.S. Government. The U.S. Government is authorised to reproduce and distribute reprints for Government purposes, notwithstanding any copyright notation herein. ICN2 acknowledges funding from Generalitat de Catalunya 2021SGR00457. ICN2 is supported by the Severo Ochoa programme from Spanish MCIN/AEI (Grant No.: CEX2021-001214-S) and is funded by the CERCA Programme/Generalitat de Catalunya and ERDF funds from EU. Part of the present work has been performed in the framework of Universitat Autónoma de Barcelona Materials Science PhD programme. Authors acknowledge the use of instrumentation as well as the technical advice provided by the National Facility ELECMI ICTS, node “Laboratorio de Microscopias Avanzadas” at University of Zaragoza. M.B. acknowledges support from SUR Generalitat de Catalunya and the EU Social Fund; project ref. 2020 FI 00103. We acknowledge support from CSIC Interdisciplinary Thematic Platform (PTI+) on Quantum Technologies (PTI-QTEP+).

## Author information

### Authors and Affiliations

### Contributions

A.S. grew and designed the ^{28}Si/SiGe heterostructures with D.D.E., L.E.A.S., and G.S. A.S. and D.D.E. fabricated heterostructure field effect transistors measured by D.D.E. and L.E.A.S. M.B. and J.A. performed TEM characterisation. S.V.A., L.T., and S.K. fabricated quantum dot devices under the supervision of L.M.K.V. I.L.M., C.D., and M.M. measured the charge noise data under the supervision of M.V. O.G. and N.S. measured valley splitting. D.D.E. analysed the data. G.S. conceived and supervised the project. D.D.E. and G.S. wrote the manuscript with input from all authors.

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### Cite this article

Degli Esposti, D., Stehouwer, L.E.A., Gül, Ö. *et al.* Low disorder and high valley splitting in silicon.
*npj Quantum Inf* **10**, 32 (2024). https://doi.org/10.1038/s41534-024-00826-9

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DOI: https://doi.org/10.1038/s41534-024-00826-9