Introduction

With the explosive growth of data, brain-inspired (i.e. neuromorphic) computing systems have achieved significant improvements in parallel computing and efficient data processing1,2,3,4,5. In particular, binarized neural networks (BNNs) have recently demonstrated their capabilities in image recognition applications6,7,8,9,10. The accelerators in the BNNs perform a matrix "multiply accumulate" (MAC) operation (i.e. vector–matrix multiplication (VMM)) between the binarized weights and analog inputs6,7. The bitwise MAC operation enables extensive applicability to resource-constrained platforms, such as edge devices and mobile processors, promising a considerable reduction in memory (approximately 32 ×) and computation (approximately 2 ×) requirements compared with other neural networks6,7,8,9,10. Furthermore, it is still difficult for emerging synaptic devices to fully implement analog neural networks (analog input and analog weight) with nonlinear conductance changes and device variations1,2,3,4,11,12,13. However, digital synaptic devices are suitable for implementing BNNs because of their binarized weights13,14,15,16.

Various memory devices, such as resistive random-access memories (RRAMs), magnetoresistive RAMs (MRAM), flash-based memory devices, static RAMs (SRAM), and dynamic RAMs (DRAMs), have been widely researched for BNN implementation11,12,13,14,15,16,17,18,19,20,21. Their definite bistable characteristics, with a high on/off ratio and input/output linearity, are required for the implementation13,14,15. However, despite their improved characteristics, these devices still do not satisfactorily meet this requirement13,14,15,16,17. Moreover, as the number of hidden layers in the multilayer perceptron structure of neural networks increases, the neuron circuits that interconnect the pre- and post-layers become more complicated, which degrades the area and power efficiencies of computing systems based on neural networks21,22,23,24. The activation function of neuronal circuits is simplified or merged into a memory array to alleviate degradation25,26,27.

Recently, silicon diodes operating in a positive-feedback loop mechanism have demonstrated their feasibility as neuromorphic devices, owing to their superior electrical characteristics, high reliability, and reproducibility28,29,30,31,32. The positive-feedback loop mechanism enables diodes to exhibit steep switching and bistable characteristics with a high ON/OFF ratio32. Compared to other memory devices used as components of emerging BNNs11,12,13,14,15,16,17,18,19,20,21, the p+-n-p-n+ diodes operating by the positive-feedback loop mechanisms have a significant advantage in terms of reliability and endurance since the relatively low operating voltage prevents the deterioration of devices under sustained operations. Furthermore, the BNN comprising the p+-n-p-n+ diodes can be more simplified than those designed by SRAMs and DRAMs18,33. In this study, we demonstrate BNNs with 4 × 1 and 2 × 2 arrays, consisting of p+-n-p-n+ diodes.

Results

Optical images of the diode array and the p+-n-p-n+ diode in this array are shown in Fig. 1a. The bistable characteristic principle of the diode is illustrated in Fig. 1b with a diode schematic, energy-band diagrams in State 0 and State 1, and the red (blue) circuit symbol of State 0 (State 1). For the diode in the array, the gate voltage (VGate) controls the injection and accumulation of charge carriers by modulating the potential barrier in the n-doped region of the energy-band diagram. In State 0, excess charge carriers are absent in the potential wells in the n- and p-doped regions of the energy-band diagram, preventing the diode current (IDiode) from flowing in the diode. In contrast, in State 1, excess charge carriers accumulate in the potential wells in the n- and p-doped regions in the energy-band diagram, resulting in the IDiode to flow in the diode. Modulation of the potential barrier allowed the diode to exhibit bistable characteristics. However, for the BNN operation, the conductance in State 0 (State 1) corresponds to Weight 0 (1), and the anode voltage (VAnode) and VGate represent the input and weight voltages (VIN and VW), respectively.

Figure 1
figure 1

Optical images of (a) diode array with p+-n-p-n+ diode, and (b) diode schematic, energy-band diagrams in States 0 and 1, and red (blue) circuit symbol of State 0 (State 1). The n-doped region in the optical image is present beneath the yellow-colored gate electrode.

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Figure 2 shows the IDiode versus VIN curves for a diode at VW = 0.0 V and VW = 1.0 V. The BNN operating conditions are illustrated in the figure. As VIN increases from − 3 to 3 V (black curves), IDiode first remains at 0 mA, after which it abruptly increases at a VIN of 1.5 V for VW = 0.0 V and a VIN of 2.5 V for VW = 1.0 V. The generation of the positive-feedback loop leads to an abrupt increase in the IDiode. As VIN decreased from 3 to − 3 V (blue curves), IDiode linearly decreased and reached 0 mA near VIN = 1 V; the positive-feedback loop was eliminated near VIN = 1 V. The bistable characteristics are presented in the IDiode versus VIN curves, and the high ratio of the current magnitudes of States 1 and 0 is approximately 108 at a VW of 1.0 V for VIN = 2.0 V (see Supporting Information, Fig. S1). The unipolar switching (i.e. rectifying) characteristics inherit the electrical properties of the p–n diode. Regardless of VW, the IDiode versus VIN curve shape in State 1 resembles that of the rectified linear unit function used for the activation function of neural networks, including BNNs34,35,36.

Figure 2
figure 2

IDiode vs. VIN curves for a diode at (a) VW = 0.0 V and (b) VW = 1.0 V. The black and blue curves indicate the forward and reverse sweeps of VIN, respectively. The BNN operating conditions are shown in the figures.

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In Fig. 2a, the diode state becomes State 1 (State 0) by the potentiation (depression) at a VIN of 2.0 V (− 2.0 V), and VW of 0.0 V. The potentiated (depressed) diode weighed 1 (0). In Fig. 2b, the potentiated or depressed diode is in a standby state at VW = 1.0 V and VIN = 0.0 V. For a VIN range of 1.1 V to 2.0 V, the IDiode of the potentiated diode is linearly proportional to VIN, the IDiode of the depressed diode remains at a low level, and the difference in the IDiode of the potentiated and depressed diodes is used for the MAC operation.

To describe the BNN operation, the diode-array architecture, schematics, and circuit symbols of the p+-n-p-n+ diodes in the weight update, standby, and multiplication operations are shown in Fig. 3a–c. In the diode array, p+, n+, and gate electrodes were connected to the input lines (ILs), output lines (OLs), and weight lines (WLs), respectively. WLs and OLs were parallel to each other and perpendicular to ILs37,38,39. The multiplication of VIN and the conductance (i.e. weight) of a diode using Ohm’s law produced IDiode, and the summation of IDiode at each common OL (i.e. the same row in the diode array) using Kirchhoff’s law yielded the output current (IOUT). Thus, the diode-array architecture can perform parallel MAC operations. For the BNN operations, the VIN for IL, VW for WL, and IOUT for OL signals represent the input, weight update selection, and output, respectively.

Figure 3
figure 3

Diode-array architecture, schematics, and circuit symbols of diodes in (a) weight update, (b) standby, and (c) multiplication operations. Colored boxes with W and IN mean the peripheral parts of the weight and input lines (WLs and ILs), respectively.

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In the weight update operation in Fig. 3a, the binarized weight (W) matrix is updated by both VIN (2.0 V or − 2.0 V) and VW (0.0 V). The diodes selected in the array with VW = 0.0 V were potentiated (depressed) at VIN of 2.0 V (− 2.0 V). In the standby operation shown in Fig. 3b, all VW and VIN are 1.0 V and 0.0 V, respectively. The diodes maintained their memory states with extremely low IDiode. In the multiplication operation shown in Fig. 3c, the VW (1.0 V) and VIN (0.0 V or from 1.1 V to 2.0 V) are applied to the diode array. IDiode represents the output of the product of VIN and the binarized weight, and IOUT is obtained from the summation of the IDiode.

Figures 4 shows the BNN operation and IDiode versus VIN characteristics of the selected diode in an array. In Fig. 4a, for potentiation (depression), voltage pulses with VIN = 2.0 V (− 2.0 V) and VW = 0.0 V were applied to the diode. After the potentiation, the IDiode is linearly proportional to the multipulse and staircase waveforms of VIN ranging from 1.1 to 2.0 V in steps of 0.1 V. In contrast, after the depression, the IDiode remained at a low level despite the same VIN pulses as the potentiation. During the standby operation between the VIN pulses, the diode memorized the weight with a power consumption of approximately 0 W. In Fig. 4b, the extracted IDiode values of the potentiated diode for each VIN pulse can be expressed as a linear function of VIN, as follows:

Figure 4
figure 4

BNN operation of a diode. (a) IDiode for potentiated and depressed diodes and (b) IDiode vs. VIN diode characteristics of potentiated diode. Here, the R-square value of the linear fit is 0.99986, which means that the diode features high linearity.

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$${I}_{{\text{Diode}}} \left({V}_{{\text{IN}}}\right)=7.4\times \left({V}_{{\text{IN}}} -1\right).$$
(1)

Here, the coefficient 7.4 represents the conductance of the potentiated diode (i.e. Weight 1). For the depressed diode (i.e. Weight 0), the conductance is close to 0, and the IDiode remains at a low level during multiplication after depression. The constant term – 1 indicates the lower limit of the VIN range for diode multiplication. This expression implies that the single diode performs multiplication between VIN and weight with outstanding linearity.

The bitwise MAC operation of the BNN in a 4 × 1 diode array is illustrated in Fig. 5. The MAC operation was conducted by multiplying the input VINn and binarized weight Wn for each nth diode. In a 4 × 1 diode array in Fig. 5a, IOUT can be expressed as

Figure 5
figure 5

BNN operation of 4 × 1 diode array. (a) Circuit diagram of array, (b) experimental data of bitwise MAC operation, and (c) calculated data of bitwise MAC operation. Here, all VIN (VIN1–VIN4) are identical.

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$${I}_{{\text{OUT}}}=\sum_{n=1}^{4}{{\text{W}}}_{{\text{n}}}\times {V}_{{\text{INn}}}.$$
(2)

The experimental data for the MAC operation are shown in Fig. 5b. All VIN were applied in the same waveforms as those in Fig. 4a. Wn is updated before the MAC operation, and IOUT remains linearly proportional to the multipulse and staircase waveforms of VIN. Moreover, IOUT is linearly proportional to the number of potentiated diodes for the same VIN pulse, and there are few electrical variations between the component diodes in the array, owing to the wafer-scale full CMOS process. Here, the product of VInn and Wn can be replaced with the IDiode in Eq. (1). Thus, Eq. (2) becomes

$${I}_{{\text{OUT}}}={I}_{{\text{Diode}}}\times {\text{n}}, \mathrm{where \,\,n}=\#\mathrm{ of \,\,potentiated \,\,diodes}.$$
(3)

The MAC operation data (obtained from Eq. (3)) plotted in Fig. 5c were in good agreement with the experimental data in Fig. 5b. The uniformity of the component diodes in the array can minimize the BNN computational errors39,40,4142. Thus, a massive array architecture comprising gated p+-n-p-n+ diodes can be realized with a high ratio of the bistable current magnitude to uniformity.

A 2 × 2 diode array is used to perform the matrix MAC operation of the BNN, as shown in Fig. 6. The binarized weights of the diodes in Fig. 6a are the components of the W matrix \(\left[\begin{array}{cc}{{\text{W}}}_{11}& {{\text{W}}}_{12}\\ {{\text{W}}}_{21}& {{\text{W}}}_{22}\end{array}\right]\), where IOUT1 (\({I}_{{\text{Diode}}}\times {\text{n}}={{\text{W}}}_{11}\times {V}_{{\text{IN}}1}+{{\text{W}}}_{12}\times {V}_{{\text{IN}}2}\)) and IOUT2 (\({I}_{{\text{Diode}}}\times {\text{m}}={{\text{W}}}_{21}\times {V}_{{\text{IN}}1}+{{\text{W}}}_{22}\times {V}_{{\text{IN}}2}\)) are obtained via the OLs, and n(m) is the number of potentiated diodes in the first (second) row in the array. In this array, the IN-vector component IN1 or IN2 is 0 (if VIN is 0.0 V) or 1 (if VIN is from 1.1 V to 2.0 V), and the OUT-vector component OUT1 (OUT2) is n (m). Thus, the matrix MAC operation can be expressed as \(\left[\begin{array}{cc}{{\text{W}}}_{11}& {{\text{W}}}_{12}\\ {{\text{W}}}_{21}& {{\text{W}}}_{22}\end{array}\right]\left[\begin{array}{c}{{\text{IN}}}_{1}\\ {{\text{IN}}}_{2}\end{array}\right]= \left[\begin{array}{c}{{\text{OUT}}}_{1}\\ {{\text{OUT}}}_{2}\end{array}\right]\), which represents the VMM between the weight matrix and input vector, W \(\cdot\) INT = OUTT.

Figure 6
figure 6

BNN operation of 2 × 2 diode array. (a) Circuit diagram of array and (b) matrix MAC operation with fixed W matrix and IN vector. Here, VIN1 and VIN2 are identical.

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The voltage pulses of VIN (2.0 V or − 2.0 V) and VW (0 V) are applied to the diode array to update the W matrix, as shown in Fig. 6a. In Fig. 6b, the 2 × 2 diode array performs the matrix MAC operation in the W = \(\left[\begin{array}{cc}1& 1\\ 1& 0\end{array}\right]\) case among the 16 different W cases (see Fig. 7 for other W cases). W is updated to the W = \(\left[\begin{array}{cc}1& 1\\ 1& 0\end{array}\right]\) case, after which VIN1 and VIN2 are applied to the same waveforms depicted in Fig. 4a for the matrix MAC operations. Thus, IOUT1 was twice as large as IOUT2. Consequently, the diode array exhibits a simplified VMM of \(\left[\begin{array}{cc}1& 1\\ 1& 0\end{array}\right]\left[\begin{array}{c}1\\ 1\end{array}\right]= \left[\begin{array}{c}2\\ 1\end{array}\right]\).

Figure 7
figure 7

Matrix MAC operations of 2 × 2 diode array for (a–f) six different W cases with fixed IN vector. The other cases are excluded because their results of the matrix MAC operations are the same as these six cases.

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In Fig. 7, we demonstrate the matrix MAC operations of the 2 × 2 diode array for six different W values. The IN-vector components IN1 and IN2 are both 1, where IOUT1 and IOUT2 correspond to the outputs OUT1 and OUT2 of the matrix MAC operation for each W case, respectively. Here, VIN1 and VIN2 are applied to the same waveforms as those in Fig. 4a. IOUT1 and IOUT2 in Fig. 7e are identical to those in Fig. 6c. For each W case, the output of the matrix MAC operation has a high concordance with the simplified VMM equation in each figure owing to the high uniformity of the diodes.

For the W matrix \(\left[\begin{array}{cc}1& 1\\ 1& 0\end{array}\right]\) in Fig. 8a, the OUT-vector components OUT1 and OUT2 vary with the IN-vector components IN1 and IN2, which are highly concordant with the simplified VMMs in Fig. 8b. IOUT1 and IOUT2 depend on the number of potentiated diodes in the array and the multipulse and staircase waveforms of VIN1 and VIN2. After multiplication, the diode array maintains the binarized weight matrix owing to the nondestructive readout characteristics of the component diodes43. Instead, the component diodes refresh their weights during multiplication operations. They also exhibit superior electrical stability against bias stresses (continuous input pulses), unlike other memory devices13,19,20,21,44,45. The diode array holds the binarized weight matrix semi-permanently using refresh operations while performing multiplication operations. Moreover, the binarized weights are not updated unless VIN and VW are applied simultaneously. The binarized weight matrix did not change for multiplication. However, for the weight update operations, the matrix is determined by VW1 and VW2.

Figure 8
figure 8

Matrix MAC operations of 2 × 2 diode array with fixed W matrix. (a) Circuit diagram of array and (b) matrix MAC operations for four different IN vectors. The W matrix is updated before the matrix MAC operations.

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Discussion

We demonstrated the BNN operation of an array composed of p+-n-p-n+ diodes with bistable characteristics. The component diode exhibited inherent unipolar switching characteristics, and the array was immune to sneak path problems, unlike previously proposed BNNs11,12,13,16,43. In addition to the outstanding bistable characteristics with a high current ratio (approximately 108), the rectifying characteristics can simplify peripheral neuron circuits. Moreover, the simplified peripheral neuron circuits help to reduce the burden of area and power consumption for BNN-based computing systems. The diode array performed matrix MAC operations with high concordance with the VMM between the binarized weight matrix and input vector. Furthermore, the diode array exhibited nondestructive readout and semi-permanent holding characteristics. Our diodes can realize the compact synaptic array in which the cell is composed of a single device with 6F2 (F = feature size) as well as operate at relatively low voltages (≤ 2 V). Consequently, p+-n-p-n+ diodes are the most suitable building blocks for area-/energy-efficient and reliable synaptic arrays in BNN.

Methods

Device fabrication

The p+-n-p-n+ diodes were fabricated using full CMOS processes from a p-type (100)-oriented silicon-on-insulator wafer with a 340-nm thick top Si layer on a 2-μm thick buried oxide layer. First, the wafer was cleaned by standard clean-1 and 50:1 diluted HF to remove particles or impurities. A 10-nm thick SiO2 layer was grown on the Si surface as a sacrificial layer to minimize channeling and damage to the channel during ion implantation by dry oxidation (800 °C, 200 min). The n-doped regions were formed using a conventional ion implantation process, in which P+ ions were implanted at a dose of 3 × 1013 cm−2 with an ion energy of 60 keV. Subsequently, the wafer was annealed at 1100 °C for 30 min under ambient nitrogen. The 25-nm thick SiO2 layers were thermally grown as the gate dielectric for the gated p+-n-p-n+ diodes by dry oxidation (850 °C, 270 min). A 400-nm thick and 1.5-μm wide poly-Si gate electrode was formed by low-pressure chemical vapor deposition (LPCVD), followed by photolithography, and a dry etching process was used to delineate the gate profile. The lightly doped drain extension regions were implanted with \({\text{BF}}_{2}^{+}\) ions at a dose of 1 × 1012 cm−2 and an ion energy of 10 keV. And then LPCVD-based tetraethyl orthosilicate (TEOS) was used to form the 200-nm thick gate sidewall spacers. For the p-doped regions, \({\text{BF}}_{2}^{+}\) ions at a dose of 3 × 1013 cm−2 were implanted at an ion energy of 40 keV. The n+ cathode, heavily n-doped poly-Si gate, and p+ anode regions were formed by masked ion implantation (P+ at 3 × 1015 cm−2, 50 keV and \({\text{BF}}_{2}^{+}\) at 3 × 1015 cm−2, 30 keV). Thereafter, the wafer was annealed at 1000 °C for 30 min in ambient nitrogen, followed by rapid thermal annealing at 1050 °C for 30 s to activate the implanted dopants with uniform diffusion and eliminate defects. The dual-step annealing process was carried out to form the p+-n-p-n+ doping structure. Finally, a Ti/TiN/Al/TiN metal alloy was deposited in the drain, source, and gate contact regions after deposition of a 700-nm thick interlayer dielectric layer (for device protection) using the LPCVD-based TEOS.

Measurement

All electrical data were acquired at room temperature using a semiconductor parameter analyzer (HP4155C, Agilent Technologies) and Keithley 2636A and 2636 B source meters. The input-pulse width for the diode and MAC array operations was selected as 1 ms because of the limitations of the Keithley source meters. The experimental set-up to examine the BNN operations of the diode array is shown in Fig. S2 of supporting information.